JP4403288B2 - Regulator circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to voltage regulators and power supply control ICs for various electronic devices, and more particularly to voltage regulators and power supply control ICs used as power supplies for portable devices and the like.
[0002]
[Prior art]
In recent years, various portable devices typified by mobile phones and video cameras are on the market. Since these portable devices are driven by a battery power source, they are required to be small, light, and have low power consumption.
Among the circuits that make up these portable devices, the regulator circuit that supplies a constant voltage has the above requirements and the characteristics that the regulator circuit compresses the ripple voltage against the ripple voltage superimposed on the power supply with a small number of parts, A so-called power supply ripple rejection rate is required to be large. For this reason, a series regulator circuit is mainly used as a constant voltage circuit for portable devices.
[0003]
FIG. 4 shows an example of a series regulator circuit 2 according to the prior art. In FIG. 4, a regulator circuit 2 receives a reference voltage generation circuit VR, and a negative feedback signal Vf obtained by dividing the output voltage V0 of the regulator circuit 2 by resistors R2 and R3, receiving the reference voltage Vref of the reference voltage generation circuit VR. An operational amplifier Q1 that amplifies the difference between the two and a source electrode that amplifies the operational amplifier output V1 are connected to a power supply 0V (Vss), a drain circuit has a resistor R1, and a level shift operation is performed to connect an intermediate amplifier circuit Amp. The first N-channel field effect transistor T1 (hereinafter referred to as Nch-FET- (Tx; Tx is abbreviated as a member number)) to be formed, and the intermediate amplifier circuit output V2 are connected to the power source voltage Vdd to connect the source electrode to the drain circuit A voltage dividing circuit of the resistors R2 and R3 forming a negative feedback circuit, and a first P-channel field effect transistor T3 (hereinafter abbreviated as Pch-FET-T (x)) for connecting the load circuit L. Configured.
[0004]
With this configuration, in a steady state, the Pch-FET-T3 supplies current to the load circuit L and the voltage dividing circuit of the resistors R2 and R3. In addition, a capacitor C is connected in parallel to the load circuit L, functions to absorb the ripple component of the output voltage V0, and is charged up to the load voltage V0. Further, the feedback voltage Vf divided by the resistors R2 and R3 is negatively fed back to the operational amplifier Q1, and is equal to the input reference voltage Vref, that is, the output voltage V0 of the regulator circuit 2 is the reference voltage. Negative feedback control is performed to equal Vref × (1 + R2 / R3).
[0005]
Next, when the load current IL to the load circuit L increases, the output voltage V0 decreases, and therefore the divided voltage Vf of the voltage dividing circuits R2 and R3 also decreases, so the output voltage V1 of the operational amplifier Q1 increases. The gate voltage of Nch-FET-T1 increases, and the drain current of Nch-FET-T1 increases. As a result, the source-gate voltage of Pch-FET-T3 also increases, the drain current of Pch-FET-T3 increases, and the negative feedback operation works so that the output voltage V0 maintains the steady output voltage state. . That is, the series regulator circuit 2 operates in such a manner that the change of the output voltage V0 due to the increase or decrease of the load current is the same as that in the steady state and the original output voltage V0 is maintained by adopting a negative feedback circuit configuration.
[0006]
However, in Pch-FET-T3, the field-effect transistor T3 has a very large shape dimension in order to minimize the output voltage drop at the rated load current. As a result, the saturation output current of the Pch-FET-T3 itself is generally designed so that a current several tens of times the rated load current can flow.
However, due to a failure in the load circuit of this series regulator, for example, a short circuit accident of the load circuit L, a short circuit between the wirings of the load circuit L, or a short circuit breakage within the capacitor C, the output voltage circuit becomes the power supply 0V circuit Vss. As shown in FIG. 5 to be described later, an excessive current IL continues to flow from the power supply Vdd to the power supply 0V circuit Vss. As a result, heat is generated. In the worst case, there is a risk of smoke and fire.
[0007]
5, (A) of FIG. 5 shows the case where the output voltage V0 is taken on the horizontal axis and the output current IL is taken on the vertical axis. For example, the output voltage V0 = 3V and the rated load current IL = 1x. In this case, when the load resistance L becomes smaller than the rated value, the load current IL increases beyond the rated value (1x), but the output voltage V0 maintains approximately 3V. When the load resistance L is further reduced and the load current IL increases to more than twice the rated value (1x), the Pch-FET-T3 enters the saturated output current state, and the loop gain of the negative feedback circuit due to the saturation of the Pch-FET-T3 Due to the decrease, the constant voltage characteristic of the output voltage V0 cannot be maintained, and the voltage V0 drops. The maximum power consumption of the field effect transistor T3 forming the output stage is when the load resistance L is short-circuited. For example, when the maximum load current IL at the time of short-circuit in the illustrated example is (2.5x) of the rated value (1x), Vdd) x (2.5x), and there is a danger of thermal destruction of Pch-FET-T3 and its peripheral parts. FIG. 5B shows the start-up characteristic of this series regulator, and the output voltage rise characteristic tr rises in about several μsec.
[0008]
Next, a conventional series regulator circuit 3 incorporating a load short-circuit protection circuit will be described with reference to FIGS. In FIG. 6, the regulator circuit 3 has the following three changes / additions to the regulator circuit 2 described in FIG. (1) An intermediate amplifier circuit Amp composed of a resistor R1 and an Nch-FET-T1 is commonly used as a first Nch-FET-T1 having a large output current capacity and a second Nch-FET- having a small output current capacity. T2 and switch element SW that switches the amplified output of both Nch-FET-T1 and T2, and the amplified output current of one of Nch-FET-T1 and T2 via this switch SW is the voltage from power supply voltage Vdd An intermediate amplifier circuit Amp having output limiting means consisting of a resistor R1 that detects the drop; and
(2) The second Pch, which detects this intermediate amplifier output V2, connects the gate electrode to the intermediate amplifier output V2, connects the source electrode to the power supply voltage Vdd, and connects the resistor R4 between the drain electrode and the power supply 0V. -FET-T4, the third Nch-FET-T5 connected to the drain electrode of this second Pch-FET-T4 with the gate electrode and drain electrode short-circuited, the source electrode connected to the regulator circuit output V0, and the source electrode Connected to the regulator circuit output V0 and connected between the fourth Nch-FET-T6 whose gate electrode is connected to the gate electrode of the third Nch-FET-T5, and the drain electrode of this fourth Nch-FET-T6 and the power supply voltage Vdd And a third Pch-FET-T7 that forms a clamp circuit by connecting the source electrode and the gate electrode to both ends of the resistor R5, and connecting the drain electrode to the intermediate amplifier circuit output V2, respectively. A first output limiting circuit Clamp configured;
(3) an overload detection circuit (comparator Q2) that detects a decrease in the output voltage V0 of the output circuit, outputs a control signal V4 to the output limiting means, and performs an overload protection operation;
It is in the point comprised with.
[0009]
With this configuration, when the load resistance L decreases and the output circuit enters an overload state, the regulator circuit output V0 operates in the following three ways depending on the load state as the output voltage V0 decreases. That is,
(A) In the rated load range or a range slightly exceeding this, the forward-amplifier circuit composed of the operational amplifier Q1, the intermediate amplifier circuit Amp, and the Pch-FET-T3 constituting the output circuit is not saturated. Since the negative feedback loop is configured with a high loop gain, the output VO of the regulator circuit 3 can hold a constant value.
[0010]
(B) Next, the operation of the first output limiting circuit Clamp will be described. When the load current increases beyond the rated value, the output V2 of the intermediate amplifier circuit decreases its output value to keep the output VO of the regulator circuit 3 constant, and the source gate of the Pch-FET-T3 of the output circuit Increase load voltage to increase load voltage. However, this intermediate amplifier circuit output V2 is connected to the gate of the second Pch-FET-T4 constituting the first output limiting circuit Clamp on the other side, and since this potential V2 drops, the drain current of the second Pch-FET-T4 increases. Therefore, the gate potentials of the third Nch-FET-T5 and the fourth Nch-FET-T6 connected to the drain of the second Pch-FET-T4 increase, and the output V0 is connected to the output circuit V0 as the load current increases. The difference voltage between the source electrodes of the third Nch-FET-T5 and the fourth Nch-FET-T6 and the increased gate potential increases, and the drains of the third Nch-FET-T5 and the fourth Nch-FET-T6 tend to decrease. Increase current. As a result, when the drain current of the fourth Nch-FET-T6 increases, the voltage drop of the resistor R5 increases, and the resistance value between the source and drain of the third Pch-FET-T7 decreases. Since the resistance between the source and drain of the third Pch-FET-T7 is inserted in parallel with the resistance R1 of the intermediate amplifier Amp, the drain current of the fourth Nch-FET-T6 exceeds a predetermined value. Therefore, the output V2 of the intermediate amplifier circuit Amp is clamped to a constant value. Therefore, the output voltage V0 drops in this load current range.
[0011]
(C) Next, the operation of the output limiting means will be described. When the load current IL further increases from the value described above, the output voltage V0 drops below the reference voltage Vref in the illustrated example. At this time, the overload detection circuit (comparator Q2) compares the reference voltage Vref with the output voltage V0 and outputs the control signal V4, switches the switch element SW, and switches the intermediate amplifier circuit Amp to the first output current capacity smaller. Switch to 2Nch-FET-T2. As a result, the output V2 of the intermediate amplifier circuit Amp shifts the potential on the power supply voltage Vdd side, and the voltage between the source and gate of the Pch-FET-T3 constituting the output circuit decreases, so the output voltage V0 decreases rapidly. .
[0012]
The operation of the output V0 of the regulator circuit 3 is illustrated in FIG. In FIG. 7, the horizontal axis represents voltage and the vertical axis represents current. In the illustrated example, the output V0 of the regulator circuit 3 is controlled to 3 V, and the output current is the rated value (1x). The above-mentioned (A) operation within the rated load range is illustrated by the symbol A in FIG. 7, (B) the operation range of the first output limiting circuit is illustrated by the symbol B, and (C) the operation region of the output limiting means is denoted by the symbol. This is indicated by C. FIG. 8 illustrates the starting characteristics of the regulator circuit 3. The horizontal axis represents time and the vertical axis represents voltage. In the regulator circuit 3, the smoothing circuit capacitor C is connected in parallel to the load circuit L. Therefore, when the power supply is turned on and started, the output current IL of the regulator circuit 3 is supplied to the capacitor C in the initial startup state. Current is equivalent to the load short circuit condition. Therefore, the regulator circuit 3 is in the operating state of the (C) output limiting means described above. Therefore, even when the load circuit L is within the rated range, the capacitor C is charged with a small output current shown by the symbol C in FIG. 7, and this output voltage is used as the reference voltage Vref of the overload detection circuit (comparator Q2). When exceeded, the operation of the output limiting means is turned off, (B) the operation mode of the first output limiting circuit is entered, the capacitor C is rapidly charged with this large output current, and (A) within the rated load range. Can enter constant voltage operation. In this start-up characteristic, (C) since the operation state of the output limiting means is surely passed, it takes about 30 μsec for the regulator circuit 3 to rise and start constant voltage operation.
[0013]
[Problems to be solved by the invention]
As described above, in the conventional regulator circuit, if the power supply current when the load is short-circuited is reduced, the output current is limited when the output voltage is lower than the reference voltage. There is a problem that it takes time to charge the attached capacity and the rise time is delayed. For example, when a regulator circuit is frequently turned ON / OFF to reduce current consumption, such as a mobile phone, if the rise time is slow, the mobile phone is difficult to use, and the power supply is turned on early. There is a need.
[0014]
The present invention has been made in view of the above points, and an object of the present invention is to solve the above-described problems and provide a regulator circuit having a good power supply start-up characteristic while ensuring the effect of reducing current consumption. There is.
[0015]
[Means for Solving the Problems]
According to the present invention, the regulator circuit includes a reference voltage generation circuit, an operational amplifier that receives the reference voltage of the reference voltage generation circuit and amplifies the difference between the negative feedback signal, and amplifies the output of the operational amplifier. An intermediate amplifier circuit having output limiting means for switching the output range of the amplified output to limit the overload current, an output circuit for amplifying the output of the intermediate amplifier circuit and supplying power to the load, and dividing the output to A voltage dividing circuit that supplies a negative feedback signal to the operational amplifier, and an overload detection circuit that detects a decrease in the output voltage of the output circuit and outputs a control signal to the output limiting means to perform an overload protection operation , In the output circuit, the source electrode of the first P-channel field effect transistor is connected to the power supply voltage Vdd, the gate electrode is connected to the output of the intermediate amplifier circuit, and the drain electrode is used as the regulator circuit output. Connected to the serial load, said regulator circuit further wherein detecting the intermediate amplifying circuit output, wherein a first output limiting circuit for suppressing clamp a change in the intermediate amplifying circuit output based on the intermediate amplifying circuit output, the regulator circuit And a delay circuit that delays an enable signal that activates the AND, and an AND element that takes a logical product of the enable signal delayed by the delay circuit and a control signal from the overload detection circuit.
[0016]
With this configuration, when the enable signal is turned on to start the regulator circuit, the control signal to the output limiting means is blocked during the period until the enable signal is delayed and output by the delay circuit, The load protection circuit operation can be interrupted.
The intermediate amplifier circuit having output limiting means includes a first N-channel field effect transistor Nch-FET having a large output current capacity, a second Nch-FET having a small output current capacity, and a switch for switching the amplified outputs of both Nch-FETs. And a resistor that detects the amplified output current of one of the Nch-FETs as a voltage drop from the power supply voltage Vdd via this switch, and the source electrodes of both Nch-FETs are connected to the power supply 0V, The gate electrode can be connected to the negative feedback amplifier output, and the drain electrode of each Nch-FET can be connected to each electrode of the switch element.
[0017]
The first output limiting circuit includes a second Pch-FET having a gate electrode connected to the intermediate amplifier circuit output and a source electrode commonly connected to a source electrode of the first Pch-FET, and a drain electrode connected to the intermediate amplifier circuit. A third Pch-FET that is connected to the output and connects a gate potential determining resistor (R5) between the source electrode and the gate electrode, the current increasing in response to an increase in the current flowing through the second Pch-FET It can be configured to flow through a gate potential determining resistor.
A third Nch-FET and a fourth Nch-FET; and a gate electrode and a drain electrode of the third Nch-FET are connected to a drain electrode of the second Pch-FET, and a source electrode is connected to the regulator circuit output. The gate electrode, the source electrode, and the drain electrode of the fourth Nch-FET can be connected to the gate electrode of the third Nch-FET, the regulator circuit output, and the gate electrode of the third Pch-FET, respectively.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
1 is a block diagram of a regulator circuit according to an embodiment of the present invention, FIG. 2 is a rising characteristic diagram of a regulator circuit output with respect to an enable signal, and FIG. 3 is an explanatory diagram for explaining the operation of the regulator circuit. The same members corresponding to are denoted by the same reference numerals.
[0019]
In FIG. 1, a regulator circuit 1 according to the present invention includes a reference voltage generating circuit VR, an operational amplifier Q1 that receives the reference voltage Vref of the reference voltage generating circuit VR and amplifies the difference between the negative feedback signal Vf, and an output of the operational amplifier. An intermediate amplifier circuit Amp having output limiting means for amplifying V1 and switching the output range of the amplified output V2 to limit the overload current, and an output for amplifying the intermediate amplifier circuit output V2 and supplying power to the load L A circuit T3, a voltage dividing circuit R2 and R3 that divides the output V0 and supplies a negative feedback signal Vf to the operational amplifier Q1, and detects a decrease in the output voltage V0 of the output circuit T3 and detects the control signal to the output limiting means Overload detection circuit Q2 that outputs V4 and performs overload protection operation,
A delay circuit Q4 for delaying an enable signal V5 for starting the regulator circuit 1, an AND element Q3 for taking the logical product of the enable signal V6 delayed by the delay circuit Q4 and the control signal V4 from the overload detection circuit Q2; , And is configured.
[0020]
With this configuration, when the enable signal V5 is turned on (H level) and the regulator circuit 1 is started, the control to the output limiting means (SW) is performed until the enable signal V5 is delayed by the delay circuit Q4 and output. The signal V7 can be blocked to interrupt the overload protection circuit operation by the output limiting means.
[0021]
【Example】
In FIG. 1, the regulator circuit includes an operational amplifier Q1 constituting a negative feedback amplifier, a common source field effect transistor Nch-FET-T1, T2 for amplifying the output of the operational amplifier Q1, and any one of the field effect transistors. (T1, T2) load R1 and a switch SW that switches the load circuit from the first Nch-FET-T1 with large output current capacity to the second Nch-FET-T2 with small output current capacity The intermediate amplifier circuit Amp constituting the means, the intermediate amplifier circuit Amp, the output V2 is amplified to form an output circuit, and the source-grounded field effect transistor Pch-FET-T3, and the output voltage V0 is divided to be negative feedback. Output voltage detection circuit R2, R3 that forms voltage Vf, Pch-FET-T4, T7, Nch-FET-T5, T6, and resistors R4, R5, and changes in output V2 of intermediate amplifier Amp First output limiting circuit Clamp to suppress and clamp, the output voltage V0 and the reference voltage A comparator Q2 that configures an overload detection circuit and outputs a control signal V4, a delay circuit Q4 that delays an enable signal V5 that activates the regulator circuit according to the present invention, and a circuit described in the related art, An AND element Q3 that takes the logical product of the enable signal V6 and the control signal V4 delayed by the delay circuit Q4 is provided. A load circuit L and an output stabilizing capacitor C are externally connected to the output circuit.
[0022]
With this configuration, the control signal V6 generated by delaying the enable signal V5 for turning on the regulator circuit 1 is L for a sufficient time (several tens of microseconds) for the regulator output V0 to rise as shown in FIG. Therefore, as with the series regulator circuit without the short circuit protection circuit, the external capacitor C can be charged to the output voltage V0 level with a large current without limiting the current. As a result, it is possible to obtain a voltage waveform that rises in a short time similar to that shown in FIG.
[0023]
Even if the load current IL of the output circuit is large, the output voltage V0 drop is small if it is within the rated load current. Therefore, the output V4 of the comparator Q2 remains at L level, and there is no short circuit protection circuit. Similar to 2 and 3, it can operate to keep the output voltage V0 constant.
Next, in a state where the output terminal is short-circuited to the power supply 0V, the output voltage V0 becomes equal to or lower than the reference voltage Vref. Therefore, when the output V4 of the comparator Q2 becomes H level, the control signal V7 also becomes H level. The field effect transistor Nch-FET-T1 that constitutes the intermediate amplifier circuit Amp is switched to the Nch-FET-T2 with a small driving capability, and the Nch-FET-T2 is saturated where the drain current is small, so the electric field that forms the output circuit The gate potential of the effect transistor Pch-FET-T3 is raised to the power supply voltage Vdd side by the resistor R1 to operate so as to reduce the drain current of the field effect transistor Pch-FET-T3 in the output circuit.
[0024]
In the example shown in Fig. 1, when the output circuit is short-circuited to the power supply 0V due to the destruction of the load, etc., the output voltage range from the normal output voltage 3.0V to the reference voltage Vref (here, approximately 1, 2V) , The first output limiting circuit Clamp that suppresses and clamps the change in the output V2 of the intermediate amplifier Amp limits the short-circuit current to about 1x (A), and further the short-circuit state progresses to the potential level of the power supply 0V. In this case, the field effect transistor Nch-FET-T1 constituting the intermediate amplifier circuit Amp is switched to the Nch-FET-T2 having a small driving capability by the operation of the comparator Q2, and saturation occurs when the drain current of the Nch-FET-T2 is small. As a result, the gate potential of the field effect transistor Pch-FET-T3 forming the output circuit is increased to the power supply voltage Vdd side by the resistor R1.
[0025]
By this operation, when the potential at the time of short circuit becomes about the potential level of the power supply 0V, the field effect transistor Pch-FET-T3 of the output circuit is limited by the intermediate amplifier circuit Amp switched to Nch-FET-T2. Since only the drain current flows through the resistor R1, it can operate as a protection circuit when the load is short-circuited.
Further, even in a circuit configuration without the first output limiting circuit Clamp in FIG. 1, that is, in the prior art circuit configuration shown in FIG. 4, an intermediate amplifier circuit Amp according to the present invention and a comparator Q2 constituting an overload detection circuit are provided. By including the delay circuit Q4 and the AND element Q3, the effect of the first output limiting circuit shown in FIG. 3 is eliminated, but it is also possible to improve the startup characteristics at the start of the regulator circuit. it can.
[0026]
【The invention's effect】
According to the present invention, the capacitor connected to the output circuit can be charged with a large current by preventing the output short circuit protection circuit from operating when the output voltage rises. For example, as in a mobile phone, it is suitable for control in which power supply to unnecessary circuit blocks is stopped and fine power control is performed to reduce power consumption of the entire device.
[0027]
Further, once the output rises, the load short-circuit protection function as in the prior art can be held.
As a result, it is possible to provide a regulator circuit with good start-up characteristics of the power supply while ensuring the effect of reducing current consumption.
[Brief description of the drawings]
FIG. 1 is a block diagram of a regulator circuit according to an embodiment of the present invention. FIG. 2 is a rising characteristic diagram of a regulator circuit output with respect to an enable signal. FIG. 3 is an explanatory diagram for explaining the operation of the regulator circuit. Regulator circuit diagram [FIG. 5] Characteristic diagram of the regulator circuit in FIG. 4 [FIG. 6] Block diagram of a conventional regulator circuit having a load short-circuit protection function [FIG. 7] Load short-circuit protection characteristic diagram of the regulator circuit [FIG. 8] Start-up characteristics diagram of the regulator circuit [Explanation of symbols]
1 Regulator circuit
Q1 operational amplifier
Q2 Comparator
Q3 AND element
Q4 Delay circuit
T1, T2, T5, T6 Nch-FET
T3, T4, T7 Pch-FET
R1 ~ R5 resistance
SW Switch L Load C Capacity
Vref reference voltage
V1 to V7, Vf signal
Vdd supply voltage
Vss power supply 0V
A Constant voltage operation region B Operation region of the first output limiting circuit C Operation region of the second output limiting circuit

Claims (4)

A reference voltage generation circuit, an operational amplifier that receives the reference voltage of the reference voltage generation circuit and amplifies the difference between the negative feedback signal, amplifies the operational amplifier output, switches the output range of the amplified output, and reduces the overload current. An intermediate amplifier circuit having output limiting means for limiting; an output circuit for amplifying the output of the intermediate amplifier circuit and supplying power to the load; and a voltage dividing circuit for dividing the output and supplying a negative feedback signal to the operational amplifier; An overload detection circuit that detects a decrease in the output voltage of the output circuit and outputs a control signal to the output limiting means to perform an overload protection operation.
The output circuit has a source electrode of a first P-channel field effect transistor (hereinafter abbreviated as Pch-FET) connected to a power supply voltage Vdd, a gate electrode connected to the output of the intermediate amplifier circuit, and a drain electrode output to a regulator circuit. Connected to the load as
The regulator circuit further detects a output of the intermediate amplifier circuit, suppresses and clamps a change in the output of the intermediate amplifier circuit based on the output of the intermediate amplifier circuit, and an enable signal for starting the regulator circuit A delay circuit that delays the AND circuit, and an AND element that takes a logical product of the enable signal delayed by the delay circuit and the control signal from the overload detection circuit,
When starting the regulator circuit by turning on the enable signal, the control signal to the output limiting means is blocked until the enable signal is output after being delayed by the delay circuit, and the overload protection circuit operates by the output limiting means. Interrupt
A regulator circuit characterized by that. The regulator circuit according to claim 1,
The intermediate amplifier circuit having output limiting means includes a first N-channel field effect transistor (hereinafter abbreviated as Nch-FET) having a large output current capacity, a second Nch-FET having a small output current capacity, and both Nch-FETs. A switch element that switches the amplified output and a resistor that detects the amplified output current of one of the Nch-FETs as a voltage drop from the power supply voltage Vdd via this switch, and the source electrode of both Nch-FETs is powered A regulator circuit characterized in that it is connected to 0 V, the gate electrode is connected to the negative feedback amplifier output, and the drain electrode of each Nch-FET is connected to each electrode of the switch element. The regulator circuit according to claim 1 or 2,
  The first output limiting circuit includes a second Pch-FET having a gate electrode connected to the output of the intermediate amplifier circuit, a source electrode commonly connected to a source electrode of the first Pch-FET, and a drain electrode connected to the output of the intermediate amplifier circuit. And a third Pch-FET for connecting a gate potential determining resistor (R5) between the source electrode and the gate electrode,
  A regulator circuit, wherein a current that increases in accordance with an increase in a current flowing through the second Pch-FET is caused to flow through the gate potential determining resistor. The regulator circuit according to claim 3,
  Further comprising a third Nch-FET and a fourth Nch-FET,
  A gate electrode and a drain electrode of the third Nch-FET are connected to a drain electrode of the second Pch-FET, and a source electrode is connected to the regulator circuit output;
  A regulator circuit, wherein the gate electrode, the source electrode, and the drain electrode of the fourth Nch-FET are connected to the gate electrode of the third Nch-FET, the regulator circuit output, and the gate electrode of the third Pch-FET, respectively. .

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