JP4392201B2 - Electronic device and manufacturing method thereof - Google Patents

Electronic device and manufacturing method thereof Download PDF

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JP4392201B2
JP4392201B2 JP2003190259A JP2003190259A JP4392201B2 JP 4392201 B2 JP4392201 B2 JP 4392201B2 JP 2003190259 A JP2003190259 A JP 2003190259A JP 2003190259 A JP2003190259 A JP 2003190259A JP 4392201 B2 JP4392201 B2 JP 4392201B2
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base member
metal base
semiconductor chip
film
wiring
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JP2005026452A (en
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朝雄 飯島
義孝 福岡
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テセラ・インターコネクト・マテリアルズ,インコーポレイテッド
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Priority to JP2003190259A priority Critical patent/JP4392201B2/en
Priority to TW093118871A priority patent/TW200507131A/en
Priority to US10/880,588 priority patent/US7342802B2/en
Publication of JP2005026452A publication Critical patent/JP2005026452A/en
Priority to US11/657,286 priority patent/US7505281B2/en
Priority to US12/008,546 priority patent/US20080296254A1/en
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Priority to US13/896,911 priority patent/US20130247372A1/en
Priority to US14/271,959 priority patent/US9521755B2/en
Priority to US15/374,233 priority patent/US10104785B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

【0001】
【発明の属する技術分野】
本発明は、半導体集積回路、大規模集積回路等の半導体チップを内蔵した多層配線板構造の電子装置と、その製造方法に関するものである。
【0002】
【従来の技術】
従来の多層配線板として、表面に半導体チップを搭載し、該半導体チップの電極間を接続するために、更には、該半導体チップの電極などを外部に導出するために、層間絶縁膜を介して積層された複数の配線膜を形成し、バンプ等により各配線膜の間の電気的接続を行うように構成したもの(特開2002−043506号公報等参照)があった。
【0003】
そして、半導体チップは一般に例えば100μm以上の厚さを有し、従って、剛性を有していた。このように、半導体チップが剛性を有するので、半導体チップを搭載した多層配線板は当然のことながら、剛性を有していた。
【0004】
【発明が解決しようとする課題】
ところで、半導体チップを搭載した多層配線板からなる電子回路を備えた電子装置には、可撓性が要求されるものが増えている。特に、内視鏡、ペースメーカー、血圧計等、人体内部に挿入したり、埋め込んだり、人体に沿わせたりするものにその傾向が強い。
しかし、そのような要求には応えていないのが実情であった。
【0005】
そこで、本願発明者は、その要求に応えるべく、実験、研究を重ねた結果、半導体チップの厚みを50μm以下にすれば、可撓性が生じ、多層配線板にはそれ単独では可撓性のあるものが開発済みであるので、その可撓性のある多層配線板に可撓性のある半導体チップを搭載することにより半導体チップ搭載状態でも可撓性のある半導体チップ内蔵の多層配線板構造の電子装置を提供することができるという着想を得た。
本発明は、そのような着想に基づいて成されたものであり、半導体チップを内蔵した可撓性のある多層配線板構造の電子装置とその製造方法を提供することを目的とする。
【0007】
【課題を解決するための手段】
請求項の電子装置は、一方の表面に配線膜が形成され、少なくとも一部の配線膜の裏面に端子用バンプが形成された第1の金属ベース部材の上記一方の表面に、可撓性を持つ薄さに形成された半導体チップがその電極が上記配線膜に接続された状態でフリップチップボンディングされ、上記第1の金属ベース部材の上記一方の表面の配線膜に接続される層間接続用バンプと上記半導体チップが納まるチップ収納空間を同じ面に有し、反対側に配線膜が形成された第2の金属ベース部材が、該チップ収納空間内に上記半導体チップが納まり且つ上記各層間接続用バンプが対応する上記配線膜に接続されるように上記第1の金属ベース部材に重ねられ、上記各バンプ間に、各バンプ間及び上記第1と第2の金属ベース部材の配線膜間を絶縁する層間絶縁膜が形成され、多層配線板構造を有することを特徴とする。
【0008】
請求項の電子装置は、請求項記載の電子装置において、上記半導体チップの厚さが50μm以下であることを特徴とする。
請求項の電子装置は、請求項記載の電子装置において、上記半導体チップの上記電極と、上記配線膜とが、該配線膜の表面部に選択的に形成した導電性材料からなる電極接続用バンプを介して接続されたことを特徴とする。
【0009】
請求項の電子装置は、請求項1〜3記載の電子装置において、前記層間絶縁膜が、ポリイミド、液晶ポリマー、ガラスクロス含浸Bステージ樹脂、又はBCBフィルムからなる絶縁性フィルムで構成されてなることを特徴とする。
【0010】
請求項の電子装置の製造方法は、端子用バンプ形成用金属層の表面に配線膜が形成された第1の金属ベース部材と、可撓性を持つ薄さに形成された半導体チップと、配線膜形成用の金属層の一方の面に上記第1の金属ベース部材の上記配線膜に接続される層間接続用バンプ及び上記半導体チップが納まるチップ収納空間を同じ面に有し、更に該面に上記層間接続用バンプが貫通され且つ上記チップ収納空間内を占有しないように層間絶縁膜が積層された第2の金属ベース部材と、を用意し、上記第1の金属ベース部材の上記配線膜形成側の一方の表面に、上記半導体チップを、その電極が上記配線膜に接続されるようにフリップチップボンディングをし、上記第1の金属ベース部材の上記一方の表面に、上記第2の金属ベース部材を、その上記チップ収納空間内に上記半導体チップが収納され、上記層間接続用バンプの上記層間絶縁膜から露出した頂面を該第の金属ベース部材の配線膜に接続させることにより、該層間絶縁膜を介して積層し、上記第2の金属ベース部材の上記配線膜形成用の金属層を選択的にエッチングすることにより配線膜を形成すると共に、上記第1の金属ベース部材の上記端子用バンプ形成用金属層を選択的にエッチングすることにより端子用バンプを形成することを特徴とする。
【0011】
【発明の実施の形態】
以下、本発明を図示実施の形態例に従って詳細に説明する。図1(A)〜(C)は本発明電子装置の第1の実施の形態を示す断面図であり、(A)は通常の状態の電子装置を示し、(B)は撓んだ状態の電子装置をデフォルメして示し、(C)は内蔵した半導体チップの撓んだ状態をデフォルメして示す。
この電子装置は、内視鏡や心臓ペースメーカ等の柔軟性を必要とする医療機器として用いられるものである。
【0012】
11は例えばニッケル(厚さ例えば0.5〜2μm)及び銅(厚さ例えば3〜18μm)を選択的にめっきすることにより所定パターンに形成した配線膜であり、該配線膜11上には、半導体集積回路チップ或いは大規模集積回路チップ等の半導体チップ(20)の電極と接続されるところの例えば金めっきによる複数の電極接続用バンプ12が形成されている。20は半導体チップで、主表面が突起バンプ12形成面に対向する向きで、その各電極がそれと対応する電極接続用バンプ12と接続されてフリップチップ接続されている。
【0013】
30は半導体チップ20主表面を覆い、該半導体チップ20と配線膜11との間を絶縁する絶縁層で、ACF、ACP、NCF、またはNCP等のアンダフィル樹脂、或いはフィルムによる柔軟性のある絶縁材からなる。
半導体チップ20は、可撓性を持たせるために、集積回路が形成された主表面と反対側の面、即ち、半導体基板(半導体チップ化後又はウエハ状態の半導体基板)の裏面を研磨して厚さが10〜50μmとなるように調整し、更に1辺の寸法が例えば20mm程度のチップに切断したものである。このように、1辺が例えば20mm程度の矩形状を有し、厚さが50μm以下の半導体チップ20は図1(C)に示すように撓む。
【0014】
13は端子用バンプで、配線膜11の半導体チップ20側とは反対側に銅により形成され、半導体チップ20の各電極を外部に導出するためのものである。15は端子用バンプ13全体を覆うように形成された半田ボールで、その高さと径は、それぞれ50〜200μmと50〜250μmで、300〜800μmのピッチで配列されている。
【0015】
40は層間絶縁膜で、例えば、ポリイミド、液晶ポリマー、或いはガラスクロス含浸Bステージ樹脂等による絶縁フィルムからなり、上記配線膜11と後述する配線膜(51)との間を層間絶縁するもので、上記半導体チップ20を逃げるチップ収納空間42を有する。該層間絶縁膜40は後述する層間接続用バンプ(52)により貫通されている。
51は例えば銅からなる配線膜で、その裏面には直径が50〜100μm程度の複数の層間接続用バンプ52が形成されており、これらの層間接続用バンプ52を介して、配線膜11と配線膜51との間が所定の位置にて電気的に接続されている。また、配線膜51の表面には、絶縁性の保護膜60が設けられている。配線膜11〜保護膜60の全体の厚さは、50〜100μm程度となっている。
【0016】
このような電子装置は、半導体チップ40抜きの多層配線板構造を有するに過ぎない状態では可撓性を充分に有し、半導体チップ40もその厚さが50μm以下ならば、図1(C)に示すように可撓性を有するので、半導体チップ20を搭載した状態でも図1(B)に示すように可撓性を有する。
従って、内視鏡、ペースメーカー、血圧計等、人体内部に挿入したり、埋め込んだり、人体に沿わせたりするものに本電子装置を使用した場合において、その可撓性により人体にマッチすることが可能となり、電子装置が人体に及ぼす影響を小さくすることができる。
【0017】
図2(A)〜(F)は図1に示した電子装置の製造方法の一例(本発明電子装置の第1の実施の形態例)を工程順に示す断面図である。
(A)図2(A)に示すように、先ず、第1の金属ベース部材16と、予め厚さが10〜50μmとなり可撓性を有するように調整した半導体チップ20と、第2の金属ベース部材56を用意する。
用意する部材の一つである第1の金属ベース部材16は、銅からなる端子形成用バンプ13となる厚さ50μm程度の銅層10の一方の表面に例えばニッケル及び銅からなる厚さ例えば5〜12μm程度の配線膜11を例えば選択的メッキ法により形成し、更に、該配線膜11の表面部に選択的に、例えばニッケル膜及び金(或いは銅)、あるいはニッケル膜及び銅膜及び金膜からなる電極接続用バンプ12を例えば選択的メッキ法により形成してなるものである。選択的メッキ法は、例えば形成しようとするパターンに対してネガのパターンを有するレジスト膜を形成し、該レジスト膜をマスクとしてメッキすることにより形成することができる。
【0018】
用意する別の一つの部材、半導体チップ20は前述のように予め厚さが10〜50μmとなり可撓性を有するように調整しておく。
用意する残りの一つの部材、第2の金属ベース部材56は、配線膜51となる厚さが3〜18μm程度の配線膜形成用の銅層50と、厚さが30〜100μm程度の層間接続用バンプ52となるバンプ形成用銅層とを、厚さが0.5〜2μm程度のニッケル膜を介して積層した3層構造の金属部材を用意し、そのバンプ形成用銅層を、フォトエッチング加工して層間接続用バンプ52を形成し、ニッケル膜の表面を露出させ、更に、残された層間接続用バンプ52をエッチングマスクとしてニッケル膜をエッチングしたものを母体としている。
【0019】
その金属ベース部材56は、半導体チップ20がフリップチップ接続された第1の金属ベース部材16に積層するときにその半導体チップ20を逃げる部分には層間接続用バンプ52が形成されておらず、半導体チップを逃げるチップ収納空間42を有している。
該第2の金属ベース部材56には、層間接続用バンプ52が貫通され、且つ上記チップ収納空間42を占有しないパターン(デバイスホールを有するパターン)を有する層間絶縁膜40が積層されている。
【0020】
該層間絶縁膜40はポリイミド、液晶ポリマー、ガラスクロス含浸Bステージ樹脂、またはBCBフィルムによる絶縁フィルムからなり、半導体チップ20を配置するための、例えば縦横20mm程度のデバイスホールとも言えるチップ収納空間42を開けてる。尚、絶縁フィルム40の厚さは、半導体チップ20の厚さとほぼ同一、又はこの半導体チップ20よりも1〜5μm程度厚く設定されている。
更に、上記チップ収納空間42上には、換言すれば、半導体チップ20を搭載する箇所に、空隙充填樹脂58を塗布しておく。チップ20と第2の金属ベース部材56との間に空隙が生じないようにするためである。
【0021】
(B)次に、第1の金属ベース部材16の半導体チップ20を搭載する箇所に、ACF、ACP、NCF、またはNCP等のアンダフィル樹脂、或いはフィルムからなる絶縁材を絶縁層30として塗布しておき、その第1の金属ベース部材16上に、上記半導体チップ20を、その各電極がそれと対応する配線膜11上の電極接続用バンプ12と接続されるようにフリップチップ接続する。その場合、半導体チップ20と第1の金属ベース部材16との間に上記絶縁層30が介在している。図2(B)はそのフリップチップ接続後の状態を示している。
【0022】
(C)次に、図2(C)に示すように、半導体チップ20が搭載された第1の金属ベース部材16上に、第2の金属ベース部材56を積層する。具体的には、チップ収納空間42内に上記半導体チップ20が納まり、層間絶縁膜40を貫通した層間接続用バンプ52の頂面が配線膜11と接続されるようにして積層を行う。
(D)次に、図2(D)に示すように、上記第2の金属ベース部材56の配線膜形成用銅層50を選択的にエッチングすることにより配線膜51を形成し、その後、カバーレイ60を形成する。
【0023】
(E)次に、図2(E)に示すように、第1の金属ベース部材16の端子用バンプ形成用銅層10を選択的にエッチングすることにより端子用バンプを形成すべく該銅層10上にエッチングマスクとなるレジスト膜64を選択的に形成する。
(F)次に、図2(F)に示すように、上記レジスト膜64をマスクとして上記銅層10をエッチングすることにより、端子用バンプ13を形成する。
その後、図2では図示しないが、端子用バンプ13をマスクとしてニッケル膜をエッチングにより除去し、更に端子用バンプ13の周りに半田15を形成する。
【0024】
以上のように、この実施形態の電子装置は、2つの配線膜11,51の間に、半導体チップ20を埋め込んで、その周囲を絶縁層30や絶縁フィルム40等で保護するようにしているので、この半導体チップ20が柔軟性を示すような50μm以下の厚さにすることが可能になり、全体として柔軟性のある多層配線板構造の電子装置を構成することができる。
【0025】
なお、本発明は、上記実施形態に限定されず、種々の変形が可能である。この変形例としては、例えば、次のようなものがある。
(1)2層構造のものを説明したが、層の数は任意である。
(2)各層に設ける半導体チップ20の数は任意である。また、半導体チップ20に加えて、レジスタやキャパシタ等の受動機能素子を内蔵させることができる。
【0026】
(3)配線膜11,51を構成する銅箔等の厚さ、及び絶縁層30や絶縁フィルム40の厚さや材料は、例示したものに限定されない。
(4)配線膜51は、ニッケル膜によるエッチングストッパを有する3層の金属部材を用いて形成しているが、この形成方法や材料は、例示したものに限定されない。
【0027】
(5)図1、図2に示す上記実施の形態例では、銅ベース部材10の表面に、ニッケル及び銅を選択めっきして配線膜11を形成し、更にこの配線膜11の所定の箇所に、半導体チップ搭載用の複数の突起バンプ12を形成しているが、配線膜11の形成はこの方法に限定されない。例えば、配線膜11となる銅箔を用い、この銅箔上の所定の箇所に半導体チップ搭載用の複数の突起バンプ12を形成し、更にこの銅箔をエッチングして配線膜11を形成しても良い。
【0028】
(6)上記実施の形態例では、配線膜11の所定の箇所に半導体チップ20を搭載するための複数の突起バンプ12を形成しているが、半導体チップ20側に接続用のバンプが形成されている場合には、この突起バンプ12は不要である。
(7)上記実施の形態例では、絶縁フィルム40の厚さを、半導体チップ20の厚さとほぼ同一、またはこの半導体チップ20よりも1〜5μm程度厚く設定しているが、層間接続用バンプ52となる金属部材56における第2の銅箔の1/3〜2/3の厚さに設定しても良い。
なお、参考例として、電子装置は、複数層の層間絶縁層により層間絶縁された複数層の配線膜の層間接続を、上記層間絶縁層を貫通する層間接続導電層により為すようにした多層配線板の上記層間絶縁層のうちのいずれかの層の内部に、電極を上記配線膜に接続されるように形成され、可撓性を持つ薄さに形成された半導体チップを有することを特徴とする。
【0030】
【発明の効果】
請求項の電子装置によれば、第1の金属ベース部材の配線膜が形成された側の表面に、可撓性を持つ薄さに形成された半導体チップを、その電極が上記配線膜に接続された状態でフリップチップボンディングし、第2の金属ベース部材を、それのチップ収納空間内に上記半導体チップが納まり且つ第2の層間接続用バンプが対応する第1の金属ベース部材の配線膜に接続されるように第1の金属ベース部材に重ね、上記各バンプ間に、各バンプ間及び上記第1と第2の金属ベース部材の配線膜間を絶縁する層間絶縁膜が形成されているので、多層配線板構造の電子装置全体として可撓性を持つようにすることができる。
【0031】
請求項の電子装置によれば、請求項記載の電子装置において、上記半導体チップの厚さが50μm以下であるので、半導体チップが可撓性を持ち、それを内蔵した多層配線板構造の電子装置も全体としても可撓性を有するようにできる。
請求項の電子装置によれば、請求項記載の電子装置において、上記半導体チップの上記電極と、上記配線膜とを、該配線膜の表面部に選択的に形成した導電性材料からなる電極接続用バンプを介して接続するので、より信頼度良く半導体チップのフリップチップ接続ができる。
【0032】
請求項の電子装置によれば、請求項1〜3記載の電子装置において、層間絶縁膜が、ポリイミド、液晶ポリマー、ガラスクロス含浸Bステージ樹脂、またはBCBフィルムであるので、層間絶縁膜形成作業が容易で、より確実な層間絶縁ができる。
請求項の電子装置の製造方法によれば、請求項記載の多層配線板構造の電子装置を得ることができる。
【図面の簡単な説明】
【図1】(A)〜(C)は本発明電子装置の第1の実施の形態を示す断面図であり、(A)は通常の状態の電子装置を示し、(B)は撓んだ状態の電子装置をデフォルメして示し、(C)は内蔵した半導体チップの撓んだ状態をデフォルメして示す。
【図2】(A)〜(F)は図1に示した電子装置の製造方法の一例(本発明電子装置の第1の実施の形態例)を工程順に示す断面図である。
【符号の説明】
10・・・端子用バンプ形成用金属層、11、51・・・配線膜、
12・・・電極接続用バンプ、13・・・端子用バンプ、
15・・・半田ボール、16・・・第1の金属ベース部材
20・・・半導体チップ、30・・・絶縁層、
40・・・層間絶縁膜、
42・・・チップ収納空間(デバイスホール)、
50・・・金属層、52・・・層間接続用バンプ、
56・・・第2の金属ベース部材
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic device having a multilayer wiring board structure incorporating a semiconductor chip such as a semiconductor integrated circuit or a large-scale integrated circuit, and a manufacturing method thereof.
[0002]
[Prior art]
As a conventional multilayer wiring board, a semiconductor chip is mounted on the surface, and in order to connect the electrodes of the semiconductor chip, and further to lead out the electrodes of the semiconductor chip to the outside, an interlayer insulating film is interposed. There has been a configuration in which a plurality of laminated wiring films are formed and electrical connection is made between the respective wiring films by bumps or the like (see Japanese Patent Application Laid-Open No. 2002-043506).
[0003]
The semiconductor chip generally has a thickness of, for example, 100 μm or more, and therefore has rigidity. Thus, since the semiconductor chip has rigidity, the multilayer wiring board on which the semiconductor chip is mounted has rigidity as a matter of course.
[0004]
[Problems to be solved by the invention]
By the way, an electronic device including an electronic circuit made of a multilayer wiring board on which a semiconductor chip is mounted is increasingly required to have flexibility. In particular, this tendency is strong for an endoscope, a pacemaker, a sphygmomanometer, or the like that is inserted into, embedded in, or along the human body.
However, the fact was that it did not meet such demands.
[0005]
Therefore, as a result of repeated experiments and researches, the inventor of the present application has obtained flexibility if the thickness of the semiconductor chip is reduced to 50 μm or less, and the multilayer wiring board alone is flexible. Since some have been developed, by mounting a flexible semiconductor chip on the flexible multilayer wiring board, even when the semiconductor chip is mounted, the multilayer wiring board structure with the built-in flexible semiconductor chip is provided. The idea was that an electronic device could be provided.
The present invention has been made based on such an idea, and an object thereof is to provide an electronic device having a flexible multilayer wiring board structure incorporating a semiconductor chip and a method for manufacturing the same.
[0007]
[Means for Solving the Problems]
The electronic device according to claim 1 is flexible on the one surface of the first metal base member in which the wiring film is formed on one surface and the terminal bump is formed on the back surface of at least a part of the wiring film. A semiconductor chip formed in a thin film having a thickness is flip-chip bonded with its electrodes connected to the wiring film, and connected to the wiring film on the one surface of the first metal base member . A second metal base member having a chip housing space for accommodating the bump and the semiconductor chip on the same surface, and having a wiring film formed on the opposite side, accommodates the semiconductor chip in the chip housing space and the interlayer connection. The bumps are overlaid on the first metal base member so that the bumps are connected to the corresponding wiring films, and between the bumps and between the wiring films of the first and second metal base members. Insulate During insulating film is formed, characterized by having a multi-layer wiring board structure.
[0008]
According to a second aspect of the present invention, in the electronic device according to the first aspect , the thickness of the semiconductor chip is 50 μm or less.
The electronic device according to claim 3 is the electronic device according to claim 1 , wherein the electrode of the semiconductor chip and the wiring film are made of a conductive material selectively formed on a surface portion of the wiring film. It is characterized by being connected through a bump for use.
[0009]
The electronic device according to claim 4 is the electronic device according to claims 1 to 3 , wherein the interlayer insulating film is made of an insulating film made of polyimide, liquid crystal polymer, glass cloth-impregnated B-stage resin, or BCB film. It is characterized by that.
[0010]
According to a fifth aspect of the present invention, there is provided an electronic device manufacturing method comprising: a first metal base member having a wiring film formed on a surface of a terminal bump-forming metal layer; and a semiconductor chip formed in a thin thickness with flexibility; One surface of the metal layer for forming the wiring film has an interlayer connection bump connected to the wiring film of the first metal base member and a chip storage space for housing the semiconductor chip on the same surface, And a second metal base member laminated with an interlayer insulating film so that the interlayer connection bumps are penetrated and do not occupy the chip housing space, and the wiring film of the first metal base member The semiconductor chip is flip-chip bonded to one surface on the formation side so that the electrode is connected to the wiring film, and the second metal is applied to the one surface of the first metal base member. the base member, the It said semiconductor chip is accommodated in the serial chip accommodation space, by connecting the top surface exposed from the interlayer insulating film of the interlayer connection bumps to the wiring layer of the first metal base member, an interlayer insulating film And forming a wiring film by selectively etching the metal layer for forming the wiring film of the second metal base member , and for forming the terminal bumps of the first metal base member Terminal bumps are formed by selectively etching the metal layer.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail according to embodiments shown in the drawings. 1A to 1C are cross-sectional views showing a first embodiment of the electronic device of the present invention. FIG. 1A shows an electronic device in a normal state, and FIG. 1B shows a bent state. The electronic device is shown deformed, and (C) shows the deformed state of the built-in semiconductor chip.
This electronic device is used as a medical device that requires flexibility, such as an endoscope or a cardiac pacemaker.
[0012]
11 is a wiring film formed in a predetermined pattern by selectively plating, for example, nickel (thickness, for example, 0.5 to 2 μm) and copper (thickness, for example, 3 to 18 μm), and on the wiring film 11, A plurality of bumps 12 for electrode connection are formed by gold plating, for example, which are connected to the electrodes of a semiconductor chip (20) such as a semiconductor integrated circuit chip or a large scale integrated circuit chip. A semiconductor chip 20 has a main surface facing the surface on which the bump 12 is formed, and each electrode thereof is connected to the corresponding electrode connection bump 12 to be flip-chip connected.
[0013]
Reference numeral 30 denotes an insulating layer that covers the main surface of the semiconductor chip 20 and insulates between the semiconductor chip 20 and the wiring film 11, and is a flexible insulating material such as an underfill resin such as ACF, ACP, NCF, or NCP, or a film. Made of material.
In order to provide flexibility, the semiconductor chip 20 is polished on the surface opposite to the main surface on which the integrated circuit is formed, that is, the back surface of the semiconductor substrate (after being formed into a semiconductor chip or in a wafer state). The thickness is adjusted so as to be 10 to 50 μm, and one side is cut into chips of about 20 mm, for example. As described above, the semiconductor chip 20 having one side having a rectangular shape of about 20 mm and a thickness of 50 μm or less bends as shown in FIG.
[0014]
Reference numeral 13 denotes a terminal bump, which is formed of copper on the side opposite to the semiconductor chip 20 side of the wiring film 11 and leads out the electrodes of the semiconductor chip 20 to the outside. Reference numeral 15 denotes solder balls formed so as to cover the entire terminal bumps 13 and have heights and diameters of 50 to 200 μm and 50 to 250 μm, respectively, and are arranged at a pitch of 300 to 800 μm.
[0015]
40 is an interlayer insulating film, for example, made of an insulating film made of polyimide, liquid crystal polymer, glass cloth impregnated B-stage resin or the like, and performs interlayer insulation between the wiring film 11 and a wiring film (51) described later. A chip storage space 42 for escaping the semiconductor chip 20 is provided. The interlayer insulating film 40 is penetrated by interlayer connection bumps (52) described later.
Reference numeral 51 denotes a wiring film made of, for example, copper, and a plurality of interlayer connection bumps 52 having a diameter of about 50 to 100 μm are formed on the back surface thereof, and the wiring film 11 and the wiring are connected via the interlayer connection bumps 52. The film 51 is electrically connected at a predetermined position. An insulating protective film 60 is provided on the surface of the wiring film 51. The total thickness of the wiring film 11 to the protective film 60 is about 50 to 100 μm.
[0016]
Such an electronic device has sufficient flexibility in a state where it only has a multilayer wiring board structure without the semiconductor chip 40. If the thickness of the semiconductor chip 40 is 50 μm or less, FIG. Therefore, even when the semiconductor chip 20 is mounted, it has flexibility as shown in FIG.
Therefore, when this electronic device is used for an endoscope, pacemaker, sphygmomanometer, etc. that is inserted into, embedded in, or along the human body, it can match the human body due to its flexibility. Thus, the influence of the electronic device on the human body can be reduced.
[0017]
2A to 2F are cross-sectional views showing an example of the method for manufacturing the electronic device shown in FIG. 1 (first embodiment of the electronic device of the present invention) in the order of steps.
(A) As shown in FIG. 2A, first, a first metal base member 16, a semiconductor chip 20 that has been adjusted to have a thickness of 10 to 50 μm in advance and have flexibility, and a second metal A base member 56 is prepared.
The first metal base member 16, which is one of the members to be prepared, has a thickness made of, for example, nickel and copper on one surface of the copper layer 10 having a thickness of about 50 μm to be the terminal forming bumps 13 made of copper. A wiring film 11 having a thickness of about 12 μm is formed by, for example, a selective plating method. Further, for example, a nickel film and gold (or copper), or a nickel film and a copper film and a gold film are selectively formed on the surface portion of the wiring film 11. The electrode connection bumps 12 are formed by, for example, a selective plating method. The selective plating method can be formed, for example, by forming a resist film having a negative pattern with respect to a pattern to be formed and plating using the resist film as a mask.
[0018]
Another member to be prepared, the semiconductor chip 20, is adjusted in advance to have a thickness of 10 to 50 μm and have flexibility as described above.
The remaining one member to be prepared, the second metal base member 56, is a wiring film forming copper layer 50 having a thickness of about 3 to 18 μm and an interlayer connection having a thickness of about 30 to 100 μm. A metal member having a three-layer structure in which a bump forming copper layer to be used as a bump 52 is laminated with a nickel film having a thickness of about 0.5 to 2 μm is prepared, and the bump forming copper layer is photoetched An interlayer connection bump 52 is formed by processing to expose the surface of the nickel film, and a base material obtained by etching the nickel film using the remaining interlayer connection bump 52 as an etching mask is used.
[0019]
The metal base member 56 is not formed with the interlayer connection bumps 52 in the portion where the semiconductor chip 20 escapes when the semiconductor chip 20 is laminated on the first metal base member 16 which is flip-chip connected. A chip storage space 42 for escaping the chips is provided.
The second metal base member 56 is laminated with an interlayer insulating film 40 having a pattern (pattern having a device hole) through which the interlayer connection bumps 52 penetrate and the chip housing space 42 is not occupied.
[0020]
The interlayer insulating film 40 is made of an insulating film made of polyimide, liquid crystal polymer, glass cloth-impregnated B-stage resin, or BCB film, and has a chip storage space 42 that can be said to be a device hole of about 20 mm in length and width for placing the semiconductor chip 20. It ’s open. The thickness of the insulating film 40 is set to be substantially the same as the thickness of the semiconductor chip 20 or about 1 to 5 μm thicker than the semiconductor chip 20.
Furthermore, in other words, the space filling resin 58 is applied on the chip storage space 42 at the place where the semiconductor chip 20 is mounted. This is to prevent a gap from being generated between the chip 20 and the second metal base member 56.
[0021]
(B) Next, an insulating material made of an underfill resin such as ACF, ACP, NCF, or NCP, or a film is applied as an insulating layer 30 to the place where the semiconductor chip 20 of the first metal base member 16 is mounted. The semiconductor chip 20 is flip-chip connected to the first metal base member 16 so that each electrode thereof is connected to the corresponding electrode connection bump 12 on the wiring film 11. In that case, the insulating layer 30 is interposed between the semiconductor chip 20 and the first metal base member 16. FIG. 2B shows a state after the flip chip connection.
[0022]
(C) Next, as shown in FIG. 2C, a second metal base member 56 is laminated on the first metal base member 16 on which the semiconductor chip 20 is mounted. More specifically, the semiconductor chip 20 is housed in the chip storage space 42, and stacking is performed so that the top surfaces of the interlayer connection bumps 52 penetrating the interlayer insulating film 40 are connected to the wiring film 11.
(D) Next, as shown in FIG. 2D, a wiring film 51 is formed by selectively etching the wiring film forming copper layer 50 of the second metal base member 56, and then a cover is formed. A ray 60 is formed.
[0023]
(E) Next, as shown in FIG. 2 (E), the copper layer for forming terminal bumps is formed by selectively etching the terminal bump forming copper layer 10 of the first metal base member 16. A resist film 64 serving as an etching mask is selectively formed on 10.
(F) Next, as shown in FIG. 2F, the copper bumps 10 are etched by using the resist film 64 as a mask, thereby forming terminal bumps 13.
Thereafter, although not shown in FIG. 2, the nickel film is removed by etching using the terminal bumps 13 as a mask, and solder 15 is formed around the terminal bumps 13.
[0024]
As described above, in the electronic device of this embodiment, the semiconductor chip 20 is embedded between the two wiring films 11 and 51, and the periphery thereof is protected by the insulating layer 30, the insulating film 40, or the like. The semiconductor chip 20 can have a thickness of 50 μm or less such that the semiconductor chip 20 exhibits flexibility, and an electronic device having a flexible multilayer wiring board structure as a whole can be configured.
[0025]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. Examples of this modification include the following.
(1) Although the two-layer structure has been described, the number of layers is arbitrary.
(2) The number of semiconductor chips 20 provided in each layer is arbitrary. In addition to the semiconductor chip 20, passive functional elements such as resistors and capacitors can be incorporated.
[0026]
(3) The thickness of the copper foil etc. which comprises the wiring films 11 and 51, and the thickness and material of the insulating layer 30 and the insulating film 40 are not limited to what was illustrated.
(4) The wiring film 51 is formed using a three-layer metal member having an etching stopper made of a nickel film. However, the formation method and material are not limited to those exemplified.
[0027]
(5) In the above-described embodiment shown in FIGS. 1 and 2, the wiring film 11 is formed by selectively plating nickel and copper on the surface of the copper base member 10, and further, at a predetermined portion of the wiring film 11. Although the plurality of bumps 12 for mounting the semiconductor chip are formed, the formation of the wiring film 11 is not limited to this method. For example, a copper foil used as the wiring film 11 is used, a plurality of bumps 12 for mounting a semiconductor chip are formed at predetermined locations on the copper foil, and the wiring film 11 is formed by etching the copper foil. Also good.
[0028]
(6) In the above embodiment, the plurality of bumps 12 for mounting the semiconductor chip 20 are formed at predetermined locations on the wiring film 11, but connection bumps are formed on the semiconductor chip 20 side. If it is, this bump 12 is not necessary.
(7) In the above embodiment, the thickness of the insulating film 40 is set to be substantially the same as the thickness of the semiconductor chip 20 or about 1 to 5 μm thicker than the semiconductor chip 20. You may set to the thickness of 1/3-2/3 of the 2nd copper foil in the metal member 56 used.
As a reference example, an electronic device includes a multilayer wiring board in which interlayer connection of a plurality of wiring films interlayer-insulated by a plurality of interlayer insulating layers is made by an interlayer connection conductive layer penetrating the interlayer insulating layer. In any one of the interlayer insulating layers, an electrode is formed so as to be connected to the wiring film, and the semiconductor chip is formed in a thin thickness having flexibility. .
[0030]
【The invention's effect】
According to the electronic device of claim 1 , a semiconductor chip formed on a thin surface having flexibility on the surface of the first metal base member on which the wiring film is formed, and an electrode thereof on the wiring film and flip-chip bonding the connected state, the second metal base member, wiring layer of the first metal base member in which the semiconductor chip is fit and a second interlayer connection bumps correspond to those of the chip accommodation space An interlayer insulating film that insulates between the bumps and between the bump films and between the wiring films of the first and second metal base members is formed so as to be connected to the first metal base member . Therefore, the entire electronic device having the multilayer wiring board structure can be made flexible.
[0031]
According to a second aspect of the present invention, in the electronic device according to the first aspect , since the thickness of the semiconductor chip is 50 μm or less, the semiconductor chip is flexible and has a multilayer wiring board structure incorporating the semiconductor chip. The electronic device as a whole can be flexible.
According to an electronic device of a third aspect, in the electronic device according to the first aspect , the electrode of the semiconductor chip and the wiring film are made of a conductive material selectively formed on a surface portion of the wiring film. Since the connection is made via the electrode connection bump, the semiconductor chip can be flip-chip connected with higher reliability.
[0032]
According to the electronic device of claim 4, in the electronic device of claims 1 to 3 , since the interlayer insulating film is polyimide, liquid crystal polymer, glass cloth impregnated B stage resin, or BCB film, the interlayer insulating film forming operation Is easy and more reliable interlayer insulation is possible.
According to the electronic device manufacturing method of the fifth aspect, the electronic device having the multilayer wiring board structure according to the first aspect can be obtained.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views showing a first embodiment of an electronic device of the present invention, FIG. 1A shows an electronic device in a normal state, and FIG. The state electronic device is shown deformed, and (C) shows the state where the built-in semiconductor chip is bent.
2A to 2F are cross-sectional views showing an example of a method for manufacturing the electronic device shown in FIG. 1 (first embodiment of the electronic device of the present invention) in the order of steps.
[Explanation of symbols]
10 ... Metal layer for forming bumps for terminals, 11, 51 ... Wiring film,
12 ... Electrode connection bumps, 13 ... Terminal bumps,
15 ... solder balls, 16 ... first metal base member ,
20 ... Semiconductor chip, 30 ... Insulating layer,
40 ... interlayer insulating film,
42 ... Chip storage space (device hole),
50 ... metal layer, 52 ... bump for interlayer connection,
56: Second metal base member .

Claims (5)

一方の表面に配線膜が形成され、少なくとも一部の配線膜の裏面に端子用バンプが形成された第1の金属ベース部材の上記一方の表面に、可撓性を持つ薄さに形成された半導体チップがその電極が上記配線膜に接続された状態でフリップチップボンディングされ、
上記第1の金属ベース部材の上記一方の表面の配線膜に接続される層間接続用バンプと上記半導体チップが納まるチップ収納空間を同じ面に有し、反対側に配線膜が形成された第2の金属ベース部材が、該チップ収納空間内に上記半導体チップが納まり且つ上記各層間接続用バンプが対応する上記配線膜に接続されるように上記第1の金属ベース部材に重ねられ、上記各バンプ間に、各バンプ間及び上記第1と第2の金属ベース部材の配線膜間を絶縁する層間絶縁膜が形成された、
多層配線板構造を有する、
ことを特徴とする電子装置。
Is wired film formed on one surface, on the one surface of the first metal base member terminal bumps are formed on the rear surface of at least a part of the wiring layer, formed on the thin with flexible The semiconductor chip is flip-chip bonded with the electrodes connected to the wiring film,
The second metal base member has an interlayer connection bump connected to the wiring film on the one surface of the first metal base member and a chip housing space for storing the semiconductor chip on the same surface, and a second wiring film formed on the opposite side. The metal base member is overlaid on the first metal base member so that the semiconductor chip is accommodated in the chip storage space and the interlayer connection bumps are connected to the corresponding wiring films. An interlayer insulating film is formed between the bumps and between the wiring films of the first and second metal base members .
Having a multilayer wiring board structure,
An electronic device characterized by that.
上記半導体チップの厚さが50μm以下であることを特徴とする請求項1記載の電子装置。The electronic device according to claim 1, wherein the semiconductor chip has a thickness of 50 μm or less. 上記半導体チップの上記電極と、上記配線膜とが、該配線膜の表面部に選択的に形成した導電性材料からなる電極接続用バンプを介して接続されたことを特徴とする請求項1記載の電子装置。And the electrode of said semiconductor chip, and the wiring film, according to claim 1, characterized in that it is connected via the electrode contact bumps made of selectively forming conductive material in the surface portion of the wiring film Electronic devices. 前記層間絶縁膜が、ポリイミド、液晶ポリマー、ガラスクロス含浸Bステージ樹脂、またはBCBフィルムである絶縁性フィルムからなる、ことを特徴とする請求項1〜3記載の電子装置。The electronic device according to claim 1 , wherein the interlayer insulating film is made of an insulating film that is polyimide, liquid crystal polymer, glass cloth-impregnated B-stage resin, or BCB film. 端子用バンプ形成用金属層の表面に配線膜が形成された第1の金属ベース部材と、可撓性を持つ薄さに形成された半導体チップと、配線膜形成用の金属層の一方の面に上記第1の金属ベース部材の上記配線膜に接続される層間接続用バンプ及び上記半導体チップが納まるチップ収納空間を同じ面に有し、更に該面に上記層間接続用バンプが貫通され且つ上記チップ収納空間内を占有しないように層間絶縁膜が積層された第2の金属ベース部材と、を用意し、
上記第1の金属ベース部材の上記配線膜形成側の一方の表面に、上記半導体チップを、その電極が上記配線膜に接続されるようにフリップチップボンディングをし、
上記第1の金属ベース部材の上記一方の表面に、上記第2の金属ベース部材を、その上記チップ収納空間内に上記半導体チップが収納され、上記層間接続用バンプの上記層間絶縁膜から露出した頂面を該第の金属ベース部材の配線膜に接続させることにより、該層間絶縁膜を介して積層し、
上記第2の金属ベース部材の上記配線膜形成用の金属層を選択的にエッチングすることにより配線膜を形成すると共に、上記第1の金属ベース部材の上記端子用バンプ形成用金属層を選択的にエッチングすることにより端子用バンプを形成する
ことを特徴とする電子装置の製造方法。
A first metal base member having a wiring film formed on the surface of a metal layer for forming a bump for terminals, a semiconductor chip formed in a flexible thin film, and one surface of the metal layer for forming a wiring film Having a chip housing space for accommodating the semiconductor chip and an interlayer connection bump connected to the wiring film of the first metal base member on the same surface, and further, the interlayer connection bump is penetrated through the surface. Preparing a second metal base member on which an interlayer insulating film is laminated so as not to occupy the chip storage space;
The semiconductor chip is flip-chip bonded to one surface of the first metal base member on the wiring film formation side so that the electrode is connected to the wiring film,
To said one surface of the first metal base member, the second metal base member, said semiconductor chip is accommodated in the said chip receiving space, and exposed from the interlayer insulating film of the interlayer connection bumps By connecting the top surface to the wiring film of the first metal base member , it is laminated via the interlayer insulating film,
To form a wiring layer by selectively etching the metal layer for the wiring film formation of the second metal base member, selectively above the terminal bump forming metal layer of the first metal base member A method for manufacturing an electronic device, comprising: forming a bump for a terminal by etching the substrate.
JP2003190259A 2003-07-02 2003-07-02 Electronic device and manufacturing method thereof Expired - Fee Related JP4392201B2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2003190259A JP4392201B2 (en) 2003-07-02 2003-07-02 Electronic device and manufacturing method thereof
TW093118871A TW200507131A (en) 2003-07-02 2004-06-28 Multi-layer circuit board for electronic device
US10/880,588 US7342802B2 (en) 2003-07-02 2004-07-01 Multilayer wiring board for an electronic device
US11/657,286 US7505281B2 (en) 2003-07-02 2007-01-24 Multilayer wiring board for an electronic device
US12/008,546 US20080296254A1 (en) 2003-07-02 2008-01-11 Multilayer wiring board for an electronic device
US13/896,911 US20130247372A1 (en) 2003-07-02 2013-05-17 Multilayer wiring board for an electronic device
US14/271,959 US9521755B2 (en) 2003-07-02 2014-05-07 Multilayer wiring board for an electronic device
US15/374,233 US10104785B2 (en) 2003-07-02 2016-12-09 Multilayer wiring board for an electronic device

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CN107112289B (en) * 2014-12-25 2020-01-07 大口电材株式会社 Substrate for semiconductor device, wiring member for semiconductor device, method for manufacturing the same, and method for manufacturing semiconductor device using substrate for semiconductor device

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