JP4389858B2 - Power circuit - Google Patents

Description

  The present invention relates to a power supply circuit that supplies power for operating a load circuit such as various sensor devices from minute electric power obtained by a power generation element.

  Various sensor devices have power supply wired or output sensor signals wired, but the wiring from the sensor device to the power supply and the wiring from the sensor device to the receiving device that receives signals I need.

  In the sensor device having such a configuration, there is a problem that it takes much time and cost because it is necessary to perform wiring construction or removal of wiring when attaching the sensor device or performing maintenance.

  Therefore, a sensor device that uses a primary battery as a power source and wirelessly transmits a sensor signal to the outside has been provided. In view of the necessity of extending the battery driving time, the power consumption of the sensor device is reduced. On the other hand, considering the effort of replacing the primary battery, etc., the adoption of a power supply unit using a power generation element has led to the reduction of the battery of the entire system.

  By the way, in the power supply circuit using a power generation element, since the minute electric power obtained from the power generation element is unstable, the power generation efficiency of how to effectively use the minute electric power is a big problem.

  For example, when considering a thick battery that uses the photoelectric effect as a power generation element, an electronic device that boosts power from a solar battery to charge a secondary battery has already been provided (for example, Patent Document 1).

  The configuration disclosed in Patent Document 1 uses power generation means for obtaining a large power generation such as a solar panel, and is not suitable for the sensor device as described above.

  Further, as a power supply circuit corresponding to a solar cell such as a single cell, as shown in FIG. 10, a minute power (voltage VIN) from the solar cell 1 is boosted (VA) by the booster circuit unit 2 and is composed of a regulator circuit. A power supply circuit that outputs a constant voltage (VOUT) in the supply circuit unit 5 and supplies power (power supply voltage) to the load circuit 4 can be considered.

Although the circuit configuration as shown in FIG. 10 can be realized under a situation where light irradiation on the solar cell 1 is always obtained, there are many cases where light irradiation cannot actually be obtained in practice. Therefore, it is conceivable to provide a secondary battery 3 at the regulator output in the same manner as in the configuration of Patent Document 1 to cope with the situation where light is not obtained. That is, when light is obtained, the secondary battery 3 is charged at the same time as the power is supplied to the load circuit 4 based on the power from the solar battery 1. When light cannot be obtained, power is supplied from the secondary battery 3 to the load circuit 4. Such a circuit configuration makes it possible to extend the life of the entire device including the load circuit 4.
JP-A-11-96450 (FIG. 1, paragraph number 0052)

  By the way, in the ubiquitous society expected in the future, a battery-less / wireless sensor device having a smaller size and a longer life is required by the above-described sensor device. However, when considering the downsizing of the entire device, In the example using the battery 1, the light receiving area and the current capability of the solar battery 1 are problems, and the problem is that stable power cannot be given to the load circuit 4 or the secondary battery 3 under a low illuminance with a small amount of light. was there.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to supply a stable power to a load circuit by efficiently using a minute power obtained from a power generation element. An object of the present invention is to provide a power supply circuit that can be reduced in size and power consumption.

In order to achieve the above-described object, according to the first aspect of the present invention, a power generating element, a boosting circuit unit that boosts a voltage obtained from the power generating element by a switching operation of the switch element, and an output voltage from the boosting circuit unit A power supply circuit unit that generates a constant voltage based on the power supply circuit unit that supplies the constant voltage to a load circuit, and includes an oscillation circuit that turns on and off the switch element in the booster circuit unit, A control circuit unit that detects a power generation amount of the element and controls power supply to the oscillation circuit based on the power generation amount, and the boost circuit unit includes a first output voltage output to the power supply circuit unit; An output unit that outputs a low second output voltage is provided, and the control circuit unit supplies the second output voltage as a power source of the oscillation circuit when the second output voltage is equal to or higher than a predetermined value. Second When the output voltage is below the predetermined value, as long as the power generation amount of at least the power generating element is equal to or greater than a predetermined amount, be one that performs control to supply the first output voltage as a power supply of the oscillation circuit, wherein The booster circuit unit boosts the voltage of the power generation element and outputs the second output voltage, and boosts the second output voltage output by the booster unit to boost the first output It is characterized by being divided into a subsequent booster that outputs a voltage .

According to the first aspect of the present invention, by controlling the power supply of the oscillation circuit according to the amount of power generated by the power generation element, the required power in the oscillation circuit can be reduced to save power and the required power can be reduced. Accordingly, the size of the circuit element itself can be reduced, and the entire apparatus can be reduced in size. In addition, the power consumption of the oscillation circuit can be reduced with a simple circuit configuration. Further, the charge current capability can be improved by using a two-stage boosting booster circuit section.

In the invention of claim 2, in the invention of claim 1, wherein the booster circuit portion is characterized by being composed by a switched capacitor circuit.

According to a third aspect of the present invention, in the second aspect of the present invention, the booster circuit unit is formed of an ASIC, and the pump capacitor element of the booster unit in the previous stage is an external capacitor element outside the ASIC.

According to the invention of claim 3 , the circuit configuration can be reduced in size, and when the power supply device is incorporated together with the power generation element, it is possible to avoid an increase in the size of the device, and the pump capacity element of the boosting unit in the preceding stage By sufficiently increasing the capacity, it is possible to secure a current capability that cannot be obtained by ASIC alone. Further, by adopting a two-stage boosting method, the charging current capability can be improved compared to the conventional case with the same chip area.

According to a fourth aspect of the present invention, in the second or third aspect of the present invention, the ASIC includes an external terminal externally provided with a pump capacitance element used in the subsequent boosting section.

According to the fourth aspect of the present invention, when the current capability of the power generation element is large, it is possible to increase the charging current by increasing the capacity of the pump capacity element in the subsequent boosting section.

According to a fifth aspect of the present invention, in the invention according to any one of the second to fourth aspects, the switch element for parallel connection of each pump capacitor element is configured by an NMOS transistor among the switch elements of the boosting units at the preceding stage and the subsequent stage. It is characterized by being.

According to the invention of claim 5 , even if the input voltage from the power generating element is low, it can be driven stably, the current capability is improved, and the circuit scale can be reduced as compared with the case of the analog switch configuration. In addition, since the gate capacitance of the switch element can be suppressed, the current consumption of the entire pump-up circuit can be suppressed.

According to a sixth aspect of the present invention, in the first to fifth aspects of the invention, the control circuit section includes means for detecting the power generation amount of the power generation element, and the power generation amount of the power generation element detected by the means is a predetermined amount. In the above-described configuration, there is provided means for supplying power to the oscillation circuit and stopping supply of power to the oscillation circuit when the power generation amount falls below the predetermined amount.

According to the invention of claim 6 , the power of the power generation element can be used effectively, and when the power generation amount of the power generation element falls below a predetermined amount, wasteful consumption of the circuit can be suppressed by stopping the power supply to the oscillation circuit. .

According to a seventh aspect of the present invention, in the sixth aspect of the present invention, the power supply to the oscillation circuit is stopped in a state where the pump capacitance element of the booster circuit unit is charged by the output of the power generation element. .

According to the seventh aspect of the present invention, even when the power generation amount of the power generation element is very small and the power supply to the oscillation circuit is stopped, the power of the power generation element is used to charge the pump capacity element of the booster circuit unit to generate power. The power of the element can be used without waste, and when the amount of power generated by the power generation element increases and the oscillation circuit starts operating, the boosted voltage of the booster circuit unit can be obtained instantaneously.

According to an eighth aspect of the present invention, in the invention according to any one of the second to seventh aspects, the on-time of the switch element for parallel connection is delayed from the off-time of the switch element for series connection of the pump capacitor elements of the booster circuit section. And the booster circuit unit includes a delay circuit that generates a gate signal from the clock signal of the oscillation circuit that delays the on time of the series connection switch element from the off time of the parallel connection switch element. the delay circuit, in series a first resistor having one end to the power supply voltage is connected, and a second resistor having one end connected to ground, the PMOS transistor and the NM O S transistor having a drain and gate connected, respectively A source of the PMOS transistor is connected to the other end of the first resistor, and a source of the NMOS transistor is connected to a second The clock signal generated by the oscillation circuit is input to the gate of the NMOS transistor, and the output from the drains of both transistors is input to two sets of inverter elements having different threshold values to be connected to the other end of the transistor. It is characterized by obtaining.

According to the invention of claim 8 , the delay circuit delays the on-time of the switch element for parallel connection from the off-time of the switch element for series connection of the pump capacitance elements, and the off-time of the switch element for parallel connection. By creating a gate signal that delays the on-time of the switch element for series connection, it is possible to prevent the switch elements from being turned on at the time of switching between the series connection and the parallel connection of the pump capacitance elements, thereby preventing a reverse current flow. In addition, current consumption in the delay circuit can be suppressed. Further, when it is desired to control the clock by applying a voltage from the outside in ASIC inspection or the like, the first and second resistors function as current limiting resistors, and can prevent the transistors in the delay circuit from being destroyed.

A ninth aspect of the invention is characterized in that, in any one of the first to eighth aspects of the invention, a storage element is connected to the output of the power supply circuit unit so as to be in parallel with the load circuit.

According to the ninth aspect of the present invention, even when the power generation amount of the power generation element cannot be obtained, power can be supplied from the power storage element to the load circuit, so that the operation life of the device as the assembly destination can be extended.

According to a tenth aspect of the present invention, in the ninth aspect of the invention, when the power generation amount of the power generation element is equal to or greater than a predetermined amount, the power storage element is charged with the output of the power supply circuit unit, and the power generation amount of the power generation element The power is supplied to the load circuit when the power becomes less than a predetermined amount.

According to the invention of claim 10 , the power storage element can be charged when the power generation amount of the power generation element is sufficient. Therefore, when the power generation amount cannot be obtained, the power for supplying power from the power storage element to the load circuit is It can be secured sufficiently.

According to an eleventh aspect of the present invention, in any of the ninth and tenth aspects, when the constant voltage output of the power supply circuit unit is in a predetermined range including the output voltage of the storage element, the constant voltage output is supplied to the load circuit and Output switching control means for directly connecting to the power storage element and connecting a constant voltage output to the load circuit and the power storage element via an output limiting resistor when the output voltage of the power storage element falls below the predetermined range. It is characterized by being.

According to the eleventh aspect of the present invention, the state in which the electric power of the power generation element cannot be sufficiently obtained continues, the boosting operation of the boosting circuit unit is stopped, and the output voltage of the storage element is lowered to a predetermined range or less, and then the boosting circuit unit When the step-up operation is resumed, a stable voltage can be supplied to the storage element from the power supply circuit unit using the boosted voltage of the booster circuit unit as an input power source.

  The present invention has an effect that it is possible to efficiently use minute electric power to achieve power saving and longer life.

  Hereinafter, the present invention will be described with reference to embodiments.

(Embodiment 1)
First, a cell configuration of a solar battery generally used as a power generation element will be described. In general, as shown in FIGS. 2 (a) and 2 (b), the cell configuration of a solar cell is such that n single cell solar cells 1 are connected in series in one panel, and about 0.5 × n A high voltage [V] is generated to operate the load circuit. However, in this configuration, there is a problem that even if one of the cells enters the shade or breaks, it does not generate power and does not function as a power circuit. In particular, when the entire apparatus incorporating the power supply circuit is reduced in size, the light receiving area of one cell is reduced, so that unevenness in light irradiation is greatly affected. As a countermeasure, there is a method of operating the load circuit by boosting the voltage of about 0.5 V obtained by the single cell solar cell 1 by the booster circuit unit 2 as shown in FIG. This method can cope with the above problem and has an advantage that the shape of the cell can be freely processed, and is effective for downsizing the power supply circuit. Further, even when a power generating element other than the solar cell 1 is used, it is possible to widely cope with a power generating element having a low voltage output.

Next, the power supply circuit of the present embodiment is assumed to be used indoors, for example, the size of the light receiving area of the solar cell is 10 cm ² . In this case, the solar cell 1 has a problem with the amount of power generation (= current capability) under a low illuminance of about 10 lux. As for indoor use, amorphous solar cells (or dye-increased solar cells) have a low illuminance generation power compared to other solar cells, but their current capability is on the order of several tens of microamperes (microamperes). The step-up operation must be performed with the current of several tens of μA. In order to supply a stabilized power by boosting / accumulating the weak energy (low voltage of about 0.5 V) obtained from the solar cell 1 with high efficiency, the current consumption of the power supply circuit itself is several μA. It must be kept to a certain extent. Moreover, in order to be able to install a power supply circuit (module) anywhere, it is necessary to reduce the overall size.

Considering the above contents, it is difficult to configure the power supply circuit by discrete components, it is desirable to construct a semiconductor integrated circuit (hereinafter referred to as AS I C). Also when considering the AS I C of the power supply circuit with low current consumption, good conversion efficiency, without the need less current capability to the oscillation circuit used in the step-up circuit unit, etc., switched composed of pump capacity element and a switching element A booster circuit is optimal.

  The present embodiment is configured in view of the above points, and as shown in FIG. 1, a pump-up composed of a switched capacitor booster circuit that boosts the output voltage VIN of the solar cell 1 used as a power generation element to a voltage V01 and a voltage VA. The circuit 20 and the pump-up circuit 20 oscillate a clock signal for generating a gate signal of a switch element described later, and the clock signal from the oscillation circuit 21 is leveled up to generate a gate signal of the switch element described later. A booster circuit unit 2 having a level shift circuit 22 for charging, and a voltage VA boosted by the booster circuit unit 2 is stabilized by a regulator circuit 50 to charge a secondary battery 3 as a storage element and to load circuit 4 The power supply circuit unit 5 to be supplied to the power supply unit and the control circuit unit 6 for controlling the booster circuit unit 2 and the power supply circuit unit 5 are provided with some external elements Except for being configured by ASIC 7.

  Next, the configuration of each unit will be described in detail.

  First, the pump-up circuit 20 of the booster circuit unit 2 uses the switched capacitor booster circuit as described above. The switched capacitor booster circuit basically has a configuration as shown in FIG. -1) All (seven in the illustrated example) capacitive elements (hereinafter referred to as pump capacitive elements) C1 to C7 having the same capacitance value are all input voltage via switch elements SW1 and SW1 'connected in series at both ends. The charge Q (= C × VIN) is stored in each of the pump capacitative elements C1 to C7 in parallel with VIN. Thereafter, the switch elements SW1 and SW1 ′ are opened and the switch element SW2 is turned on, so that the pump capacitance elements C1 to C7 are connected in series to obtain a boosted voltage VA that is n times (8 times) the input voltage VIN. ing. This switched capacitor booster circuit requires switch elements SW1, SW1 ', SW2 for switching parallel / series connection and a circuit for generating a gate signal for driving these switch elements SW1, SW1', SW2.

  On the other hand, when the ASIC 7 constitutes a switched capacitor booster circuit, the switch element is constituted by a transistor in the ASIC 7. At this time, the switch element cannot be completely turned on / off unless the gate potential of the switch element is set to the highest potential in the device circuit. Therefore, a level shift circuit 22 that generates a clock signal and converts the output voltage of the oscillation circuit 21 to the maximum potential is also necessary.

That is, as shown in FIG. 3 (a), assuming that the output voltage of the solar cell 1 is the input voltage VIN and the voltage of about 0.5V is boosted 8 times to 4V (= VA). As shown in the figure, seven elements are required, and it is desirable to use a two-layer polysilicon capacitor element that is less affected by parasitic capacitance than a general poly diffusion capacitor. Here, the size of the ASIC 7 is assumed to be 3 mm square, the total capacitance value in the ASIC 7 is assumed to be 1400 pF (200 pF per piece), and the oscillation period is equivalent to 3.5 μs (: 285 kHz, which can be realized by the ASIC. 1), in the circuit configuration of FIG. 1, the regulator circuit 50 of the power supply circuit unit 5 uses the boosted voltage VA as an input voltage and needs to match the charging voltage of the secondary battery 3 with the output voltage VOUT as described above. There is. Here, when a lithium manganese secondary battery is used as the secondary battery 3 and its center voltage 3.15 ± 0.15V is used, the maximum standard value MAX of the charging voltage is 3.3V, and the regulator circuit 50 is normally operated. In order to operate, the input voltage, that is, the boosted voltage VA in the booster circuit unit 2 needs to be at least 3.3 V or more. With respect to the boost voltage VA, when the charge is stored by connecting the pump capacitance elements in parallel and then switched to the series connection and the charge circuit 4 is supplied with the charge, the equivalent circuit shown in FIG. A voltage drop ΔVA obtained from the equation (1) occurs. When boosting to 4 V using seven pump capacitance elements (capacitance value 200 pF), the charging current (load circuit current) obtained from the equation (1) is about 6 μA and ΔVA is 0.7 V. In other words, the input voltage of the regulator circuit 50 when more load current increases becomes less 3.3V, normally the regulator circuit 50 does not operate. As a result, a sufficient current cannot be supplied from the power supply circuit to the load circuit 4. In the equivalent circuit of FIG. 3B, CX represents the combined capacity of the seven pump capacitance elements, and Q represents the charge.

Q = C × Δ VA = I × t (1)
However, C: capacitance value of the pump capacitor element, I: charging current, t is the switching cycle of the switch elements SW1, SW1 ′ and switch element SW2, as described above, the basic switched capacitor booster circuit of FIG. When used as the up circuit 20, the AS I C7 does not have sufficient output current capability.

  Therefore, the pump-up circuit 20 of the booster circuit unit 2 of the present embodiment boosts the input voltage VIN by one pump capacitance element C1 as shown in FIG. 3C, and the capacitance by the boosted voltage V01. A circuit comprising a booster 20a at the previous stage for charging the element C01 and a booster 20b at the subsequent stage for boosting the voltage V01 four times by using three pump capacitance elements C2 to C4 to obtain the voltage VA. Yes. An external element outside the ASIC 7 is used as the pump capacitance element C1, and the pump capacitance elements C2 to C4 are configured using a two-layer polysilicon capacitance inside the ASIC 7, and the capacitance value is 400 pF (total 1200 pF divided by three). Value).

The operation of the pump-up circuit 20 configured as described above is as follows. First, in the booster 20a, the switch elements SW1 and SW1 ′ are turned on by the gate signal generated by the level shift circuit 22 based on the clock signal generated by the oscillation circuit 21, and a voltage of about 0.5V from the thick battery 1 is obtained. To charge the pump capacitance element C1. After this charging, the switch elements SW1 and SW1 ′ are turned off by the gate signal from the level shift circuit 22, the switch element SW2 is turned on, and the pump capacitor element C1 is connected to the solar cell 1 in series. By repeating this parallel connection and series connection of the capacitor C1, the output voltage of the booster 20a becomes approximately 1.0V which is twice the voltage of 0.5V. The subsequent booster 20b uses the voltage of about 1.0 V as an input voltage, turns on the switch elements SW1 and SW1 ′ corresponding to the pump capacitance elements C2 to C4, and inputs the pump capacitance elements C2 to C4. In parallel with the voltage, each is charged to about 1.0 V. After this charging, the switch elements SW1 and SW1 ′ are turned on by the gate signal from the level shift circuit 22, and the switch element SW2 is turned on. Pump capacity elements C2 to C4 are connected in series. By repeating this, the voltage VA boosted to 4.0 V is output. When the above formula (1) is calculated, the drop voltage ΔVA is 0.7 V and the charging current (load circuit current) is about 26 μA, which is greatly improved as compared with the basic circuit configuration of FIG. It will be. When the load current, that is, the charging current is 20 μA, the output V01 of 1.0 V needs to have a current capacity of 80 μA, which is at least four times that. Considering that the capacitance value of the pump capacitive element C1 is 400 pF in the ASIC 7 similarly to the other pump capacitive elements C2 to C4, the voltage drop of the voltage V01 is about 0.7 V (= 80 μA × 3.5 μs / 400 pF). ) And the voltage VA is lowered accordingly. In order to be able to ignore the voltage drop of the voltage V01 which is the reference of the boost voltage VA, it is preferable to set the pump capacitance element C1 to about 100 nF (in this case, ΔV01 is several mV). since it is difficult to built the aS I C, the pump capacity element C1 as an external device to be connected between the terminals CN1, CP1, and using less less small chip capacitor leakage current.

As can be seen from the above equation (1), it is understood that the charging current is better as the capacity of the pump capacity element is larger. Therefore, the connection terminal (CN2-CP2.CN3-CP3, CN4-CP4 in FIG. 1) to which the capacitive element can be added in parallel is provided for the pump capacitive element built in AS I C7. Thereby, when the solar cell 1 is always irradiated with light and the power generation capability of the solar cell 1 is large, the charge current capability can be increased by connecting an external chip capacitor in parallel to each pump capacitance element. it can.

  By the way, the level shift circuit 22 and the oscillation circuit 21 constitute a clock generation unit for generating a gate signal (clock signal) for driving each switch element of the pump-up circuit 20 as described above.

  Next, a specific configuration of the oscillation circuit 21 of the clock generation unit will be described.

  The oscillation circuit 21 is configured based on a multivibrator oscillation circuit as shown in FIG. 4, and this circuit configuration has a small circuit scale and realizes low current consumption. The oscillation period T is T = 2R0 · As indicated by C0 · ln3, it is determined by the capacitance of the resistor R0 and the capacitor C0. Here, the clock signals CLKA and CLKB output by oscillation are input to the level shift circuit 22 and are delayed, and are output as gate signals of the switch elements SW1, SW1 ′ and SW2, but the period of the gate signal Is determined by the oscillation period T (= 1 / frequency f) of the oscillation circuit 21. Therefore, as can be seen from the above equation (1), the oscillation period T greatly affects the charging current (load current), and the oscillation frequency f is preferably faster. Therefore, it is preferable that the resistance R0 and the capacitive element C0 have smaller values.

  Therefore, in the oscillation circuit 21 in the present embodiment, the resistor R0 uses a diffused resistor having a small variation, and the capacitive element C0 uses a two-layer polysilicon capacitor without a parasitic capacitive element to suppress the influence of the parasitic capacitance. However, if the resistance R0 is too small, the current consumption of the oscillation circuit 21 itself becomes large. Therefore, for each of the resistance R0 and the capacitive element C0, the resistance is determined by simulation so that the period T is 3.5 μs. As R0, 1.5 MΩ was obtained, and as the capacitive element C0, 1 pF was obtained.

  The current consumption of the oscillation circuit 21 having the configuration shown in FIG. 4 greatly depends on the power supply voltage VOSC, the inversion threshold value of each inverter is near VOSC / 2, and a through current flows near Vgs = VOSC / 2 of the transistor of the inverter configuration. . If the power supply voltage VOSC increases, the inversion threshold also increases, so that the Vgs of the inverter configuration transistor increases and the through current also increases.

  Here, the oscillation circuit 21 supplies the voltage of the secondary battery 3 as the power supply voltage VOSC through the diode D1 and the switch element SWA, and the output voltage V01 of the booster 20a of the pump-up circuit 20 as the power supply voltage VOSC. As shown in FIG. 1, the switch elements SWA and SWB shown in FIG. 1 are switched on / off in response to a control signal from the control circuit unit 6 to switch the power supply to the oscillation circuit 21. Configure the means.

  That is, the control circuit unit 6 operates using the output voltage VA of the secondary battery 3 or the pump-up circuit 20 as a power source, and monitors the output voltage VIN of the solar cell 1 by the reference power source circuit 60 as shown in FIG. A reference voltage VR3 for detecting), a reference voltage VR2 for monitoring the output voltage V01 of the pump-up circuit 20, and a reference voltage VR1 for a regulator circuit 50 to be described later. The reference voltage VR3 is generated by a comparator CP2. The output voltage VIN of the solar cell 1 is compared, and the reference voltage VR2 is compared with the voltage V01 by the comparator CP1.

  The outputs of the comparators CP1 and CP2 pass through a logic circuit, the switch element SWB is controlled by the output of the NOR gate NOR1 of the logic circuit, and the switch element SWA is controlled by the output of the AND gate AND1. Reference numeral 61 denotes a reference current circuit.

Here, in the first state in which the output voltage VIN of the solar cell 1 is almost zero and the boosted voltage V01 of the booster 20a is not generated, that is, the outputs of the comparators CP1 and CP2 are at “H” level. And a second state in which the output voltage VIN is generated from the solar cell 1 by light irradiation and exceeds the reference voltage VR3, but the output voltage V01 of the booster 20a has not yet exceeded the reference voltage VR2, that is, a comparator. When the output of CP1 is at "H" level and the output of comparator CP2 is at "L" level, the output voltage VIN is generated from the solar cell 1 upon receiving light irradiation and exceeds the reference voltage VR3, and the output voltage of the booster 20a The third state in which V01 exceeds the reference voltage VR2, that is, the state in which the outputs of the comparators CP and CP2 are both “L” level is discriminated by the logic circuit, In the first state, the outputs of the NOR gate NOR1 and the AND gate AND1 both become “L” level, and the switch elements SWB and SWA are both turned off. In the second state, the output of the NOR gate NOR1 is “L” level. The output of the AND gate AND1 becomes “H” level, and the switch element SWB is turned off and the switch element SWA is turned on. Further, in the third state, the output of the NOR gate NOR1 is “H” level. The output becomes “L” level, and the switch element SWB is turned on and the switch element SWA is turned on.

  Thus, in a state where sunlight is not incident, there is almost no power generation amount of the solar cell VIN, and the voltage VIN is almost 0 V, so that it is below the reference voltage VR3. That is, it is in the first state. In this state, since the switch element SWA is off, power is not supplied from the secondary battery 3 to the oscillation circuit 21 of the booster circuit 2 via the diode D, and the oscillation circuit 21 is in a stopped state, so that the secondary battery There is no wasteful power consumption of 3.

  Then, when there is light irradiation and the amount of power generation from the solar cell 1 increases and the output voltage VIN exceeds the reference voltage VR3, that is, in the second state, the switch element SWA is turned on and the secondary battery 3 starts the oscillation circuit 21. Is supplied with power, and the oscillation circuit 21 starts oscillation.

  When this oscillation starts, gate signals are sent to the switch elements SW1, SW1 ′ and SW2 of the pump-up circuit 20 via the level shift circuit 22 at a predetermined cycle, and the boosting units 20a and 20b start the boosting operation. Output voltages V01 and VA are generated, and the output voltage VA becomes an input voltage of the regulator circuit 50 of the power supply circuit unit 5. The constant voltage output VOUT stabilized by the regulator circuit 50 is supplied to the secondary battery 3 and the load circuit 4. Supplied as

  When the output voltage V01 exceeds the reference voltage VR2, that is, in the third state, the switch element SWA is turned off and the switch element SWB is turned on, so that the power supply of the oscillation circuit 21 is supplied from the secondary battery 3 to the booster 20a. The voltage is switched to V01.

  By controlling the power supply of the oscillation circuit 21 in this way, the power consumption of the oscillation circuit 21 can be reduced to at least about 1/3 compared with the case where the oscillation circuit 21 is always supplied with power.

  The oscillation circuit 21 is supplied with power from the boosting unit 20a that doubles the voltage, but of course, a voltage of 3 times, 4 times,..., N times may be used. However, a lower voltage is better in order to reduce the overall power consumption as much as possible. That is, the oscillation circuit 21 can be any power supply voltage of 1V. Further, if the ASIC 7 is miniaturized and low threshold drive is realized, and the oscillation circuit 21 can be driven by the output voltage VIN (single voltage) of the single-cell solar cell 1 itself, further power consumption can be reduced.

  By the way, the pump-up circuit 20 used in the present embodiment is configured by the switched capacitor booster circuit as described above. Specifically, the pump-up circuit 20 is configured by the ASIC 7, and each pump capacitance element is configured as shown in FIG. The switch elements SW1 and SW1 ′ for connecting the transistors in series are constituted by PMOS transistors or NMOS transistors, and the switch element SW2 for connecting the pump capacitance elements in parallel is constituted by an NMOS transistor.

Here, the analog switch in the switch element SW1 or SW2 connected to P M OS transistor and NMOS transistor in parallel as shown in FIG. 5 (b), when the switch element SW1 'using an analog switch by NMOS transistors When the input voltage VIN is used as 1 V or higher, it can be reliably turned on / off. However, when the low voltage of about 0.5 V of the single cell solar cell 1 is used as the input voltage VIN, it cannot be handled. . That is, when constituting the switch element SW1 of the pump capacitor element C1 with PMOS transistors, the threshold of the transistor is in the vicinity of 0.5V, there is a no possibility in full on the P M OS transistor. Further, in the pump-up circuit 20, in order to accelerate the charging of the pump capacitance element, it is necessary to increase the current capacity by increasing the channel width W / channel length L of each transistor, but at the same time the gate capacitance increases. The gate signal is lost. As a result, the inrush current at the time of switching the switch increases, and at the same time, the current consumption increases due to charging and discharging of this capacity. With such an analog switch, the current consumption will increase it means that the gate capacitance of the NMO S and PMOS transistors are attached.

  Therefore, in the present embodiment, the circuit configuration as shown in FIG. 5A described above is used to optimize the switching element so as to reduce the current consumption.

  Here, the switch element configuration of the boosting unit 20a in the previous stage will be described. In the circuit configuration shown in the figure, the switch elements SW1 and SW1 'operating at an input voltage VIN of 0.5V are configured by NMOS transistors. If the switch elements SW1 and SW1 'are NMOS transistors, even if the input voltage VIN is about 0.5V, a signal having the highest potential is input to the gate, so that the switch elements SW1 and SW1' can be turned on reliably. On the other hand, since the output point of the output voltage V01 is a place that requires current capability, each of the switch elements SW2 connected in series is composed of an NMOS transistor. When an NMOS transistor is used, a substrate bias effect occurs, but when the potential at both ends of the transistor is low (1 V or less), the influence of the substrate bias effect is small.

  Next, the switching configuration of the subsequent booster 20b will be described. Each switch element SW1 of the boosting unit 20b may be constituted by a PMOS transistor. However, when the size is increased, the parasitic capacitance between the n-well (I) and the p-substrate increases as shown in FIG. Become. At this time, when the substrate (n-well (I)) is connected to the pump capacitance element (for example, C2), the parasitic capacitance element Cs is attached to the connection point and p-sub (II), and the pump-up loss is large. turn into.

  Conversely, when the substrate (n-we11 (I)) is connected to the voltage V01, the maximum potential is input to the gate, and when the transistor is turned off, the diode is turned on from the connection point toward the voltage V01, resulting in loss. appear. Next, considering that the substrate (n-well (1)) is connected to the maximum potential VA, in this case, a potential difference is generated between the substrate and the source, so that the influence of the substrate bias effect of the transistor is a problem. It becomes. Therefore, in the present embodiment, these parallel connection switch elements SW1 are also configured by NMOS transistors having current capability.

  For example, in the circuit configuration of FIG. 5A, when the switch SW1 corresponding to the pump capacitor C3 is turned on, the source is V01 voltage (1V), the drain is 3V, and the gate has a VA potential (4V). Is input, since Vgs = 3V, the transistor is turned on (the 4V side is open and has no capability, so in this case, the source is on the 1V side). Further, since the transistor constituting the switch element SW1 'on the GND side of the pump capacitance element C3 is reliably turned on and becomes GND, the drain instantaneously drops to about 1 V due to the coupling of the pump capacitance element C3.

  As a result, the transistors constituting the switch element SW1 are turned on sufficiently exceeding the threshold value.

  On the other hand, the switch elements connected in series with the pump capacitance elements C2 to C4 such as the switch elements SW2 of the boosting unit 20b are configured with PMOS because if they are configured with NMOS transistors, they are less likely to be turned on later due to the substrate bias effect. .

  The gate signals of the switches SW1, SW1 ′, SW2 are the same for the series-connected PMOS transistor shown in FIG. 6A and the series-connected NMOS transistor shown in FIG. The three types of signals for the NMOS transistors for parallel connection shown in c) are generated, but a delay time of Δt is provided so that the rise and fall of the gate signal for series connection and the gate signal for parallel connection do not overlap. Therefore, the level shift circuit 22 delays the clock signal oscillated from the oscillation circuit 21 and generates a gate signal. If the gate signals overlap, a backflow occurs when the up-capacitor element is switched between parallel connection and series connection, and a large loss occurs as a whole of the boost (decrease in boost conversion efficiency).

  As described above, the switch elements SW1 and SW1 ′ for parallel connection of the pump capacitative elements of the pump-up circuit 21 are all configured by NMOS transistors, so that they can be reliably turned on / off even with an input voltage VIN of about 0.5V. Since the amount of transistors for switch elements can be reduced compared to the switch configuration, each switch element gate capacitance can be suppressed and the switch switching response can be made faster, thereby suppressing the through current at the time of switch switching. Therefore, the power consumption of the booster circuit unit 2 can be reduced.

  Next, a specific configuration of the level shift circuit 22 that constitutes the clock generation unit together with the above-described oscillation circuit 21 will be described.

  As shown in FIG. 7A, the level shift circuit 22 of the present embodiment sets the voltage values of the clock signals CLKA and CLKB (the voltage value of the secondary battery 3 or the boosted voltage V01) output from the oscillation circuit 21 to the highest potential. A delay circuit 22c having a level shift unit 22a for shifting to (the voltage of the secondary battery 3 or the boosted voltage VA), and delay resistors Ra and Rb for smoothing the rise of the clock signal provided on the output side; A delay of Δt is obtained by converting the clock signal whose rise is smoothed by the delay circuit 22c into inverted signals having different widths by the inverter elements NT1a and NT1b having different thresholds, and returning them to the original by the inverter elements NTc and NTc. The phase is reversed by making a gate signal that does not overlap the rise with time and by inverting it with inverter elements NTd and NTd. And a logic circuit 22b to make over preparative signal. With this configuration, the level shift circuit 22 of this embodiment has a simple circuit configuration and can suppress current consumption. Note that when the clock signal is fixed by applying an external voltage to the LVSFO terminal in ASIC inspection or the like, the resistors Ra and Rb become current limiting resistors, thereby preventing transistor breakdown.

  That is, as shown in FIG. 7B, in the case of the configuration in which the clock signal is delayed by the logic circuit 22b ′ after the level shift by the level shift unit 22a ′ that does not use the resistors Ra and Rb, the scale of the logic circuit configuration becomes large. The current consumption is large. When the time difference Δt of the clock signal, that is, the gate signal of the switch element for parallel connection with respect to the gate signal of the switch element for series connection becomes longer, the on-time of the switch element for parallel connection becomes shorter, and the pump capacitance element Therefore, in the configuration for creating the delay time only with the logic circuit, it is necessary to delay the delay circuit with a slow response and perform feedback.

  Next, a specific configuration of the regulator circuit 50 of the power supply circuit unit 5 used in the present embodiment will be described with reference to FIG.

  The regulator circuit 50 includes an output path including a current limiting resistor Rx as an output unit to the load circuit 4 and the secondary battery 3, and an output path not included, and switch elements SWa and SWb provided in the output paths. The output path is switched by turning on / off.

  These switch elements SWa and SWb are connected to the input terminal of the regulator circuit 50 through the diode D together with the voltage VA of the booster 20b (that is, the output voltage VOUT) to the resistance R1 of several tens of MΩ. It is controlled by the output of the comparator CP0 that compares the voltage divided by R2 with the reference voltage VR1 generated by the above-described reference power supply circuit 60 of the control circuit unit 6.

  Further, the regulator circuit 50 reduces the overcharge and overdischarge of the secondary battery 3, and the output voltage value VOUT is 3.15V when the power supply voltage of the regulator circuit 50, that is, the voltage VA of the booster 20a is 3.3V or more. It is necessary to produce an accurate output voltage of ± 0.15V. For this purpose, as shown in the drawing, a reference voltage VR1 formed by a reference power supply circuit 60 in the control circuit 6 and made up of a relatively stable constant voltage of 1V is supplied to an amplifier AP, a series control transistor Q0, and a voltage detection tens of MΩ. The voltage dividing circuit including the resistors R3 and R4 and the 3-bit electronic trimming circuit 51 are configured to be 3.15 times.

  Here, if there is a variation in the constant voltage generated by the reference power supply circuit 60, the variation is also 3.15 times and appears in the output of the regulator circuit 50. Therefore, in the regulator circuit 50, the electronic trimming circuit 51 increases the accuracy. I have to.

  Here, when the solar cell 1 is not exposed to light for a long time and the voltage of the secondary battery 3 is 3 V or less (below the MIN value of the charging voltage), the solar cell 1 is irradiated with light. Since the voltage VA of the pump-up circuit 20 rises and the output voltage VOUT is 3 V or less until the regulator circuit 50 operates, the output VX of the amplifier AP of the regulator circuit 50 becomes “L” level. A current flows in a system of voltage VA-voltage VOUT. Thereafter, the regulator circuit 50 takes in the output voltage VOUT divided by the voltage dividing circuit of the resistors R3 and R4 of several tens of MΩ into the electronic trimming circuit 51, and the non-amplification of the amplifier AP so as to gradually increase the output voltage VOUT to 3.1V. The voltage returned to the inverting input terminal is controlled and the secondary battery 3 is charged with the output voltage VOUT.

  Here, since the power supply circuit of the present embodiment is reduced in size as a whole, the light receiving area of the solar cell 1 is also small, and the charging current to the secondary battery 3 is also small accordingly. Therefore, when the state in which the light irradiation cannot be obtained continues and the voltage value of the secondary battery 3 is a low value (the source / drain voltage Vds of the control transistor Q0 is large), if the light irradiation is subsequently obtained, A current equal to or higher than the charging current of the secondary battery 3 is drawn, and the voltage VA does not rise for a while because of the booster 20b.

  Therefore, when the output voltage VOUT, that is, the voltage of the secondary battery 3 is low, the above output path is switched, and the limiting resistor Rx is inserted into the output of the regulator circuit 50 and the secondary battery 3. As the limiting resistance Rx is increased, the state in which the boosted voltage VA of the boosting unit 20b of the pump-up circuit 20 does not increase can be alleviated. However, the voltage drop is caused by the consumption current of the load circuit 4.

Accordingly, when the solar cell 1 is irradiated with light and the output voltage VOUT is 3.15V ± 0.15V (predetermined range), that is, when the voltage VA is higher than the voltage of the secondary battery 3, the non-inversion of the comparator CP0. The voltage at the input end becomes higher than the reference voltage, and the output of the comparator CP0 at this time turns on the switch element SWa, turns off the switch element SWb, and does not insert the limiting resistor Rx into the output path. not obtained and when the output voltage of the secondary battery 3 is equal to or less than 3.0 V, the voltage at the non-inverting input terminal of the comparator CP 0 is a reference voltage or less, the comparator CP0 inverts the output, this inverted signal The switch SWa is turned off and the switch SWb is turned on, and the limiting resistor Rx is inserted into the output path.

  By providing the power supply circuit unit 5 including such a regulator circuit 50, a situation where power cannot be obtained from the solar battery 1 continues, and the output voltage of the secondary battery 3 is set by the regulator circuit 50. A stable output voltage VOUT can be supplied to the secondary battery 3 even when the output of the solar battery 1 is obtained after the voltage drops below VOUT and the boosting operation of the pump-up circuit 20 is resumed.

  In the present embodiment configured as described above, the secondary battery 3 is provided on the output side of the regulator circuit 50 as described above, and the situation is such that light irradiation cannot be obtained. For this purpose, the control circuit unit 6 for determining whether or not the output voltage VIN of the solar cell 1 exceeds a certain value is provided as described above. As a result, when light irradiation is obtained, current is supplied to the load circuit 4 by the generated power from the solar cell 1, and at the same time, the secondary battery 3 is charged. Electric power can be supplied from the battery 3 to the load circuit 4.

  On the other hand, when the secondary battery 3 is used, there are problems of overcharge and overdischarge. However, by making the output voltage VOUT of the regulator circuit 50 accurate, the secondary battery 3 can be prevented from firing and charged normally. It is. Further, the entire power consumption can be reduced by driving the power supply voltage of the oscillation circuit 21 with the voltage V01 of the boosting unit 20a.

Further, the size of the device can be reduced by the ASIC, and the life of the device can be extended by reducing the overall power consumption even in a situation where the power generation amount of the solar cell 1 as a whole cannot be obtained.
(Embodiment 2)
In the present embodiment, as shown in FIG. 9, in the control circuit unit 6, the output of the output voltage V01 of the pump-up circuit 20 and the switch element SWC inserted between the solar cell 1 and the output of the comparator CP2 are inverted. The second embodiment is different from the first embodiment in that a NOR gate that takes a negative OR of the signal obtained by inverting the output of the comparator CP1 and controls the switch element SWC by the output is provided.

  That is, as described in the first embodiment, when the sunlight is not irradiated, that is, when the voltage VIN is equal to or lower than the reference voltage VR3, the switching elements SWA and SWB are turned off and the oscillation circuit 21 and the shift level circuit 22 involved in the boosting operation. However, at this time, the output voltage VIN of the solar cell 1 is equal to or lower than the reference voltage VR3, and the amount of power generation is small, but it is not in a state of no power at all.

  Therefore, in this embodiment, the output of the NOR gate NOR2 is set to “H” in that state, and the switch element SWC is turned on, so that the electric power of the solar cell 1 is stored in the capacitor element C1 constituting the booster 20a of the pump-up circuit 20. By doing so, the electric power of the solar cell 1 is used effectively. That is, since the voltage V01 of the pump capacitor element C1 is a voltage that is a reference for boosting, it is desirable that the voltage V01 be a higher voltage. When the obtained state is obtained, a predetermined boosted voltage can be instantaneously obtained, and as a result, power can be supplied to the load circuit 4 and the secondary battery 3 by the boosted voltage VA of the booster 20b. When the output voltage VIN of the solar cell 1 exceeds the reference voltage VR3, the output of the NOR gate NOR2 is inverted to the “L” level, so that the switch element SWC is turned off and the output voltage VIN of the solar cell 1 is supplied to the pump-up circuit 20 From the output terminal of the boosted voltage V01.

1 is an overall circuit configuration diagram of Embodiment 1. FIG. It is explanatory drawing of a solar cell. (A) is a basic circuit configuration diagram of a switched capacitor booster circuit, (b) is an equivalent circuit diagram thereof, and (c) is a circuit configuration diagram of a pump-up circuit used in the first embodiment. 2 is a specific circuit diagram of an oscillation circuit used in Embodiment 1. FIG. (A) is a specific circuit diagram of a pump-up circuit used in the first embodiment, (b) is a specific circuit diagram of a comparative pump-up circuit, (c) is a cross-sectional view showing the structure of the switching element. 4 is a timing chart of gate signals of switch elements of a pump-up circuit used in the first embodiment. (A) is a specific circuit diagram of a level shift circuit used in the first embodiment, and (b) is a specific circuit diagram of a level shift circuit for comparison. FIG. 3 is a specific circuit example diagram of a power supply circuit unit used in the first embodiment. FIG. 5 is a circuit configuration diagram of an entire second embodiment. It is a circuit block diagram of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solar cell 2 Booster circuit part 20 Pump-up circuit 21 Oscillation circuit 22 Level shift circuit 3 Secondary battery 4 Load circuit 5 Power supply circuit part 50 Regulator circuit 6 Control circuit part 60 Reference power supply circuit 61 Reference current circuit VR1-VR3 Reference voltage NOR1 NOR gate AND1 AND gate SWA, SWB Switch element D Diode C1 Pump capacitance element

Claims (11)

A power generation element, a booster circuit unit that boosts a voltage obtained from the power generation element by a switching operation of the switch element, generates a constant voltage based on an output voltage from the booster circuit unit, and supplies the constant voltage to the load circuit And a power supply circuit having an oscillation circuit for turning on and off the switch element in the boost circuit unit,
A control circuit unit that detects a power generation amount of the power generation element and controls power supply to the oscillation circuit based on the power generation amount;
The booster circuit unit is provided with an output unit that outputs a second output voltage lower than the first output voltage output to the power supply circuit unit,
The control circuit unit supplies the second output voltage as a power source for the oscillation circuit when the second output voltage is equal to or higher than a predetermined value, and at least when the second output voltage is lower than the predetermined value. As long as the power generation amount of the power generation element is not less than a predetermined amount, the first output voltage is controlled to be supplied as a power source of the oscillation circuit ,
The booster circuit unit boosts the voltage of the power generation element and outputs the second output voltage, and boosts the second output voltage output by the booster unit to boost the first output voltage. A power supply circuit characterized in that the power supply circuit is divided into a subsequent booster that outputs an output voltage . Power circuit according to claim 1, wherein the booster circuit unit, characterized in that it is constituted by a switched capacitor circuit. 3. The power supply circuit according to claim 2, wherein the booster circuit unit is formed of an ASIC, and the pump capacitor element of the previous booster unit is an external capacitor element outside the ASIC. 4. The power supply circuit according to claim 2, wherein the ASIC includes an external terminal externally provided with a pump capacitance element used in the subsequent boosting unit. 5. The power supply circuit according to claim 2, wherein among the switching elements of the boosting units at the front stage and the rear stage, switching elements for parallel connection of the pump capacitance elements are configured by NMOS transistors. The control circuit unit includes means for detecting the power generation amount of the power generation element, and when the power generation amount of the power generation element detected by the means is equal to or greater than a predetermined amount, power is supplied to the oscillation circuit, and the power generation amount 6. The power supply circuit according to claim 1, further comprising means for stopping power supply to the oscillation circuit when the value is less than the predetermined amount. The power supply circuit according to claim 6, wherein power supply to the oscillation circuit is stopped in a state where the pump capacitance element of the booster circuit unit is charged by the output of the power generation element. The on-time of the switch element for parallel connection is delayed from the off-time of the switch element for series connection of the pump capacitor elements of the booster circuit section, and the series connection is made more than the off-time of the switch element for parallel connection The boost circuit unit includes a delay circuit that generates a gate signal that delays the ON time of the switch element from the clock signal of the oscillation circuit,
The delay circuit includes a first resistor having one end connected to the power supply voltage, a second resistor having one end connected to the ground, and a series circuit of a PMOS transistor and an NMOS transistor each having a drain and a gate connected to each other. And the source of the PMOS transistor is connected to the other end of the first resistor, the source of the NMOS transistor is connected to the other end of the second resistor, and the clock signal generated by the oscillation circuit is 8. The power supply circuit according to claim 2, wherein a gate signal is obtained by inputting to the gates of the NMOS transistors and inputting outputs from the drains of both transistors to two sets of inverter elements having different threshold values. . The power supply circuit according to any one of claims 1 to 8, wherein a storage element is connected to an output of the power supply circuit unit so as to be in parallel with the load circuit. The power storage element is charged by the output of the power supply circuit unit when the power generation amount of the power generation element is equal to or greater than a predetermined amount, and the power is loaded when the power generation amount of the power generation element is equal to or less than the predetermined amount. The power supply circuit according to claim 9, wherein the power supply circuit is supplied to the circuit. When the constant voltage output of the power supply circuit unit is in a predetermined range including the output voltage of the power storage element, the constant voltage output is directly connected to the load circuit and the power storage element, and the output voltage of the power storage element is less than or equal to the predetermined range 11. The power supply circuit according to claim 9, further comprising output switching control means for connecting a constant voltage output to the load circuit and the power storage element via an output limiting resistor.

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