JP4388069B2 - コンフィギュレーション可能なロジック回路装置 - Google Patents
コンフィギュレーション可能なロジック回路装置 Download PDFInfo
- Publication number
- JP4388069B2 JP4388069B2 JP2006530116A JP2006530116A JP4388069B2 JP 4388069 B2 JP4388069 B2 JP 4388069B2 JP 2006530116 A JP2006530116 A JP 2006530116A JP 2006530116 A JP2006530116 A JP 2006530116A JP 4388069 B2 JP4388069 B2 JP 4388069B2
- Authority
- JP
- Japan
- Prior art keywords
- multiplexer
- circuit device
- logic circuit
- memory cell
- configurable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/04—Distributors combined with modulators or demodulators
Description
2 データバス
3 マルチプレクサ(ロジックブロック)
4 マルチプレクサ(ロジックブロック)
5 選択線
6 選択線
7 実行ブロック
8 マルチプレクサ
9 不揮発性メモリセル
10 不揮発性メモリセル
11 選択線
12 マルチプレクサ
13 マルチプレクサ
14 データバス
15 コンフィギュレーションバス
16 実行ブロック
Claims (7)
- 複数のデータ入力および1つまたは複数の制御信号入力を含むロジック信号切換のための少なくとも1つのマルチプレクサを有するコンフィギュレーション可能なロジック回路装置であって、少なくとも1つのマルチプレクサは、回路装置の1つまたは複数の外部の制御信号発生要素によって、制御信号入力に印加され得るコンフィギュレーション信号により回路動作中にランタイム可変にてコンフィギュレーション可能であり、かつデータ入力に印加され得るロジック信号を回路動作中にランタイム可変にて転送するようになったものにおいて、マルチプレクサ(8)の少なくとも1つの制御信号入力は不揮発性のメモリセル(10)と接続され、その際不揮発性のメモリセル(10)は一つの前記外部の制御信号発生要素の出力に接続され、それによって前記メモリセル(10)は回路動作中にランタイム可変にてのコンフィギュレーション可能であり、その際前記外部の制御信号発生要素は他のマルチプレクサの出力であることを特徴とするコンフィギュレーション可能なロジック回路装置。
- マルチプレクサ(8)の少なくとも1つのデータ入力が不揮発性のメモリセル(9)に接続されていることを特徴とする請求項2記載のコンフィギュレーション可能なロジック回路装置。
- 少なくとも1つのメモリセル(9,10)が、回路装置に由来する動的なランタイム可変の信号を介して可変であることを特徴とする請求項1又は2記載のコンフィギュレーション可能なロジック回路装置。
- 少なくとも1つのメモリセル(9,10)は、XMR技術またはFRAM(強誘電体RAM)技術の磁気抵抗メモリであることを特徴とする請求項2又は3記載のコンフィギュレーション可能なロジック回路装置。
- メモリセル(9,10)は、OUM(オボニックスユニファイドメモリ)技術またはFRAM(強誘電体RAM)技術のメモリであることを特徴とする請求項2又は3記載のコンフィギュレーション可能なロジック回路装置。
- 回路装置は、他のロジック回路装置に接続可能であるか、または接続されていることを特徴とする請求項1乃至5の1つに記載のコンフィギュレーション可能なロジック回路装置。
- 回路装置は、フィールドプログラマブルゲートアレイ(FPGA)またはコンプレックスプログラマブルロジックデバイス(CPLD)の一部であることを特徴とする請求項1乃至6の1つに記載のコンフィギュレーション可能なロジック回路装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10346679 | 2003-10-08 | ||
PCT/EP2004/011220 WO2005036750A1 (de) | 2003-10-08 | 2004-10-07 | Konfigurierbare logikschaltungsanordnung |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007508726A JP2007508726A (ja) | 2007-04-05 |
JP4388069B2 true JP4388069B2 (ja) | 2009-12-24 |
Family
ID=34428233
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006530116A Expired - Fee Related JP4388069B2 (ja) | 2003-10-08 | 2004-10-07 | コンフィギュレーション可能なロジック回路装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7355439B2 (ja) |
JP (1) | JP4388069B2 (ja) |
CN (1) | CN1864332B (ja) |
DE (1) | DE102004045527B4 (ja) |
WO (1) | WO2005036750A1 (ja) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004012531B4 (de) * | 2004-03-15 | 2006-12-28 | Siemens Ag | Rekonfigurierbare digitale Logikeinheit |
US20100138575A1 (en) | 2008-12-01 | 2010-06-03 | Micron Technology, Inc. | Devices, systems, and methods to synchronize simultaneous dma parallel processing of a single data stream by multiple devices |
US20100174887A1 (en) | 2009-01-07 | 2010-07-08 | Micron Technology Inc. | Buses for Pattern-Recognition Processors |
US8604593B2 (en) * | 2009-10-19 | 2013-12-10 | Mosaid Technologies Incorporated | Reconfiguring through silicon vias in stacked multi-die packages |
US9323994B2 (en) | 2009-12-15 | 2016-04-26 | Micron Technology, Inc. | Multi-level hierarchical routing matrices for pattern-recognition processors |
US9443156B2 (en) | 2011-12-15 | 2016-09-13 | Micron Technology, Inc. | Methods and systems for data analysis in a state machine |
US20130275709A1 (en) | 2012-04-12 | 2013-10-17 | Micron Technology, Inc. | Methods for reading data from a storage buffer including delaying activation of a column select |
US9524248B2 (en) | 2012-07-18 | 2016-12-20 | Micron Technology, Inc. | Memory management for a hierarchical memory system |
US9448965B2 (en) | 2013-03-15 | 2016-09-20 | Micron Technology, Inc. | Receiving data streams in parallel and providing a first portion of data to a first state machine engine and a second portion to a second state machine |
US9703574B2 (en) | 2013-03-15 | 2017-07-11 | Micron Technology, Inc. | Overflow detection and correction in state machine engines |
US11366675B2 (en) | 2014-12-30 | 2022-06-21 | Micron Technology, Inc. | Systems and devices for accessing a state machine |
US10430210B2 (en) | 2014-12-30 | 2019-10-01 | Micron Technology, Inc. | Systems and devices for accessing a state machine |
WO2016109571A1 (en) | 2014-12-30 | 2016-07-07 | Micron Technology, Inc | Devices for time division multiplexing of state machine engine signals |
US10691964B2 (en) | 2015-10-06 | 2020-06-23 | Micron Technology, Inc. | Methods and systems for event reporting |
US10977309B2 (en) | 2015-10-06 | 2021-04-13 | Micron Technology, Inc. | Methods and systems for creating networks |
US10846103B2 (en) | 2015-10-06 | 2020-11-24 | Micron Technology, Inc. | Methods and systems for representing processing resources |
US10146555B2 (en) | 2016-07-21 | 2018-12-04 | Micron Technology, Inc. | Adaptive routing to avoid non-repairable memory and logic defects on automata processor |
US10268602B2 (en) | 2016-09-29 | 2019-04-23 | Micron Technology, Inc. | System and method for individual addressing |
US10019311B2 (en) | 2016-09-29 | 2018-07-10 | Micron Technology, Inc. | Validation of a symbol response memory |
US10929764B2 (en) | 2016-10-20 | 2021-02-23 | Micron Technology, Inc. | Boolean satisfiability |
US10592450B2 (en) | 2016-10-20 | 2020-03-17 | Micron Technology, Inc. | Custom compute cores in integrated circuit devices |
DE102022124995A1 (de) * | 2022-09-28 | 2024-03-28 | Fujitsu Client Computing Limited | Schaltvorrichtung, Computersystem, und Verfahren |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5760602A (en) * | 1996-01-17 | 1998-06-02 | Hewlett-Packard Company | Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA |
US6097212A (en) | 1997-10-09 | 2000-08-01 | Lattice Semiconductor Corporation | Variable grain architecture for FPGA integrated circuits |
US6204686B1 (en) * | 1998-12-16 | 2001-03-20 | Vantis Corporation | Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources |
US6292019B1 (en) * | 1999-05-07 | 2001-09-18 | Xilinx Inc. | Programmable logic device having configurable logic blocks with user-accessible input multiplexers |
DE10249204A1 (de) | 2001-10-29 | 2003-05-28 | Siemens Ag | Rekonfigurierbare digitale Logikeinheit |
WO2003039001A1 (en) * | 2001-10-29 | 2003-05-08 | Leopard Logic, Inc. | Programmable interface for field programmable gate array cores |
EP1324495B1 (en) * | 2001-12-28 | 2011-03-30 | Fujitsu Semiconductor Limited | Programmable logic device with ferrroelectric configuration memories |
US6556042B1 (en) * | 2002-02-20 | 2003-04-29 | Xilinx, Inc. | FPGA with improved structure for implementing large multiplexers |
CN1295879C (zh) * | 2002-03-18 | 2007-01-17 | 皇家飞利浦电子股份有限公司 | 在可重构逻辑中宽多路复用器的实现 |
-
2004
- 2004-09-20 DE DE102004045527A patent/DE102004045527B4/de not_active Expired - Fee Related
- 2004-10-07 JP JP2006530116A patent/JP4388069B2/ja not_active Expired - Fee Related
- 2004-10-07 WO PCT/EP2004/011220 patent/WO2005036750A1/de active Application Filing
- 2004-10-07 CN CN200480028848XA patent/CN1864332B/zh not_active Expired - Fee Related
- 2004-10-07 US US10/571,790 patent/US7355439B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1864332B (zh) | 2010-06-23 |
JP2007508726A (ja) | 2007-04-05 |
CN1864332A (zh) | 2006-11-15 |
DE102004045527B4 (de) | 2009-12-03 |
WO2005036750A1 (de) | 2005-04-21 |
US20070024319A1 (en) | 2007-02-01 |
DE102004045527A1 (de) | 2005-05-19 |
US7355439B2 (en) | 2008-04-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4388069B2 (ja) | コンフィギュレーション可能なロジック回路装置 | |
US7477072B1 (en) | Circuit for and method of enabling partial reconfiguration of a device having programmable logic | |
US5414377A (en) | Logic block with look-up table for configuration and memory | |
US7176717B2 (en) | Programmable logic and routing blocks with dedicated lines | |
US7375549B1 (en) | Reconfiguration of programmable logic devices | |
US5760602A (en) | Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA | |
US6861870B1 (en) | Dynamic cross point switch with shadow memory architecture | |
US9722613B1 (en) | Circuit arrangement for and a method of enabling a partial reconfiguration of a circuit implemented in an integrated circuit device | |
JP4249745B2 (ja) | 集積回路上で揮発性と不揮発性プログラム可能ロジックを結合させるための技術 | |
US5737766A (en) | Programmable gate array configuration memory which allows sharing with user memory | |
US6288566B1 (en) | Configuration state memory for functional blocks on a reconfigurable chip | |
US7088134B1 (en) | Programmable logic device with flexible memory allocation and routing | |
US7463056B1 (en) | Writeable shift register lookup table in FPGA with SRAM memory cells in lookup table reprogrammed by writing after initial configuration | |
US20030214321A1 (en) | Architecture for programmable logic device | |
JPH07177008A (ja) | 改良されたプログラマブル論理セルアレイアーキテクチャ | |
JP2005512359A (ja) | 埋込み固定論理回路をサポートする相互接続ロジックを有するプログラマブルゲートアレイ | |
US7282949B2 (en) | FPGA powerup to known functional state | |
JPH06350436A (ja) | フィールドプログラマブルゲートアレイ | |
US7737723B1 (en) | Transparent field reconfiguration for programmable logic devices | |
US20050122132A1 (en) | Configuration memory implementation for lut-based reconfigurable logic architectures | |
KR100223623B1 (ko) | 비휘발성 기억셀용 테스트 회로 | |
US6879185B2 (en) | Low power clock distribution scheme | |
EP1143452A2 (en) | Memory circuitry for programmable logic integrated circuit devices | |
JP3707360B2 (ja) | 回路機能の再構成方法、及びプログラマブル論理回路装置 | |
US6680871B1 (en) | Method and apparatus for testing memory embedded in mask-programmable logic device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090121 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090512 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090803 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20090803 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090901 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091001 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121009 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131009 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |