JP4387265B2 - Method for manufacturing protruding electrode - Google Patents

Method for manufacturing protruding electrode Download PDF

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JP4387265B2
JP4387265B2 JP2004221463A JP2004221463A JP4387265B2 JP 4387265 B2 JP4387265 B2 JP 4387265B2 JP 2004221463 A JP2004221463 A JP 2004221463A JP 2004221463 A JP2004221463 A JP 2004221463A JP 4387265 B2 JP4387265 B2 JP 4387265B2
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core
solder
chamfered
protruding electrode
substrate
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JP2006041335A (en
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雅彦 古野
純一 小野崎
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Tamura Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1183Reworking, e.g. shaping
    • H01L2224/1184Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1356Disposition
    • H01L2224/13562On the entire exposed surface of the core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1357Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

本発明は、はんだ付け等による電子部品の実装のために半導体基板やプリント配線板の上に形成される突起電極製造方法に関する。本明細書では、半導体基板、プリント配線板、インターポーザ基板等を、単に「基板」という。また、突起電極の表面がはんだで被覆されたものも「突起電極」といい、この場合のはんだで被覆される部分を「コア」という。 The present invention relates to a method of manufacturing a protruding electrode formed on a semiconductor substrate or a printed wiring board for electronic component mounting by soldering or the like. In this specification, a semiconductor substrate, a printed wiring board, an interposer substrate, and the like are simply referred to as “substrate”. Further, the bump electrode whose surface is coated with solder is also called “protrusion electrode”, and the portion covered with solder in this case is called “core”.

突起電極を有する電子部品がFC(flip chip)やBGA(ball grid array)であり、FCやBGAはその突起電極を介して他の基板に実装される。これとは逆に、突起電極が設けられた基板上に、裸の電子部品を実装する技術もある。従来の一般的な突起電極の製造方法は、スクリーン印刷法やディスペンス法などを用いて基板の下部電極上にはんだペーストを塗布し、このはんだペーストを加熱してリフローする、というものである。これにより、半球状のはんだから成る突起電極が得られる。   An electronic component having a protruding electrode is an FC (flip chip) or BGA (ball grid array), and the FC or BGA is mounted on another substrate via the protruding electrode. On the other hand, there is a technique for mounting a bare electronic component on a substrate provided with a protruding electrode. A conventional general method for manufacturing a protruding electrode is to apply a solder paste on a lower electrode of a substrate by using a screen printing method, a dispensing method, or the like, and heat and reflow the solder paste. Thereby, a protruding electrode made of hemispherical solder is obtained.

次に、本発明の前提となる従来の突起電極について説明する(例えば特許文献1参照)。図4[1]は、この種の突起電極を示す断面図である。以下、この図面に基づき説明する。   Next, a conventional protruding electrode which is a premise of the present invention will be described (for example, see Patent Document 1). FIG. 4 [1] is a cross-sectional view showing this type of protruding electrode. Hereinafter, description will be given based on this drawing.

突起電極80は、基板81上に設けられたコア82と、コア82の表面90に設けられた球状のはんだ層83とから成る。コア82の表面90は、基板81に接する側面91と、側面91の上方に位置する上面92と、上面92と側面91との境界に位置する角部93とに分かれている。コア82は、基板81上の図示しない下部電極上に、銅メッキ等より形成されている。はんだ層83は、例えばコア82上にはんだペーストを塗布し、これをリフローすることにより形成されている。   The protruding electrode 80 includes a core 82 provided on the substrate 81 and a spherical solder layer 83 provided on the surface 90 of the core 82. The surface 90 of the core 82 is divided into a side surface 91 in contact with the substrate 81, an upper surface 92 positioned above the side surface 91, and a corner 93 positioned at the boundary between the upper surface 92 and the side surface 91. The core 82 is formed on a lower electrode (not shown) on the substrate 81 by copper plating or the like. The solder layer 83 is formed, for example, by applying a solder paste on the core 82 and reflowing it.

突起電極80によれば、はんだリフロー時に溶融しないコア82の表面90にはんだ層83を有するので、全体がはんだから成る突起電極に比べて、はんだリフローによって形が崩れにくい、突起電極80の高さを高くできる等の利点がある。   According to the bump electrode 80, the solder layer 83 is provided on the surface 90 of the core 82 that does not melt during solder reflow. Therefore, the height of the bump electrode 80 is less likely to be deformed by solder reflow than the bump electrode made entirely of solder. There is an advantage that can be increased.

特開平10−70127(図3)Japanese Patent Laid-Open No. 10-70127 (FIG. 3)

しかしながら、従来の突起電極80では次のような問題があった。   However, the conventional protruding electrode 80 has the following problems.

図4[2]に示すように、コア82の角部93を境に、はんだ層83が側面91と上面92とで分かれてしまうことがあった。その結果、特に上面92側のはんだ量が少ないと、実装後にはんだ付け不良を起こすことがあった。この現象は、はんだ層83全体のはんだ量が少ないほど顕著になる。一方、これを防ぐためにはんだ層83全体のはんだ量を単純に増やそうとすると、隣接する突起電極80同士の短絡を招くので、ファインピッチへの対応が困難になる。   As shown in FIG. 4 [2], the solder layer 83 may be divided into the side surface 91 and the upper surface 92 with the corner portion 93 of the core 82 as a boundary. As a result, particularly when the amount of solder on the upper surface 92 side is small, poor soldering may occur after mounting. This phenomenon becomes more prominent as the amount of solder in the entire solder layer 83 is smaller. On the other hand, if an attempt is made to simply increase the amount of solder in the entire solder layer 83 in order to prevent this, a short circuit occurs between adjacent protruding electrodes 80, making it difficult to cope with fine pitch.

そこで、本発明の目的は、はんだ濡れ性を改善した突起電極製造方法を提供することにある。 An object of the present invention is to provide a manufacturing method of the bump electrode with improved solder wettability.

角部93を境にはんだ層83が側面91と上面92とで分かれてしまうのは、角部93のはんだ濡れ性が悪いためと考えられる。図5は、固体金属表面のはんだ濡れを示す説明図である。以下、図4及び図5に基づき、コア82の角部93について、はんだ濡れ性が悪い理由について説明する。   The reason why the solder layer 83 is divided between the side surface 91 and the upper surface 92 at the corner 93 is considered to be because the solder wettability of the corner 93 is poor. FIG. 5 is an explanatory diagram showing solder wetting on the surface of a solid metal. Hereinafter, the reason why the solder wettability is poor in the corner portion 93 of the core 82 will be described with reference to FIGS. 4 and 5.

図5[1]は、平らな固体金属100の表面のはんだ濡れを示し、はんだ付けの一般的な説明に用いられるものである。はんだは、加熱されて溶融し、溶融はんだ101となっている。溶融はんだ101は、液体フラックス102の作用によって、固体金属100上に濡れ広がっている。このとき、溶融はんだ101の濡れは三つの力A,B,Cの作用によって作られることがわかる。つまり、三つの力A,B,Cが平衡状態になったとき、溶融はんだ101が一定の広がりを示す。Aは、液体の曲面に接する方向に作用するものであり、液体の表面張力、すなわち溶融はんだ101の表面積を最小にしようとする力である。Bは、固体金属100と液体フラックス102との界面に作用する力である。Cは、溶融はんだ101と固体金属100との間の界面張力を表す。CとBは固体金属100表面に沿って互いに相反する方向に働き、AとCはそれぞれの金属に特有のものである。一般に固体と液体の濡れの良否は、次のヤングの関係式によって表される。   FIG. 5 [1] shows the solder wetting of the surface of the flat solid metal 100 and is used for general explanation of soldering. The solder is heated and melted to form a molten solder 101. The molten solder 101 spreads on the solid metal 100 by the action of the liquid flux 102. At this time, it can be seen that the molten solder 101 is wetted by the action of three forces A, B, and C. That is, when the three forces A, B, and C are in an equilibrium state, the molten solder 101 exhibits a certain spread. A acts in a direction in contact with the curved surface of the liquid, and is a force for minimizing the surface tension of the liquid, that is, the surface area of the molten solder 101. B is a force acting on the interface between the solid metal 100 and the liquid flux 102. C represents the interfacial tension between the molten solder 101 and the solid metal 100. C and B work in directions opposite to each other along the surface of the solid metal 100, and A and C are specific to each metal. In general, the quality of wetting between a solid and a liquid is expressed by the following Young's relational expression.

B=C+Acosθ ・・・(1)
∴cosθ=(B−C)/A ・・・(2)
この式(1)において、θは、溶融はんだ101の接触角であり、小さいほどはんだ濡れ性が良い。
B = C + A cos θ (1)
∴cos θ = (BC) / A (2)
In this formula (1), θ is the contact angle of the molten solder 101, and the smaller the value, the better the solder wettability.

一方、図5[2]は、固体金属100の表面が原点Oにおいて平面から角度φだけ折れ曲がっている場合の、原点Oでのはんだ濡れを示す。この場合、原点Oが図4の角部93に相当する。また、力A,B,Cの大きさは図5[1]のときと同じであるとする。このとき、溶融はんだ101の接触角をθ’とすると、ヤングの関係式によって次式が成り立つ。   On the other hand, FIG. 5 [2] shows solder wetting at the origin O when the surface of the solid metal 100 is bent at an angle φ from the plane at the origin O. In this case, the origin O corresponds to the corner 93 of FIG. Further, it is assumed that the magnitudes of the forces A, B, and C are the same as those in FIG. At this time, when the contact angle of the molten solder 101 is θ ′, the following equation is established by Young's relational expression.

Bcosφ=C+Acosθ’ ・・・(3)
∴cosθ’=(Bcosφ−C)/A ・・・(4)
ここで、0<cosφ<1であるから、式(2)と式(4)とを比較して、
θ’>θ ・・・(5)
が得られる。
Bcosφ = C + Acosθ ′ (3)
∴cos θ ′ = (B cos φ−C) / A (4)
Here, since 0 <cosφ <1, comparing the equations (2) and (4),
θ ′> θ (5)
Is obtained.

つまり、平面からの角度φが大きいほど、接触角θ’が大きくなる、すなわちはんだ濡れ性が悪くなる。図4の角部93は、角度φが90°に近いので、はんだ濡れ性が非常に悪いのである。その結果、図4[2]に示すように、側面91の溶融はんだが角部93を乗り越えられないため、上面92のはんだ量が少なくなってしまうのである。   That is, as the angle φ from the plane is larger, the contact angle θ ′ is larger, that is, the solder wettability is worsened. The corner portion 93 in FIG. 4 has very poor solder wettability because the angle φ is close to 90 °. As a result, as shown in FIG. 4 [2], since the molten solder on the side surface 91 cannot get over the corner portion 93, the amount of solder on the upper surface 92 is reduced.

本発明は、この知見に基づき、コアの角部のはんだ濡れ性を改善するためになされたものである。以下、本発明に係る製造方法によって製造された突起電極を、単に「本発明に係る突起電極」という。すなわち、本発明に係る突起電極は、基板上に設けられたコアと、このコアの表面を覆うはんだ層とから成り、全体として半球状を呈するものである。そして、コアの表面は、基板に接する側面と、側面の基板に接しない側に位置する上面と、上面と側面との境界に位置する面取り面とを備えている。本発明では、従来のコアの角部を面取り面に加工しているので、すなわち図5[2]で言えば角度φを小さくしているので、形状に起因するはんだ濡れ性が改善される。なお、角部とは面と面との交線のことである。 The present invention has been made to improve the solder wettability at the corners of the core based on this finding. Hereinafter, the protruding electrode manufactured by the manufacturing method according to the present invention is simply referred to as “the protruding electrode according to the present invention”. That is, the protruding electrode according to the present invention is composed of a core provided on the substrate and a solder layer covering the surface of the core, and has a hemispherical shape as a whole. The surface of the core includes a side surface in contact with the substrate, an upper surface located on the side not contacting the substrate, and a chamfered surface located at the boundary between the upper surface and the side surface. In the present invention, since the corner portion of the conventional core is processed into a chamfered surface, that is, the angle φ is reduced in FIG. 5 [2], the solder wettability due to the shape is improved. In addition, a corner | angular part is an intersection line of a surface.

このとき、面取り面は凸状の曲面とすることが好ましい。その理由を図6に基づき説明する。図6では、固体金属100の表面を円筒面とし、その円筒面の曲率(曲率半径の逆数)を様々な値にしている。ここで、前述のヤングの関係式は、接線方向の力で構成されるので、曲率に関係なく成り立つと考えられる。そのため、どのような曲率の固体金属100に対しても、溶融はんだ101の接触角θは一定になる。つまり、面取り面を凸状の曲面とすることは、図5[2]で言えば角度φを零にすることに等しい。なお、「凸状の曲面」とは、曲率が一定の曲面に限定するものではなく、曲率が連続的に変化する滑らかな曲面も含まれる。   At this time, the chamfered surface is preferably a convex curved surface. The reason will be described with reference to FIG. In FIG. 6, the surface of the solid metal 100 is a cylindrical surface, and the curvature of the cylindrical surface (reciprocal of the radius of curvature) is set to various values. Here, the above-mentioned Young's relational expression is constituted by a tangential force, and therefore is considered to hold regardless of the curvature. Therefore, the contact angle θ of the molten solder 101 is constant with respect to the solid metal 100 having any curvature. That is, making the chamfered surface a convex curved surface is equivalent to setting the angle φ to zero in FIG. 5 [2]. The “convex curved surface” is not limited to a curved surface having a constant curvature, but also includes a smooth curved surface in which the curvature continuously changes.

面取り面は平面としてもよい。このとき、上面と面取り面との境界部分及び面取り面と側面との境界部分は、前述した理由により、それぞれ凸状の曲面とすることが好ましい。   The chamfered surface may be a flat surface. At this time, it is preferable that the boundary portion between the upper surface and the chamfered surface and the boundary portion between the chamfered surface and the side surface are respectively convex curved surfaces for the reasons described above.

上面と面取り面とは互いに一体化された一体面としてもよい。このときも、一体面は凸状の曲面とすることが好ましい。   The upper surface and the chamfered surface may be integrated with each other. Also at this time, the integral surface is preferably a convex curved surface.

突起電極は、銅、銀、金及びニッケルのいずれか一つから成り、その表面に錫メッキ、金メッキ、ニッケル−金メッキ及びはんだメッキのいずれか一つの処理が施された、としてもよい。突起電極の材料の具体例を挙げたものである。   The protruding electrode may be made of any one of copper, silver, gold, and nickel, and the surface thereof may be subjected to any one of tin plating, gold plating, nickel-gold plating, and solder plating. Specific examples of the material of the protruding electrode are given.

また、本発明に係る突起電極は、表面がはんだによって被覆される、としてもよい。このはんだは、例えば、錫、インジウム、銀、銅、亜鉛、ビスマス、アンチモン、ゲルマニウム、アルミニウム、ニッケル、鉛及び金の中から選ばれた少なくとも一つの元素を含む合金である。   Further, the protruding electrode according to the present invention may have a surface covered with solder. This solder is, for example, an alloy containing at least one element selected from tin, indium, silver, copper, zinc, bismuth, antimony, germanium, aluminum, nickel, lead, and gold.

また、本発明に係る製造方法は、本発明に係る突起電極を製造する方法であって、コア形成工程、面取り面形成工程及びはんだ層形成工程を備えている。そして、コア形成工程では、基板上にコアを形成する。面取り面形成工程では、コア形成工程で形成されたコアに面取り面を形成する。はんだ層形成工程は、面取り面形成工程で面取り面が形成されたコアの表面にはんだ層を形成する。 The manufacturing method according to the present invention is a method for manufacturing the protruding electrode according to the present invention, and includes a core forming step, a chamfered surface forming step, and a solder layer forming step. In the core formation step, a core is formed on the substrate. In the chamfered surface forming step, a chamfered surface is formed on the core formed in the core forming step. In the solder layer forming step, a solder layer is formed on the surface of the core on which the chamfered surface is formed in the chamfered surface forming step.

また、面取り面形成工程では、コアにバフ研磨又はバレル研磨を施すことによって面取り面を形成する。 In the chamfered surface forming step, the chamfered surface is formed by buffing or barrel polishing the core .

本発明に係る突起電極製造方法によれば、コアの角部を面取り面に加工することにより、コアの表面にはんだ層を形成するときのはんだ濡れ性を改善できる。したがって、はんだ層がコアの側面と上面とに分かれてしまうことを防止できるので、実装時のはんだ付けの歩留り及び実装後のはんだ付けの信頼性を向上できる。 According to the manufacturing method of the bump electrode according to the present invention, by processing a corner portion of the core to the chamfered surface, it can improve the solder wettability when forming the solder layer on the surface of the core. Therefore, it is possible to prevent the solder layer from being divided into the side surface and the top surface of the core, so that the yield of soldering during mounting and the reliability of soldering after mounting can be improved.

換言すると、コアの側面の溶融はんだが面取り面に沿ってコアの上面に濡れ広がるため、はんだ層が上面と側面との境界部分で途切れるような不具合を生じることが無く、必要最小限のはんだ量で信頼性の高いはんだ接合が得られるとともに、ファインピッチへの対応も可能となる。   In other words, the molten solder on the side surface of the core wets and spreads on the top surface of the core along the chamfered surface, so that the solder layer does not break at the boundary between the top surface and the side surface, and the minimum amount of solder required This makes it possible to obtain highly reliable solder joints and to handle fine pitches.

図1[1]は、本発明に係る突起電極の第一実施形態を示す断面図である。以下、この図面に基づき説明する。   FIG. 1 [1] is a cross-sectional view showing a first embodiment of the bump electrode according to the present invention. Hereinafter, description will be given based on this drawing.

本実施形態の突起電極10は、基板11上に設けられたコア12と、コア12の表面20に設けられたはんだ層13とから成る。そして、コア12の表面20は、基板11に接する側面21と、側面21の基板11に接しない側(すなわち上方)に位置する上面22と、上面22と側面21との境界に位置する面取り面23とを備えている。   The protruding electrode 10 of this embodiment includes a core 12 provided on the substrate 11 and a solder layer 13 provided on the surface 20 of the core 12. The surface 12 of the core 12 includes a side surface 21 that contacts the substrate 11, a top surface 22 that is positioned on the side of the side surface 21 that does not contact the substrate 11 (that is, the upper side), and a chamfered surface that is positioned at the boundary between the top surface 22 and the side surface 21. 23.

基板11は、半導体基板、プリント配線板、インターポーザ基板等であり、表面に図示しない下部電極を有し、その下部電極上にコア12が形成される。コア12は、良好な導電性を有するとともにはんだ層13よりも高融点の金属、例えば銅、銀、金、ニッケル等から成る。コア12の形状は、円柱状や角柱状である。はんだ層13は、例えばSn−Pb(融点183℃)、Sn−Ag−Cu(融点218℃)、Sn−Ag(融点221℃)、Sn−Cu(融点227℃)等から成る。面取り面23は、後述するようにバフ研磨、バレル研磨等によって、凸状の曲面に仕上げられている。 The substrate 11 is a semiconductor substrate, a printed wiring board, an interposer substrate, or the like, has a lower electrode (not shown) on the surface, and a core 12 is formed on the lower electrode. The core 12 is made of a metal having good conductivity and a melting point higher than that of the solder layer 13, such as copper, silver, gold, or nickel. The shape of the core 12 is cylindrical or prismatic. The solder layer 13 is made of, for example, Sn—Pb (melting point 183 ° C.), Sn—Ag—Cu (melting point 218 ° C.), Sn—Ag (melting point 221 ° C.), Sn—Cu (melting point 227 ° C.), or the like. Chamfered surface 23 is buffed as described later, by barrels polishing or the like, is finished to a convex curved surface.

突起電極10によれば、従来のコアの角部を面取り面23に加工しているので、形状に起因するはんだ濡れ性を改善できる。したがって、側面21の溶融はんだが面取り面23を簡単に乗り越えて上面22へ広がるため、上面22のはんだ量が十分に確保される。   According to the protruding electrode 10, since the corner portion of the conventional core is processed into the chamfered surface 23, the solder wettability resulting from the shape can be improved. Therefore, the molten solder on the side surface 21 easily gets over the chamfered surface 23 and spreads to the upper surface 22, so that a sufficient amount of solder is secured on the upper surface 22.

図1[2]は、本発明に係る突起電極の第二実施形態を示す断面図である。以下、この図面に基づき説明する。ただし、図1[1]と同じ部分は同じ符号を付すことにより説明を省略する。   FIG. 1 [2] is sectional drawing which shows 2nd embodiment of the protruding electrode which concerns on this invention. Hereinafter, description will be given based on this drawing. However, the same parts as those in FIG.

本実施形態の突起電極30では、面取り面31が平面になっている。そして、面取り面31と側面21との境界部分及び面取り面31と上面22との境界部分には、それぞれ角部32,33が形成されている。しかし、角部32,33は、従来のコアの角部に比べて角度が緩やかであることから、はんだ濡れ性が改善されている。このような形状は、例えば研磨条件を適宜設定することによって実現される。   In the protruding electrode 30 of this embodiment, the chamfered surface 31 is a flat surface. Corner portions 32 and 33 are formed at the boundary portion between the chamfered surface 31 and the side surface 21 and at the boundary portion between the chamfered surface 31 and the upper surface 22, respectively. However, since the corners 32 and 33 are gentler than the corners of the conventional core, the solder wettability is improved. Such a shape is realized, for example, by appropriately setting polishing conditions.

図1[3]は、本発明に係る突起電極の第三実施形態を示す部分拡大断面図である。以下、この図面に基づき説明する。ただし、図1[2]と同じ部分は同じ符号を付すことにより説明を省略する。   FIG. 1 [3] is a partially enlarged cross-sectional view showing a third embodiment of the protruding electrode according to the present invention. Hereinafter, description will be given based on this drawing. However, the same parts as those in FIG.

本実施形態では、面取り面34が平面部35及び曲面部36,37によって構成されている。曲面部36は側面21と平面部35との境界部分に位置し、曲面部37は上面22と平面部35との境界部分に位置する。曲面部36,37は、凸状の曲面である。曲面部36,37によって平面部36と側面21及び上面22とが角部を生ずることなく緩やかに接続しているので、はんだ濡れ性が改善されている。このような形状は、例えば研磨条件を適宜設定することによって実現される。   In the present embodiment, the chamfered surface 34 is constituted by a flat surface portion 35 and curved surface portions 36 and 37. The curved surface portion 36 is located at the boundary portion between the side surface 21 and the flat surface portion 35, and the curved surface portion 37 is located at the boundary portion between the upper surface 22 and the flat surface portion 35. The curved surface portions 36 and 37 are convex curved surfaces. Since the flat surface portion 36 and the side surface 21 and the upper surface 22 are gently connected by the curved surface portions 36 and 37 without generating corner portions, the solder wettability is improved. Such a shape is realized, for example, by appropriately setting polishing conditions.

図2は、本発明に係る突起電極の第四実施形態及びその製造方法を示す断面図であり、図2[1]〜図2[3]の順に工程が進行する。以下、この図面に基づき説明する。ただし、図1と同じ部分は同じ符号を付すことにより説明を省略する。   FIG. 2 is a cross-sectional view showing a fourth embodiment of the bump electrode according to the present invention and a method for manufacturing the same, and the steps proceed in the order of FIG. 2 [1] to FIG. 2 [3]. Hereinafter, description will be given based on this drawing. However, the same parts as those in FIG.

まず、図2[1]に示すように、基板11上にコア12を形成する。コア12の側面21と上面22との境界部分には、角部24が生じている。コア12の形成工程は、例えばフォトリソグラフィ技術と銅メッキ技術とを用いるが、従来と同じであるので詳しい説明は省略する。   First, as shown in FIG. 2 [1], the core 12 is formed on the substrate 11. A corner 24 is formed at the boundary between the side surface 21 and the upper surface 22 of the core 12. For example, a photolithography technique and a copper plating technique are used for the formation process of the core 12, but since it is the same as the conventional technique, detailed description thereof is omitted.

続いて、図2[2]に示すように、コア12の角部24を除去して面取り面を形成し、その面取り面と上面22とを一体化した一体面41を形成する。このとき、後述するように、コア12に例えばバフ研磨、バレル研磨等を施して、一体面41を形成する。一体面41は、凸状の曲面になっている。このような形状は、例えば研磨条件を適宜設定することによって実現される。 Subsequently, as shown in FIG. 2 [2], the corner portion 24 of the core 12 is removed to form a chamfered surface, and an integrated surface 41 in which the chamfered surface and the upper surface 22 are integrated is formed. At this time, as described later, for example, buffing the core 12, is subjected to barrels polishing or the like, to form an integral surface 41. The integral surface 41 is a convex curved surface. Such a shape is realized, for example, by appropriately setting polishing conditions.

最後に、一体面41が形成されたコア12の表面20に、はんだ層13を形成する。はんだ層13の形成工程は、例えばはんだペーストの塗布及びリフロー、溶融はんだ槽への浸漬等を用いるが、従来と同じであるので詳しい説明は省略する。   Finally, the solder layer 13 is formed on the surface 20 of the core 12 on which the integrated surface 41 is formed. The solder layer 13 is formed by using, for example, solder paste application and reflow, dipping in a molten solder bath, and the like, but since it is the same as in the past, detailed description thereof is omitted.

本実施形態の突起電極40によれば、コア12に面取り加工を施して、面取り面と上面22とを一体化させた一体面41を形成することにより、一体面41と側面21とが角部を生ずることなく緩やかに接続しているので、はんだ濡れ性が改善される。   According to the protruding electrode 40 of the present embodiment, the core 12 is chamfered to form the integrated surface 41 in which the chamfered surface and the upper surface 22 are integrated. Since the connection is made gently without generating solder, the solder wettability is improved.

図3は図2[2]の面取り面形成工程の具体例を示す断面図であり、図3[1]はバフ研磨、図3[2]は電解研磨(参考形態)、図3[3]はバレル研磨である。以下、この図面に基づき説明する。ただし、図2と同じ部分は同じ符号を付すことにより説明を省略する。 3 is a cross-sectional view showing a specific example of the chamfered surface forming step of FIG. 2 [2], FIG. 3 [1] is buff polishing, FIG. 3 [2] is electrolytic polishing (reference form) , and FIG. 3 [3]. Is barrel polishing. Hereinafter, description will be given based on this drawing. However, the same parts as those in FIG.

図3[1]に示すバフ研磨について説明する。バフ40は、例えば綿布やサイザル麻布を基材としたものであり、回転台41上に固定されている。バフ40上にはスラリー状の研磨剤42が載置されている。そして、研磨剤42上にコア12を基板11ごと押し付けて、バフ40を高速で回転させる。このとき、コア12の角部24は、上面22と側面21との二面から研磨されることにより、上面22及び側面21よりも研磨速度が大きいので、図1及び図2に示すような面取り面の形状を得やすい。なお、角部24の研磨速度が上面22及び側面21と同じか又は小さいと、角部24を除去できない。また、バフ40の回転とは逆方向に、基板11側も回転させてもよい。   The buffing shown in FIG. 3 [1] will be described. The buff 40 is made of, for example, cotton cloth or sisal linen and is fixed on the turntable 41. A slurry-like abrasive 42 is placed on the buff 40. Then, the core 12 is pressed together with the substrate 11 onto the abrasive 42, and the buff 40 is rotated at a high speed. At this time, since the corner portion 24 of the core 12 is polished from two surfaces of the upper surface 22 and the side surface 21, the polishing rate is higher than that of the upper surface 22 and the side surface 21, so that the chamfer as shown in FIGS. Easy to obtain surface shape. If the polishing rate of the corner 24 is the same as or smaller than that of the upper surface 22 and the side surface 21, the corner 24 cannot be removed. Further, the substrate 11 side may also be rotated in the direction opposite to the rotation of the buff 40.

ここで参考形態として、図3[2]に示す電解研磨について説明する。前処理として、全てのコア12が同電位になるように、基板11全面に例えばスパッタリングによって銅から成るメッキ電極50を形成しておく。そして、メッキ電極50陽極とし、鉛又はステンレス鋼から成る電極板51を陰極とし、これらを電解液52中に浸漬する。ここで、メッキ電極50と電極板51とに直流電源53(又は交流電源を併用)から電圧を印加する。このとき、コア12の角部24は、上面22や側面21よりも先鋭になっていることにより、上面22及び側面21よりも電界が集中する。つまり、角部24は上面22及び側面21よりも研磨速度が大きいので、図1及び図2に示すような面取り面の形状を得やすい。 Here, the electropolishing shown in FIG. 3 [2] will be described as a reference form . As a pretreatment, a plating electrode 50 made of copper, for example, is formed on the entire surface of the substrate 11 so that all the cores 12 have the same potential. Then, the plating electrode 50 is used as the anode, the electrode plate 51 made of lead or stainless steel is used as the cathode, and these are immersed in the electrolytic solution 52. Here, a voltage is applied to the plating electrode 50 and the electrode plate 51 from a DC power supply 53 (or an AC power supply in combination). At this time, the corner portion 24 of the core 12 is sharper than the upper surface 22 and the side surface 21, so that the electric field is concentrated on the upper surface 22 and the side surface 21. That is, since the corner portion 24 has a higher polishing rate than the upper surface 22 and the side surface 21, it is easy to obtain a chamfered surface shape as shown in FIGS.

図3[3]に示すバレル研磨について説明する。図示しないバレル(barrel:樽)内に、コア12が形成された基板11とともに、メディア60、水61及びコンパウンド(図示せず)を入れる。メディア60は、球状の固形砥粒を用いている。ここで、バレルを回転させると、メディア60がコア12に衝突することにより、コア12が研磨される。このとき、コア12の角部24は、上面22や側面21よりも水61中に突き出していることにより、上面22及び側面21よりもメディア60が衝突しやすい。つまり、角部24は上面22及び側面21よりも研磨速度が大きいので、図1及び図2に示すような面取り面の形状を得やすい。ここでは、バレルを回転させる回転バレル研磨を説明したが、バレルを振動させる振動バレル研磨や、磁性体メディアと交番磁界とを用いる電磁バレル研磨等を用いてもよい。   The barrel polishing shown in FIG. 3 [3] will be described. A medium 60, water 61 and a compound (not shown) are put together with the substrate 11 on which the core 12 is formed in a barrel (not shown). The media 60 uses spherical solid abrasive grains. Here, when the barrel is rotated, the core 12 is polished by the medium 60 colliding with the core 12. At this time, the corner portion 24 of the core 12 protrudes into the water 61 rather than the upper surface 22 and the side surface 21, so that the media 60 is more likely to collide with the upper surface 22 and the side surface 21. That is, since the corner portion 24 has a higher polishing rate than the upper surface 22 and the side surface 21, it is easy to obtain the shape of the chamfered surface as shown in FIGS. Here, rotational barrel polishing for rotating the barrel has been described, but vibration barrel polishing for vibrating the barrel, electromagnetic barrel polishing using a magnetic medium and an alternating magnetic field, or the like may be used.

なお、上記実施形態は、言うまでもなく、本発明を限定するものではない。例えば、はんだ層は、前述したはんだの具体例から成るものとしても良い。   Needless to say, the above embodiment does not limit the present invention. For example, the solder layer may be made of the specific example of solder described above.

本発明に係る突起電極の実施形態を示し、図1[1]は第一実施形態を示す断面図、図1[2]は第二実施形態を示す断面図、図1[3]は第三実施形態を示す部分拡大断面図である。FIG. 1 [1] is a sectional view showing a first embodiment, FIG. 1 [2] is a sectional view showing a second embodiment, and FIG. 1 [3] is a third embodiment. It is a partial expanded sectional view showing an embodiment. 本発明に係る突起電極の第四実施形態及びその製造方法を示す断面図であり、図2[1]〜図2[3]の順に工程が進行する。It is sectional drawing which shows 4th embodiment of the bump electrode which concerns on this invention, and its manufacturing method, and a process progresses in order of FIG. 2 [1]-FIG. 2 [3]. 図2[2]の面取り面形成工程の具体例を示す断面図であり、図3[1]はバフ研磨、図3[2]は電解研磨(参考形態)、図3[3]はバレル研磨である。FIG. 3 is a cross-sectional view showing a specific example of the chamfered surface forming step of FIG. 2 [2], FIG. 3 [1] is buff polishing, FIG. 3 [2] is electrolytic polishing (reference form) , and FIG. 3 [3] is barrel polishing. It is. 従来の突起電極を示す断面図であり、図4[1]は理想的な状態であり、図4[2]は問題のある状態である。It is sectional drawing which shows the conventional protruding electrode, FIG. 4 [1] is an ideal state, and FIG. 4 [2] is a problematic state. 固体金属表面のはんだ濡れを示す説明図であり、図5[1]は固体金属表面が平らな場合であり、図5[2]は固体金属表面が曲がっている場合である。It is explanatory drawing which shows the solder wetting of the solid metal surface, FIG. 5 [1] is a case where the solid metal surface is flat, and FIG. 5 [2] is a case where the solid metal surface is bent. 様々な曲率の固体金属表面のはんだ濡れを示す説明図である。It is explanatory drawing which shows the solder wetting of the solid metal surface of various curvature.

10,30,40 突起電極
11 基板
12 コア
13 はんだ層
20 コアの表面
21 側面
22 上面
23,31,34 面取り面
41 一体面
10, 30, 40 Projected electrode 11 Substrate 12 Core 13 Solder layer 20 Core surface 21 Side surface 22 Upper surface 23, 31, 34 Chamfered surface 41 Integrated surface

Claims (2)

基板上に上面及び側面からなるコアを形成するコア形成工程と、
前記コアにバフ研磨を施すことによって前記上面と前記側面との境界に面取り面を形成する面取り面形成工程と、
前記側面、前記上面及び前記面取り面の全てをはんだ層で覆って全体として半球状に形成するはんだ層形成工程と、
を備えたことを特徴とする突起電極の製造方法。
A core forming step of forming a core composed of an upper surface and side surfaces on the substrate;
A chamfered surface forming step of forming a chamfered surface at a boundary between the upper surface and the side surface by buffing the core;
A solder layer forming step of covering all of the side surface, the upper surface and the chamfered surface with a solder layer to form a hemisphere as a whole;
A protruding electrode manufacturing method comprising:
基板上に上面及び側面からなるコアを形成するコア形成工程と、
前記コアにバレル研磨を施すことによって前記上面と前記側面との境界に面取り面を形成する面取り面形成工程と、
前記側面、前記上面及び前記面取り面の全てをはんだ層で覆って全体として半球状に形成するはんだ層形成工程と、
を備えたことを特徴とする突起電極の製造方法。
A core forming step of forming a core composed of an upper surface and side surfaces on the substrate;
A chamfered surface forming step of forming a chamfered surface at the boundary between the upper surface and the side surface by performing barrel polishing on the core;
A solder layer forming step of covering all of the side surface, the upper surface and the chamfered surface with a solder layer to form a hemisphere as a whole;
A protruding electrode manufacturing method comprising:
JP2004221463A 2004-07-29 2004-07-29 Method for manufacturing protruding electrode Expired - Lifetime JP4387265B2 (en)

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