JP4385479B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging apparatus that captures an optical image.
[0002]
[Prior art]
[Conventional Example 1] As a conventional technique, a technique for detecting a moving object edge based on a difference between frames of an image and generating a moving object image is known.
[0003]
[Conventional Example 2] In addition, in equations (8) to (13) of Japanese Patent Laid-Open No. 6-139361, a resettable integrator is provided at the current output destination of the light receiving element, and the output current polarity of the light receiving element is being read out. The operation of reversing is described. With such a configuration, it is possible to obtain a temporal change in pixel output as a current integrated value.
[0004]
[Problems to be solved by the invention]
By the way, the above-described conventional example 1 detects a moving object edge based on a difference between frames of an image. For this reason, when the moving object moves at a high speed, the position of the moving object between frames greatly deviates, making it difficult to detect the moving object edge. In addition, in the case of a moving object that moves extremely rapidly, the position of the moving object is completely separated between frame images. In such a state, it becomes very difficult to identify the shape and number of moving objects based on moving object edges.
[0005]
On the other hand, in Conventional Example 2 described above, the resettable integrator must accumulate the change in the output current of the light receiving element in real time. Therefore, the row-by-row exposure operation and the current output operation must be executed simultaneously. Therefore, the exposure time of the light receiving elements per row of pixels is substantially limited to the readout time per row (so-called horizontal scanning period). For this reason, the exposure time is extremely short compared with a normal image sensor, and there is a problem that it is not suitable for a dark scene.
[0006]
Further, in the conventional example 2, since the above-described operation is individually executed for each row, the detection timing of the time change does not overlap at all even in the adjacent row. For this reason, when the moving object moves at high speed, the moving object image is scattered in units of rows. Therefore, it is not suitable for use for identifying the shape of a moving object.
In view of the above-described problems, the present inventor has previously performed a pre-processing for detecting a temporal change in pixel output prior to a pixel output readout operation. It was considered preferable for generating a moving object image.
[0007]
  Therefore,One embodiment of the present inventionAccordingly, an object of the present invention is to provide an imaging device capable of executing a predetermined pre-process in advance for pixel output in parallel with a pixel output readout operation.
  further,In another embodiment, the one embodiment described aboveAn object of the present invention is to provide an imaging apparatus suitable for generating a moving body image of a high-speed moving body by applying the imaging apparatus.
  In another embodiment, the one embodiment described aboveAn object of the present invention is to provide an imaging apparatus that can capture images of a plurality of frames in one frame period.
  In another embodiment, the one embodiment described aboveAn object of the present invention is to provide an imaging apparatus capable of expanding the dynamic range of pixel output by applying the imaging apparatus.
  In another aspect, each of the above aspectsIt is an object of the present invention to provide an imaging apparatus capable of further increasing the degree of freedom of selection such as exposure time and photo opportunity.
[0008]
[Means for Solving the Problems]
  1st invention respond | corresponds to the light receiving element which accumulate | stores the signal charge according to incident light, the charge transfer MOS switch which transfers the said signal charge from the said light receiving element to a capacity | capacitance, and the signal charge accumulate | stored in the said capacity | capacitance An amplifying element that generates a signal voltage, a reset MOS switch that resets the signal charge of the capacitor, and a row selection MOS switch are arranged in a matrix, respectively, and the row selection MOS switch and each vertical column The row selection MOS switch, the charge transfer MOS switch, and the reset MOS arranged in a row direction, each of which is connected to a vertical read line that reads the signal voltage from the amplification element, and includes a shift register and a logic circuit An output circuit that outputs a control pulse to the switch and the vertical readout line are connected and output from the amplification element And a post-processing circuit that holds the signal voltage, and the output circuit controls switching between the ON state and the OFF state of the reset MOS switch and the charge transfer MOS switch in the same row in one frame period. Each of the pulses is output a plurality of times to set a plurality of exposure periods in one frame period, and the row selection MOS switch is turned on only once in the one frame period, and each of the plurality of exposure periods corresponding to the plurality of exposure periods is set. A signal voltage is output to the vertical readout line.
[0009]
In a second aspect based on the first aspect, the output circuit transfers the signal charge generated by the light receiving element during the first exposure period to the capacitor by turning on the charge transfer MOS switch. An operation of starting a second exposure period by the light receiving element, an operation of turning on the row selection MOS switch and outputting a signal voltage corresponding to a signal charge transferred to the capacitor to the vertical readout line, After resetting the capacitor with the reset MOS switch turned on, the signal charge generated by the light receiving element during the second exposure period is transferred to the capacitor with the charge transfer MOS switch turned on, A control pulse for outputting the signal voltage corresponding to the signal charge to the vertical readout line is output.
[0010]
  According to a third invention, in the first or second invention, the output circuit includes a transfer circuit that outputs a control pulse for each row to the row selection MOS switch arranged in the row direction, and a row direction. And a control circuit for outputting a control pulse for each row with respect to the arranged charge transfer MOS switch and the reset MOS switch.
[0011]
  In a fourth aspect based on the second aspect, the post-processing circuit generates a differential voltage between the signal voltage obtained in the first exposure period and the signal voltage obtained in the second exposure period. It is a difference signal generation circuit which performs.
[0012]
  In a fifth aspect based on the fourth aspect, the difference signal generation circuit includes a first MOS switch on the input side, a second MOS switch on the output side, a third MOS switch, a first capacitor, a second capacitor, The first MOS switch is connected to the vertical readout line, the first MOS switch, the first capacitor, and the second MOS switch are connected in series, and a midpoint between the first MOS switch and the first capacitor. Is connected to the ground via the second capacitor, and the midpoint of the first capacitor and the second MOS switch is connected to the ground via the third MOS switch.
[0013]
  In a sixth aspect based on the second aspect, the post-processing circuit calculates a differential voltage between a signal voltage corresponding to the signal charge generated in the first exposure period and a dark signal output after the reset. Holding the differential voltage between the dark signal output after the reset and the signal voltage corresponding to the signal charge generated in the second exposure period, and outputting the differential voltage selectively or in parallel It is a distribution circuit which performs.
[0014]
  According to a seventh invention, in the sixth invention, the distribution circuit includes a first system circuit, a second system circuit, and a selection switch for selecting the first system and the second system, The one-system circuit has a first MOS switch on the input side, a second MOS switch on the output side, a third MOS switch, a first capacitor, and a second capacitor, and the first MOS switch includes the first MOS switch, Connected to a vertical readout line, the first MOS switch, the first capacitor, and the second MOS switch are connected in series, and a midpoint between the first MOS switch and the first capacitor is grounded via the second capacitor. The middle point of the first capacitor and the second MOS switch is connected to the ground via the third MOS switch, and the circuit of the second system Side fourth MOS switch, an output side fifth MOS switch, a sixth MOS switch, a third capacitor, and a fourth capacitor, and the fourth MOS switch is connected to the vertical readout line, and A 4MOS switch, the third capacitor, and the fifth MOS switch are connected in series, and a midpoint between the fourth MOS switch and the third capacitor is connected to the ground via the fourth capacitor, The midpoint of the fifth MOS switch is connected to the ground via the sixth MOS switch.
[0015]
  In an eighth aspect based on the second aspect, the post-processing circuit includes a first difference between a signal voltage corresponding to the signal charge generated in the first exposure period and a dark signal output after the reset. A second signal voltage corresponding to the signal charge generated during the second exposure period, which is a time different from the time of the first exposure period and the dark signal output after the reset Holding a differential voltage, aligning the output level according to the difference between the first exposure time and the second exposure time, and comparing the first differential voltage and the second differential voltage after aligning the output level It is a synthesis circuit that outputs either one of them and generates a difference signal between the first differential voltage and the second differential voltage after the output levels are made uniform.
[0016]
  According to a ninth aspect based on the eighth aspect, the synthesis circuit includes a first system circuit, a second system circuit, a comparator, a difference detection circuit, an output from the first system circuit, and the first system circuit. A switch for switching to any one of the outputs from the second system circuit, the first system circuit comprising: a first MOS switch on the input side; a second MOS switch on the output side; and a third MOS switch; A first capacitor, a second capacitor, and a first variable gain amplifier, wherein the first MOS switch is connected to the vertical readout line; the first MOS switch; the first capacitor; the second MOS switch; The first variable gain amplifier is connected in series, and a midpoint between the first MOS switch and the first capacitor is connected to the ground via the second capacitor. The middle point of the first capacitor and the second MOS switch is connected to the ground via the third MOS switch, and the second system circuit includes a fourth MOS switch on the input side and a fifth MOS on the output side. A switch, a sixth MOS switch, a third capacitor, a fourth capacitor, and a second variable gain amplifier, the fourth MOS switch being connected to the vertical readout line, the fourth MOS switch, 3 capacitors, the fifth MOS switch, and the second variable gain amplifier are connected in series, and a midpoint between the fourth MOS switch and the third capacitor is connected to the ground via the fourth capacitor, and the third capacitor The midpoint of the capacitor and the fifth MOS switch is connected to the ground via the sixth MOS switch, and the comparator Is connected to the variable gain amplifier of the system with the longer exposure time, compares the output of the variable gain amplifier with a reference value, and supplies a comparison result to the switching control terminal of the changeover switch, The difference detection circuit is connected to the first variable gain amplifier and the second variable gain amplifier.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0019]
<< First Embodiment >>
Figure1 is a diagram illustrating an internal circuit configuration of the imaging apparatus 13.
  In FIG. 1, in the imaging device 13, unit pixels 1 are arranged in a matrix with n rows and m columns. These unit pixels 1 are composed of a photodiode PD that performs photoelectric conversion, a charge transfer MOS switch QT, a charge reset MOS switch QP, a row selection MOS switch QX, and a junction field effect transistor. It is comprised from the element QA.
[0020]
The outputs of such unit pixels 1 are connected in common for each vertical column, and m vertical readout lines 2 are formed. A current source 4 is connected to each of the vertical read lines 2.
The imaging device 13 is provided with two vertical shift registers 3a and 3b. Among them, the clock φCK and the serial input φDTa are given to the vertical shift register 3a. Shift outputs φTa1 to n of the vertical shift register 3a are applied to first inputs of AND circuits AP1 to APn, respectively. A control pulse φPX is commonly applied to the second inputs of the AND circuits AP1 to APn. The outputs φPX1 to n of the AND circuits AP1 to APn are applied to the gates of the MOS switches QX in each row.
[0021]
On the other hand, the clock φCK and the serial input φDTb are supplied to the vertical shift register 3b. Shift outputs φTb1 to n of vertical shift register 3b are applied to first inputs of AND circuits AT1 to ATn and AND circuits AR1 to ARn, respectively. A control pulse φTG is given to the second inputs of the AND circuits AT1 to ATn. The outputs φTG1 to n of the AND circuits AT1 to ATn are applied to the gates of the MOS switches QT in each row. A control pulse φRG is applied to the second inputs of the AND circuits AR1 to ARn. The outputs φRG1 to n of the AND circuits AR1 to ARn are given to the gates of the MOS switches QP in each row.
Further, post-processing circuits 6 are connected to the vertical readout lines 2 respectively. The output of the post-processing circuit 6 is sequentially read out via the horizontal read line 9.
[0022]
[Circuit Configuration of Post-Processing Circuit 6 in First Embodiment]
FIG. 2 is a diagram showing a circuit configuration of the post-processing circuit 6 in the first embodiment.
Inside the post-processing circuit 6, the vertical readout line 2 is connected to the horizontal readout line 9 through the buffer amplifier AA, the MOS switch QB, the capacitor CC and the MOS switch QD in series. The midpoint between the MOS switch QB and the capacitor CC is connected to the ground via the capacitor CB. The midpoint between the capacitor CC and the MOS switch QD is connected to the ground via the MOS switch QC.
[0024]
[Description of Operation of First Embodiment]
FIG. 3 is a timing chart for explaining the operation of the first embodiment.
Hereinafter, the operation of the first embodiment will be described with reference to FIG.
First, at time T1 in FIG. 3, a single pulse is input to the serial input φDTb of the vertical shift register 3b. The vertical shift register 3b shifts this single pulse by one stage and outputs it as a shift output φTb1. By this shift output φTb1, the AND circuits AR1 and AT1 in the first row are activated, and the control pulses φRG1 and φTG1 are continuously output.
[0025]
This control pulse φRG1 turns on the MOS switch QP in the first row. As a result, the gate voltage of the amplification element QA in the first row is reset.
Subsequently, the MOS switch QT in the first row is turned on by the control pulse φTG1. Then, the signal charge of the photodiode PD in the first row is absorbed by the gate capacitance of the amplifying element QA and reset. The photodiode PD in the first row newly starts to accumulate signal charges from this reset point.
[0026]
Such a reset operation is sequentially executed for the second and subsequent rows by the shift operation of the vertical shift register 3b. The L line in FIG. 4 shows a state in which the reset process of the photodiode PD is sequentially executed for each line.
Next, at time T2 in FIG. 3, a single pulse is input to the serial input φDTb of the vertical shift register 3b. The vertical shift register 3b shifts this single pulse by one stage and outputs it as a shift output φTb1. By this shift output φTb1, the AND circuits AR1 and AT1 in the first row are activated, and the control pulses φRG1 and φTG1 are continuously output.
[0027]
This control pulse φRG1 turns on the MOS switch QP in the first row. As a result, the gate voltage of the amplification element QA in the first row is reset.
Subsequently, the MOS switch QT in the first row is turned on by the control pulse φTG1. Then, the signal charge of the photodiode PD in the first row is transferred to and held in the gate capacitance of the amplifying element QA.
[0028]
Such a holding operation is sequentially executed for the second and subsequent rows by the shift operation of the vertical shift register 3b. Row K in FIG. 4 shows a state in which the holding process of the amplifying element QA is sequentially executed in units of rows.
Next, at time T3 in FIG. 3, single pulses are simultaneously input to the serial inputs φDTa and φDTb of the two vertical shift registers 3a and 3b.
[0029]
The vertical shift register 3a shifts this single pulse by one stage and outputs it as a shift output φTa1. This shift output φTa1 activates the AND circuit AP1 in the first row and outputs a control pulse φPX1.
This control pulse φPX1 turns on the MOS switch QX in the first row. At this time, the signal charge accumulated in the first exposure period shown in FIG. 3 is held in the gate capacitance of the amplification element QA in the first row. The amplifying element QA in the first row outputs a signal voltage corresponding to this signal charge to the vertical read line 2.
[0030]
In this state, the post-processing circuit 6 sets the MOS switches QB and QC to the on state. As a result, a charging path is formed through the capacitor CC, and the signal voltage on the vertical readout line 2 is held in the capacitor CC. The post-processing circuit 6 sets the MOS switch QC to the OFF state after holding the signal voltage.
Following such an operation, a control pulse φRG1 is output. This control pulse φRG1 turns on the MOS switch QP in the first row. As a result, the gate voltage of the amplification element QA in the first row is reset.
[0031]
Subsequently, the control pulse φTG1 is output. This control pulse φTG1 turns on the MOS switch QT in the first row. At this time, the signal charges accumulated in the second exposure period shown in FIG. 3 exist in the photodiode PD in the first row. This signal charge is transferred via the MOS switch QT and held in the gate capacitance of the amplifying element QA. The amplifying element QA in the first row outputs a signal voltage corresponding to this signal charge to the vertical read line 2.
[0032]
In this state, the post-processing circuit 6 sets the MOS switch QB to the on state. As a result, a charging path is formed via the capacitor CB, and the signal voltage on the vertical readout line 2 is held in the capacitor CB.
In this state, the MOS switches QD in the 1 to m columns are switched and set to the on state. As a result, the differential voltage between the signal voltage of the capacitor CB and the signal voltage of the capacitor CC is sequentially read out to the horizontal readout line 9 by one row. This differential voltage is a difference signal indicating a change in pixel output between the first exposure period and the second exposure period shown in FIG.
[0033]
Such a read operation is sequentially executed for the second and subsequent rows by the shift operation of the vertical shift registers 3a and 3b. The row J in FIG. 4 shows a state in which the signal voltage read operation is sequentially executed in units of rows.
By repeating the above-described series of operations for one frame, a difference signal for one screen is generated.
[0034]
[Effects of First Embodiment]
With the operation described above, in the first embodiment, a difference signal that captures a change in pixel output between the first exposure period and the second exposure period shown in FIG. 3 is obtained. The time interval between the first exposure period and the second exposure period is shorter than one frame period. Therefore, it is possible to reliably capture the moving object edge even for a high-speed moving object.
[0035]
Further, prior to the readout process, a process for holding the past pixel output is performed in advance. Therefore, unlike the conventional example 2, the exposure time is not limited in the readout period, and a moving body image can be captured even in a dark situation.
In the first embodiment, the time interval between the first exposure time and the second exposure time, the photo opportunity, and the like can be freely changed by combining the reset operation.
Next, another embodiment will be described.
[0036]
<< Second Embodiment >>
FirstThe structural feature of the second embodiment is that a post-processing circuit 16 and horizontal readout lines 9a to 9c are provided instead of the post-processing circuit 6 and the horizontal readout line 9 of the first embodiment (FIG. 1). It is a point. Hereinafter, the circuit configuration of the post-processing circuit 16 for distributed output will be described with reference to FIG.
[0037]
[Circuit Configuration of Post-Processing Circuit 16 in Second Embodiment]
In FIG. 5, inside the post-processing circuit 16, the vertical readout line 2 is branched into two systems via the buffer amplifier AA.
One first system side is connected to the horizontal readout line 9a through the MOS switch QB1, the capacitor CC1, the variable gain amplifier A1, and the MOS switch QD1 in this order. The midpoint of the MOS switch QB1 and the capacitor CC1 is connected to the ground via the capacitor CB1. The midpoint between the capacitor CC1 and the variable gain amplifier A1 is connected to the ground via the MOS switch QC1.
[0038]
The other second system side is connected to the horizontal readout line 9b through the MOS switch QB2, the capacitor CC2, the variable gain amplifier A2, and the MOS switch QD2 in this order. The midpoint between the MOS switch QB2 and the capacitor CC2 is connected to the ground via the capacitor CB2. The midpoint between the capacitor CC2 and the variable gain amplifier A2 is connected to the ground via the MOS switch QC2. Further, the outputs of the two variable gain amplifiers A1 and A2 are switched and selected via the switch SW, and then connected to the horizontal readout line 9c via the MOS switch QD3.
[0040]
[Description of Operation of Second Embodiment]
FIG. 6 is a diagram schematically showing the processing operation in units of rows in the second embodiment.
In the second embodiment, the first preceding process (reset process), the second preceding process (holding process), and the calling operation are executed synchronously at unequal intervals. As a result, two types of pixel outputs having different exposure periods can be obtained in one frame period. These two types of pixel outputs are time-divisionally output to the vertical readout line 2 during readout processing.
[0041]
On the first system side, the MOS switches QB1 and QC1 are set to the on state while the first type of pixel output is being output. As a result, a charging path is formed through the capacitor CC1, and the first-type pixel output is charged in the capacitor CC1.
After charging the first type of pixel output, the first system side sets the MOS switch QC1 to the off state and holds the first type of pixel output in the capacitor CC1.
[0042]
In this state, when a dark signal is output to the vertical readout line 2, a charging path is formed through the capacitor CB1, and the dark signal is charged to the capacitor CB1.
After charging the dark signal, the first system side sets the MOS switch QB1 to the off state and holds the dark signal in the capacitor CB1.
By such a double sampling operation, a differential voltage between the dark signal and the first type of pixel output is generated on the other end side of the capacitor CC1. This differential voltage corresponds to the first (true) pixel output excluding the dark signal. This true pixel output is supplied to the input terminal of the variable gain amplifier A1.
[0043]
On the other hand, the second system side sets the MOS switches QB2 and QC2 to the ON state during the period in which the dark signal is output to the vertical readout line 2. As a result, a charging path is formed through the capacitor CC2, and the dark signal is charged in the capacitor CC2.
After charging the dark signal, the second system side sets the MOS switch QC2 to the off state and holds the dark signal in the capacitor CC2.
[0044]
In this state, when a second type of pixel output is output to the vertical readout line 2, a charging path is formed via the capacitor CB2, and the second type of pixel output is charged to the capacitor CB2.
After charging the second type of pixel output, the second system side sets the MOS switch QB2 to the OFF state and holds the second type of pixel output in the capacitor CB2.
[0045]
By such a double sampling operation, a differential voltage between the second pixel output and the dark signal is generated on the other end side of the capacitor CC2. This differential voltage corresponds to the second (true) pixel output excluding the dark signal. This true pixel output is supplied to the input terminal of the variable gain amplifier A2.
The two variable gain amplifiers A1 and A2 adjust the gain and polarity in accordance with the difference in exposure time between the two types of pixel outputs, and align the output levels of the two types of pixel outputs.
[0046]
In this state, the MOS switches QD1 to QD3 in the 1 to m columns are switched and set to the on state. As a result, the first pixel output is sequentially read out by one row on the horizontal readout line 9a. The second type of pixel output is sequentially read out by one row on the horizontal readout line 9b. One of the two types of pixel outputs is sequentially read out by one row on the horizontal readout line 9c.
By repeating such a series of operations for one frame, a plurality of types of image signals having different exposure times are selectively or concurrently output within one frame period.
[0047]
[Effects of Second Embodiment, etc.]
By the operation described above, in the second embodiment, it is possible to selectively or in parallel obtain a plurality of pixel outputs having different exposure times within one frame period. Therefore, it is possible to perform auto bracketing (capturing a plurality of frames of images by changing the exposure state) within one frame period. In this case, since a plurality of frames can be taken at high speed in one frame period, the risk of missing a photo opportunity during the auto bracketing operation is reliably reduced.
[0048]
In the second embodiment described above, pixel outputs having different exposure times are distributed and output. However, the present invention is not limited to this. For example, a post-processing circuit that takes the difference between the two outputs after adjusting the gain by adjusting the gain of pixel outputs having different exposure times may be provided. In this case, as in the first embodiment, it is possible to detect the motion of a high-speed moving body.
[0049]
In the second embodiment described above, pixel outputs having different exposure times are obtained. However, the present invention is not limited to this. For example, as shown in FIG. 4, the first preceding process (reset process), the second preceding process (holding process), and the reading operation may be executed synchronously at equal intervals. In this case, it is possible to obtain a plurality of images in the same exposure state within one frame period. By sequentially recording such a plurality of images in order, it is possible to perform slow motion shooting or high-speed continuous shooting.
Next, another embodiment will be described.
[0050]
<< Third Embodiment >>
FirstThe structural feature of the third embodiment is that a post-processing circuit 26 and horizontal readout lines 9d to 9e are provided instead of the post-processing circuit 6 and the horizontal readout line 9 in the first embodiment (FIG. 1). It is a point. Hereinafter, the circuit configuration of the post-processing circuit 26 for distributed output will be described with reference to FIG.
[0051]
[Circuit Configuration of Post-Processing Circuit 26 in the Third Embodiment]
In FIG. 7, in the post-processing circuit 26, the vertical readout line 2 is branched into two systems via the buffer amplifier AA.
Among them, the first system side is input to the variable gain amplifier A1 through the MOS switch QB1 and the capacitor CC1 in this order. The midpoint of the MOS switch QB1 and the capacitor CC1 is connected to the ground via the capacitor CB1. The midpoint between the capacitor CC1 and the variable gain amplifier A1 is connected to the ground via the MOS switch QC1.
[0052]
The output of the variable gain amplifier A1 is supplied to the comparator CMP, the switch SW, and the difference detection circuit DEF. The comparison output of the comparator CMP is supplied to the switching control terminal of the switch SW.
On the other hand, the second system side is input to the variable gain amplifier A2 through the MOS switch QB2 and the capacitor CC2 in this order. The midpoint between the MOS switch QB2 and the capacitor CC2 is connected to the ground via the capacitor CB2. The midpoint between the capacitor CC2 and the variable gain amplifier A2 is connected to the ground via the MOS switch QC2.
[0053]
The output of the variable gain amplifier A2 is supplied to the switch SW and the difference detection circuit DEF, respectively.
The switching output of the switch SW is connected to the horizontal readout line 9d via the MOS switch QD4. On the other hand, the output of the difference detection circuit DEF is connected to the horizontal readout line 9e via the MOS switch QD5.
[0056]
[Description of Operation of Third Embodiment]
Also in the third embodiment, as in the second embodiment, two types of (true) pixel outputs having different exposure times are output from the variable gain amplifiers A1 and A2.
Among these, the pixel output on the long exposure time side has a higher image S / N and the black side is less crushed. Therefore, normally, the switch SW outputs a pixel output on the long exposure time side.
[0057]
However, when the pixel output level on the long exposure time side exceeds the threshold voltage Vth shown in FIG. 8, the saturation characteristic is entered and white-side collapse occurs in the gradation characteristics. Therefore, when the pixel output level on the long exposure time side exceeds the threshold voltage Vth, the comparator CMP switches the switch SW to the pixel output on the short exposure time side. The pixel output on the short exposure time side has a sufficient margin up to the saturation region, and the white side is not crushed in the gradation characteristics. In addition, since the signal level is at a sufficient level during this switching operation, a sufficient level as the image S / N can be obtained even at the pixel output on the short exposure time side. The pixel output on the short exposure time side is adjusted in gain and polarity by the variable gain amplifiers A1 and A2, and the pixel output on the long exposure time side and the output level are aligned in advance. There is no risk of a beard waveform.
[0058]
By such a switching operation, it is possible to synthesize a pixel output with a wide dynamic range from two types of pixel outputs within one frame period, as shown by the dotted line characteristics in FIG.
This wide dynamic range pixel output is sequentially output to the horizontal readout line 9d via the MOS switch QD4.
[0059]
On the other hand, two types of (true) pixel outputs having different exposure times are also input to the difference detection circuit DEF after the levels and polarities are aligned from the variable gain amplifiers A1 and A2. If the pixel output level on the long exposure time side is equal to or less than the threshold value Vth, the two types of pixel outputs are signals of substantially the same level. Based on the two types of pixel outputs having the same level, the difference detection circuit DEF generates a difference signal indicating a change in pixel output at a time interval shorter than one frame period. This difference signal is sequentially read out to the horizontal readout line 9e via the MOS switch QD5.
[0060]
[Effects of the third embodiment, etc.]
As described above, in the third embodiment, it is possible to obtain a pixel output with a wide dynamic range as shown by the dotted line characteristics in FIG.
In particular, the two types of pixel outputs have clearly short imaging time lags. Therefore, even if these two types of pixel outputs are mixed in one screen, there is almost no adverse effect such as an image failure.
[0061]
In the third embodiment described above, the dynamic range of the pixel output is expanded by switching the pixel output, but the present invention is not limited to this. For example, the dynamic range may be expanded by providing a circuit for weighted addition of pixel outputs having different exposure times. Further, pixel outputs with less white crushing (black crushing) may be synthesized by providing a circuit that performs MAX calculation (or MIN calculation) after leveling pixel outputs having different exposure times.
[0062]
<< Additional items of embodiment >>
In the embodiment described above, the post-processing circuits 6, 16, and 26 are provided for each vertical readout line 2. With this configuration, it is not necessary to use the horizontal readout line for time division, and the horizontal scanning frequency can be prevented from becoming extremely high. However, the present invention is not limited to this. For example, a post-processing circuit may be provided at the output end of the horizontal readout line. In this case, there is an advantage that there is no variation in pixel processing in units of columns.
[0063]
In the above-described embodiment, the description has been made in the order of reset processing → holding processing → reading operation, but the present invention is not limited to this. For example, when the exposure period is set by dividing one frame period into two, the reset process may be omitted. Further, the first exposure period and the second exposure period may be freely set by appropriately changing the reset processing insertion timing and the number of times. In addition, by enabling the pixel processing unit to hold a plurality of pixel outputs, three or more types of pixel outputs may be generated within one frame period.
[0064]
In the above-described embodiment, the holding process is described as the processing function of the pixel processing unit, but the present invention is not limited to this. In general, it is possible to provide a desired processing function as preprocessing for pixel output. For example, the processing functions of the pixel processing unit may include functions such as quantization processing, pixel interpolation processing, gradation conversion processing, orthogonal transformation processing, and spatial frequency filter processing.
[0065]
The “one frame period” in the claims has a broad meaning of a period (for example, one vertical scanning period) in which an image is read out by two-dimensional scanning on the imaging surface. Therefore, the above-described embodiment is not limited to an imaging apparatus that performs progressive scanning. For example, the present invention can be applied to an imaging apparatus that performs interlace scanning.
[0066]
【The invention's effect】
  One embodiment of the present inventionThe pixel output preprocessing operation and the readout operation are smoothly executed in parallel without colliding with each other. As a result, there is a pixel output for which the preprocessing has been completed in the pixel processing unit at the time of reading out the pixel output. On the other hand, the light receiving element has a pixel output including the pre-processed exposure. As described above, with the configuration of the present invention, it becomes possible to generate pixel outputs at a plurality of points in one frame period, which was impossible in the past. These pixel outputs at a plurality of points in time clearly have a shorter imaging time lag than pixel outputs between general frames. Therefore, there is a remarkable advantage that problems caused by the imaging time lag (problems described in the problem to be solved by the invention) hardly occur in subsequent image processing.
[0067]
  Another aspect of the present inventionThen, the pixel output held in the past exists in the pixel processing unit at the time of reading. On the other hand, the light receiving elements provided side by side have pixel outputs accumulated after the holding time. The difference signal generation circuit generates a difference signal that captures pixel output changes at time intervals shorter than one frame period from these new and old pixel outputs. In this case, since the imaging output time lag of the pixel output is shorter than that in the conventional example 1, it is possible to reliably capture the moving body edge of the high-speed moving body. Unlike the conventional example 2, since the exposure time is not substantially limited to the readout time, it is possible to reliably generate a moving object image even in a dark situation. Further, unlike the conventional example 2, the detection timing of the change in pixel output largely overlaps in adjacent rows, so that adverse effects such as shifting of the moving body image in units of rows are hardly caused.
[0068]
  Another aspect of the present inventionThen, the pixel output held in the past exists in the pixel processing unit at the time of reading. On the other hand, the light receiving elements provided side by side have pixel outputs accumulated after the holding time. The distribution circuit can generate a plurality of images within one frame period by distributing the pixel outputs at the plurality of time points. By such an operation, it is possible to obtain a plurality of images suitable for applications (such as auto bracketing, slow motion shooting, and high-speed continuous shooting) in which a plurality of frames are shot in a short time.
[0069]
  Another aspect of the present inventionThen, the pixel output held in the past exists in the pixel processing unit at the time of reading. On the other hand, the light receiving elements provided side by side have pixel outputs accumulated after the holding time. These pixel outputs at a plurality of points in time are clearly short with an imaging time lag of less than one frame period. By combining the pixel outputs at a plurality of points in time, the combining circuit can expand the dynamic range of the pixel output while avoiding image corruption caused by the imaging time lag.
[0070]
  Another aspect of the present inventionThen, the pixel processing unit is provided with a function of resetting the pixel output. By varying the reset timing, it is possible to freely change the photo opportunity and the exposure period for the pixel outputs existing in the pixel processing unit and the light receiving element at the time of reading.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an internal circuit configuration of an imaging apparatus 13;
FIG. 2 is a diagram showing a circuit configuration of a post-processing circuit 6 for motion detection.
FIG. 3 is a timing chart illustrating a vertical read operation.
FIG. 4 is a diagram illustrating an operation when generating a plurality of pixel outputs having the same exposure time within one frame period.
FIG. 5 is a diagram showing a circuit configuration of a post-processing circuit 16 for distributed output.
FIG. 6 is a diagram illustrating an operation when generating a plurality of pixel outputs having different exposure times within one frame period.
7 is a diagram showing a circuit configuration of a post-processing circuit 26 for expanding a dynamic range. FIG.
FIG. 8 is a diagram illustrating pixel synthesis by switching pixel outputs.
[Explanation of symbols]
PD photodiode
QT MOS switch for charge transfer
QP MOS switch for charge reset
QX MOS switch for row selection
QA amplifier
1 unit pixel
2 Vertical readout line
3a Vertical shift register
3b Vertical shift register
6, 16, 26 Post-processing circuit
9 Horizontal readout line
13 Imaging device

Claims (9)

A light receiving element that accumulates signal charges according to incident light;
A charge transfer MOS switch for transferring the signal charge from the light receiving element to a capacitor;
An amplifying element for generating a signal voltage corresponding to the signal charge accumulated in the capacitor;
A reset MOS switch for resetting the signal charge of the capacitor;
A row selection MOS switch;
Are arranged in a matrix,
A vertical readout line connected to the row selection MOS switch for each vertical column and reading the signal voltage from the amplifying element;
An output circuit comprising a shift register and a logic circuit, and outputting a control pulse to the row selection MOS switch, the charge transfer MOS switch and the reset MOS switch arranged in a row direction;
A post-processing circuit connected to the vertical readout line and holding the signal voltage output from the amplification element,
The output circuit is
In one frame period, in the same row, a control pulse for switching between the ON state and the OFF state of the reset MOS switch and the charge transfer MOS switch is output a plurality of times to set a plurality of exposure periods in one frame period. With
An imaging apparatus, wherein the row selection MOS switch is turned on only once in one frame period, and the signal voltages corresponding to the plurality of exposure periods are output to the vertical readout lines . The imaging device according to claim 1,
  The output circuit is
  An operation of transferring the signal charge generated by the light receiving element in the first exposure period to the capacitor with the charge transfer MOS switch turned on, and starting a second exposure period by the light receiving element;
  An operation of turning on the row selection MOS switch to output a signal voltage corresponding to the signal charge transferred to the capacitor to the vertical read line;
  After resetting the capacitor with the reset MOS switch turned on, the signal charge generated by the light receiving element during the second exposure period is transferred to the capacitor with the charge transfer MOS switch turned on, An operation of outputting a signal voltage corresponding to the signal charge to the vertical readout line;
  An image pickup apparatus that outputs a control pulse for performing the operation. In the imaging device according to claim 1 or 2,
  The output circuit is
  A transfer circuit that outputs a control pulse for each row to the row selection MOS switches arranged in a row direction;
  A control circuit for outputting a control pulse for each row to the charge transfer MOS switch and the reset MOS switch arranged in a row direction;
  An imaging apparatus comprising:   The imaging device according to claim 2,
  The post-processing circuit is a difference signal generation circuit that generates a differential voltage between the signal voltage obtained in the first exposure period and the signal voltage obtained in the second exposure period. Imaging device. The imaging apparatus according to claim 4,
  The difference signal generation circuit includes:
  A first MOS switch on the input side, a second MOS switch on the output side, a third MOS switch, a first capacitor, and a second capacitor;
  The first MOS switch is connected to the vertical readout line;
  The first MOS switch, the first capacitor, and the second MOS switch are connected in series,
  The midpoint of the first MOS switch and the first capacitor is connected to the ground via the second capacitor,
  The image pickup apparatus, wherein a midpoint between the first capacitor and the second MOS switch is connected to the ground via the third MOS switch.   The imaging device according to claim 2,
  The post-processing circuit includes:
  Holding a differential voltage between a signal voltage corresponding to the signal charge generated in the first exposure period and a dark signal output after the reset;
  Holding a differential voltage between a dark signal output after the reset and a signal voltage corresponding to the signal charge generated in the second exposure period;
  An image pickup apparatus that is a distribution circuit that outputs the differential voltage selectively or in parallel.   The imaging device according to claim 6,
  The distribution circuit includes a first system circuit, a second system circuit, and a selection switch for selecting the first system and the second system,
  The first system circuit is:
  A first MOS switch on the input side, a second MOS switch on the output side, a third MOS switch, a first capacitor, and a second capacitor;
  The first MOS switch is connected to the vertical readout line;
  The first MOS switch, the first capacitor, and the second MOS switch are connected in series,
  The midpoint of the first MOS switch and the first capacitor is connected to the ground via the second capacitor,
  The midpoint of the first capacitor and the second MOS switch is connected to the ground via the third MOS switch,
  The second system circuit is:
  A fourth MOS switch on the input side, a fifth MOS switch on the output side, a sixth MOS switch, a third capacitor, and a fourth capacitor;
  The fourth MOS switch is connected to the vertical readout line;
  The fourth MOS switch, the third capacitor, and the fifth MOS switch are connected in series,
  The midpoint of the fourth MOS switch and the third capacitor is connected to the ground through the fourth capacitor,
  The midpoint of the third capacitor and the fifth MOS switch is connected to the ground via the sixth MOS switch.
  An imaging apparatus characterized by that.   The imaging device according to claim 2,
  The post-processing circuit includes:
  Holding a first differential voltage between a signal voltage corresponding to the signal charge generated during the first exposure period and a dark signal output after the reset;
  The second differential voltage between the dark signal output after the reset and the signal voltage corresponding to the signal charge generated in the second exposure period, which is different from the time of the first exposure period, is held. ,
  The output level according to the difference between the first exposure time and the second exposure time is aligned, the first differential voltage after the output level is aligned and the second differential voltage are compared, and either one is output. ,
  An image pickup apparatus, comprising: a synthesis circuit that generates a difference signal between the first differential voltage and the second differential voltage after the output levels are aligned.   The imaging device according to claim 8,
  The synthesis circuit is one of a first system circuit, a second system circuit, a comparator, a difference detection circuit, an output from the first system circuit, and an output from the second system circuit. A changeover switch for switching to
  The first system circuit is:
  A first MOS switch on the input side, a second MOS switch on the output side, a third MOS switch, a first capacitor, a second capacitor, and a first variable gain amplifier;
  The first MOS switch is connected to the vertical readout line;
  The first MOS switch, the first capacitor, the second MOS switch, and the first variable gain amplifier are connected in series,
  The midpoint of the first MOS switch and the first capacitor is connected to the ground via the second capacitor,
  The midpoint of the first capacitor and the second MOS switch is connected to the ground via the third MOS switch,
  The second system circuit is:
  A fourth MOS switch on the input side, a fifth MOS switch on the output side, a sixth MOS switch, a third capacitor, a fourth capacitor, and a second variable gain amplifier;
  The fourth MOS switch is connected to the vertical readout line;
  The fourth MOS switch, the third capacitor, the fifth MOS switch, and the second variable gain amplifier are connected in series,
  The midpoint of the fourth MOS switch and the third capacitor is connected to the ground through the fourth capacitor,
  The midpoint of the third capacitor and the fifth MOS switch is connected to the ground via the sixth MOS switch,
  The comparator is connected to the variable gain amplifier of the system with the longer exposure time, compares the output of the variable gain amplifier with a reference value, and supplies a comparison result to the switching control terminal of the changeover switch,
  The difference detection circuit is connected to the first variable gain amplifier and the second variable gain amplifier.
  An imaging apparatus characterized by that.

Images