JP2003527775A - Image sensor structure for pixel-based charge integration control - Google Patents

Abstract

(57) [Summary] A sensor array that generates an image captured at the end of a time frame. The array has a plurality of unit cells for detecting an image by multiple within-frame charge-integrations, and control means for individually controlling each of the unit cells. The unit cells are programmable multiple charge-integration unit cells having photocurrent integrating and non-integrating modes. The control means includes means for controlling the charge integration a plurality of times independently of the charge integration of the other unit cells in a single frame capture of each unit cell.

Description

Detailed Description of the Invention

FIELD OF THE INVENTION The present invention relates generally to image sensor array structures, and more particularly to logic control thereof.

BACKGROUND OF THE INVENTION Image sensors generally include an array of detection unit cells, each unit cell including a pixel that is exposed to light and produces an electrical response that represents it. The following defines the basic terms used in connection with image sensor technology and some known methods therefor.

The minimum signal that can be detected by an image sensor is defined as the minimum incident light intensity that is incident on a pixel and produces a recognizable and meaningful signal above the noise level. It is considered that the signal of the light intensity smaller than the noise level acts in the cutoff region of the image sensor.

The maximum signal that can be detected by an image sensor is defined as the maximum incident light intensity that is incident on a pixel of the image sensor to produce a discernable desaturation response. Signals with light intensity higher than this level are considered to be in the saturation region.

The area between the cutoff area and the saturation area is defined as the sensitivity area of the image sensor. The intensity of the optical signal within the sensitivity region of the image sensor causes a response signal corresponding to the intensity of the input light.

The resolution and the minimum sensitivity determine the noise floor. Dynamic range (DR) characteristics are defined in terms of the ratio of the maximum strength limit to the minimum strength limit. The dynamic range of an image sensor can be expressed in three equivalent ways.

[0007]   In the first method, the dynamic range is represented by the ratio:

[0008]

[Equation 1]

Here, DR ¹ _L is a dynamic range characteristic of the image sensor, and n is a positive number (normally rounded to an integer).

Therefore, an image sensor having a dynamic range of 10 ³ : 1 has 10
It can capture signals as large as 00 times.

The second method of expressing the dynamic range is logarithmic and is expressed as follows.

[0012]

[Equation 2]

A third method often used to describe the dynamic range of an image sensor is by the number of bits required to represent the dynamic range in binary form. This number of bits is directly related to the dynamic range by the equation:

[0014]

[Equation 3]

[0015]   Here, Nb is the number of bits, and Intg is a function for extracting the integer part of the argument.

Ideally, the most desirable image sensor is one that mimics the properties of the human eye and captures a scene with properties comparable to the retina of the human eye. However, the retina of the human eye has a dynamic range of 10 ⁸ : 1 whereas the commercially available image sensor “silicon retina” typically has a dynamic range of 10 ³ : 1. Thus, the characteristics of the silicon retina are considerably inferior to the dynamic range characteristics of the human eye.

Dynamic range is a central issue in image sensor design research. The basis of this research is to understand the function of the retina of the human eye. The wonderful properties of the retina of the human eye result from the fact that each photoreceptor of the retina locally modulates its sensitivity to incident light. The individual photoreceptors in the retina of the human eye are each 103: 1.
Although it has only a dynamic range of
The ability to regulate t point) "results in much better overall retinal properties.
Being able to shift the operating point means that the photoreceptor reduces its sensitivity when exposed to high intensity light and increases its sensitivity when exposed to low intensity light. To do.

Research into improving the dynamic range of artificial retinas has been intensively conducted and today takes one of the following forms:

Logarithmic sensor : This type of sensor logarithmically compresses the dynamic range.
Logarithmic compression is done by a photodetector that behaves logarithmically, or a circuit that responds logarithmically to the incoming photocurrent.

However, these circuits are susceptible to manufacturing processes, and slight differences in manufacturing processes can result in varying pixel response sensitivities. Even the adjacent pixels may have greatly different response sensitivities. Such inhomogeneity appears as fixed pattern noise (FPN) and causes another cause of poor image quality.

Multiple exposure sensor : obtain multiple images with different exposures (charge integration time),
Combine them to form one image. Typically, the combination of images of different exposures is done at the video output of the image sensor.

Due to the limitations associated with image acquisition time and image-combining, which are computationally expensive / time-consuming, this method is usually limited to the acquisition and processing of two images. The drawback of this method is that if the exposure times of the two acquired images are significantly different, the result is image-color artifacts.
cts) and edge artifacts.

Autonomous / Per-Pixel Controlled- Exposure Time Sensor : Due to this method, the exposure time of each pixel is controlled independently and locally to the incident light intensity. Adjusted. The best results are obtained if this method is carried out efficiently. Two notable attempts in this direction have been reported.

One method reported is based on a unit cell incorporating a static set-reset flip-flop. Charge accumulation is triggered by resetting each pixel at a programmable point (time), which controls the charge integration time. Unfortunately, the result is a larger unit cell area, a smaller fill factor, or both. Therefore, this unit cell is not suitable for a fine pixel / high resolution image sensor.

Furthermore, the dynamic range of the image sensor is determined by the column scan rate (column sca
n rate). The column scan rate is limited by the programming rate of each column. For example, if the column scan rate is done at the pixel clock rate (which itself is problematic and causes noise), each column program must be loaded in one pixel time. This can only be done by a very wide and fast bus that loads the row control registers.

SG Chen and JP Lee wrote in their paper “Adaptive Sensitivity CCD Image Sens.
or: Charge-Coupled Devices and Solid-State Optical Sensors V ”(Proc. SPI
E, Vol. 2415, pp. 303-309, 315), the use of flip-flops is considered. However, they do not elaborate on its implementation in the paper. In this paper, implementation is limited to three different exposure times with a ratio of 64: 8: 1. In many scenes, these steps are generally too coarse to remove quantization artifacts.

The second method reported is Independent Pixel Reset.
set: IPR) method. This method requires resetting the charge on the integrating capacitor in each unit cell independently. Each unit cell is individually reset through the row reset control and column reset control circuits. This method provides an area efficient solution.

However, this method is limited in its scope. This is because unit cells with the same exposure time are not reset at the same time. That is, the unit cell in the upper left corner of the image sensor array is reset much faster than the unit cell in the lower right corner. For example, if the array consists of 768 x 483 rows and the reset is done with a pixel clock of 67 nsec, the time difference between the upper left corner reset and the lower right corner reset would be 24.86 msec, which is unacceptable for commercial video applications. Therefore, this method is not suitable for large arrays for video rates of 30 frames per second in real time.

Further, the exposure time of the sensor is, for example, 1, 1/2, 1/4, 1/8 of the maximum integration time.
And a few values such as 1/16, which is unsatisfactory in real-time high quality imaging. Therefore, the IPR technique is currently unsuitable for most commercial applications.

SUMMARY It is an object of the present invention to provide a new and improved CMOS image sensor structure that facilitates scene capture with improved properties and dynamic range.

According to a preferred embodiment of the present invention, a sensor array is provided that produces a captured image at the end of a time frame. The array has a plurality of unit cells for detecting an image by a plurality of multiple within-frame charge-integrations, and a control means for individually controlling each of the unit cells. The unit cell is a programmable multiple charge-integration unit cells having a photocurrent integrating and non-integrating mode.
).

Each unit cell includes a photodetector, a charge storage element that stores the charge transfer from the photodetector, and a programmable memory unit that stores the charge integration state of the unit cell.

The control means includes means for controlling charge integration a plurality of times independently of charge integration of other unit cells in a single frame capture of each unit cell.

The control means includes means for providing N charge integration sub-periods within a single frame capture, where N is equal to or greater than 1.

Within each single frame capture, the control means individually and individually integrate the charges of each unit cell within a given cell group. Generally, the control means includes row select lines and column select lines. The row selection line transfers a plurality of first signals to the unit cell, and the column selection line transfers a plurality of second signals (eg, program and sense signals) to the unit cell.

Further, the control means also programs the unit cell. One group of cells (eg, one line of unit cells) are programmed at about the same time, preferably sequentially. The means for programming may also include means for sequentially programming one or more lines containing a plurality of unit cells.

The control means comprises means for defining a charge integration sub-period, where in another aspect the charge integration sub-period takes a variable length of time. The control means also includes means for providing fine time resolution in clock time units and means for providing a wide dynamic range of charge integration steps. Usually, the wide dynamic range is within 2 ^N −1 integration time unit steps.

Further in accordance with a preferred embodiment of the present invention, there is provided a method for detecting an image in a plurality of unit cells. This method includes the steps of individually accessing each of the unit cells and controlling the charge integration of each unit cell independently of the charge integration of a plurality of other unit cells.

The method further includes the steps of determining a charge integration time for each unit cell and programming each unit cell based on the determined charge integration time.

Further, according to a preferred embodiment of the present invention, there is provided a method for improving the intra-scene dynamic range of an image sensor array composed of a plurality of unit cells. This method includes a process of individually accessing each unit cell and a process of individually controlling each unit cell.

The method also includes individually controlling the charge integration time of each of the unit cells, which includes individually programming each cell. The step of individually programming includes the step of programming each unit cell based on a predetermined charge integration time and the step of programming each unit cell with a plurality of charge integration sub-periods.

Further in accordance with a preferred embodiment of the present invention, there is provided a programmable image sensor including a plurality of unit cells for capturing an image. This sensor has a first plurality (P) of input lines carrying data and a second plurality ((P) of input lines connected to the cells.
H) columns (where P is less than or equal to H) and receives data and selectively receives the data to program the array N times within a single frame of motion video. A controller for distributing to the rows.

Generally, the data is programming data and includes charge integration / non-integration state data for each of the plurality of unit cells. Preferably, each of the plurality of programmable unit cells is individually controlled.

DETAILED DESCRIPTION OF THE INVENTION In the following, a novel CMOS that facilitates independent control of the charge integration time of each pixel
The image sensor structure and method will be described in detail. In the preferred embodiment, independent per-pixel exposure control is achieved by directly and independently controlling the charge integration time of the pixel.

The present invention describes two novel image sensor structures used for both interlaced and non-interlaced. Preferably, the image sensor structure includes a plurality of image sensor unit cells capable of multiple charge integration sub-periods, allowing for individual charge integration times for each pixel.

The practice of the present invention facilitates programming the charge integration time in many, varying, small steps. The result is hundreds or thousands of exposure time values. This is important for effective dynamic range compression and removal of quantization noise and image artifacts. For moving video, exposure times in the range of 2 ¹⁰ : 1 unit steps are possible. This helps achieve a wide dynamic range scene capture that is roughly comparable to the characteristics of the retina of the human eye.

Further, with the novel use of the row program loader, the present invention provides different charge integration times for all pixels simultaneously. The present invention describes loading all line programs at video rate, one line at a time. Furthermore, this operation is done outside the image sensor array.

Please refer to FIG. FIG. 1 illustrates an array 10 which is a new and improved non-interlaced CMOS image sensor array structure. The array 10 includes a plurality of unit cells 12 to implement independent, pixel-by-pixel charge integration control.

Please also refer to FIG. FIG. 2 shows a unit cell 12 which is a basic building block of the array 10. The unit cell 12 captures light and produces a corresponding electrical signal. Preferably, the unit cell 12 is a patent application PCT / 1L00 / 00129 (CMOS Unit Cell with Autonomous / Per-Pixel Charge Integr) filed on Mar. 2, 2000.
ation Time Control Circuit), a plurality of integration sub-periods are possible, as is the case with the unit cell disclosed in the ation time control circuit. Patent application PCT / 1L00 / 00129 was filed by the same applicant as this application and is hereby incorporated by reference.

For purposes of clarity, reference herein to “unit cell” is the same as reference to “pixel” and “integral” is synonymous with charge integral.

All unit cells 12 in array 10 undergo a programming cycle, as described in more detail below, where they are programmed for a predetermined integration time.
Each such program cycle is followed by a predetermined integration time. Each such predetermined integration cycle may include a series of integrating sub-periods and / or a series of non-integrating sub-periods. When the integration time ends, the unit cell 12 is read out. The reset, programming cycle, integration cycle and read operation are repeated. Integration time is defined as the time from reset to read.

During the integration sub-period, the pre-programmed unit cell 12 injects charge into the integrating capacitor within the unit cell 12. During the non-integrating sub-period, the integrating capacitor stores the collected charge, but the preprogrammed unit cell 12 does not inject additional charge into the capacitor. As explained in PCT / 1L00 / 00129,
There may be multiple integrating and non-integrating sub-periods, alternating between integrating and non-integrating, depending on a predetermined programmed cycle.

During the integration time, all unit cells 12 initially enabled for charge integration
Is "exposed" to light intensity. Note that the integration time is the same for all unit cells 12, but the charge collected during this period is different for each unit cell 12.
The charge stored in each unit cell 12 is proportional to the effective charge integration time (ie, the sum of the various integrating subperiods for each pixel) and the local intensity of the incident light.

The unit cell 12 maintains the charge previously stored in its integrating capacitor unless actively discharged. As such, the unit cell 12 functions as an analog memory element that holds an analog signal.

Therefore, the total integration time and total accumulated charge of each unit cell 12 depends on the associated series of programmed integrating / non-integrating states, and each sub-period is subject to a different charge integrating action. Based on PCT / 1L00 / 00129,

[0056]

[Equation 4]

For a special case such that, the following relationship is obtained (T ₀ is the basic time unit,
T _m is the Int signal that remains “high” in the i th integration sub-period,
q is the number of program / integration sub-periods in the sequence, T is the total charge integration time).

[0058]

[Equation 5]

[0059] as well as,

[0060]

[Equation 6]

Therefore, the integration time can be programmed by a binary number (u _q-1 u _q-2 ... u ₂ u ₁ u ₀ ) ₂ .

[0062]   (U_q-1u_q-2． ． ． u_Twou₁u₀)_TwoIs (00 ... 01)_TwoWhen T _i (Min) = T₀Is the shortest integration time.

When (u _q-1 u _q-2 ... u ₂ u ₁ u ₀ ) ₂ is (11 ... 11) ₂ , T
Is the longest integration time, ie

[0064]

[Equation 7]

[0065] Becomes

Here, T _max is the maximum integration time, q is the number of program / integration sub-periods, and T ₀ is the basic charge integration time unit.

(U _q-1 u _q-2 ... u ₂ u ₁ u ₀ ) ₂ can take any integer between the minimum value and the maximum value, and can be changed in units of T ₀ . Therefore, the integration time is T ₀ , 2
T ₀ , 3T ₀ ,. ． ． Can take any value up to T _max in steps of T ₀ .

The charge collected or the corresponding voltage is proportional to the total integration time and the magnitude of the photocurrent. The photocurrent itself is proportional to the intensity of the incident light.

[0069]   This can be summarized in the following two equations.

[0070]

[Equation 8]

[0071]

[Equation 9]

Here, I _ph is the photocurrent, T is the total integration time, C _I is the capacitance of the integrating capacitor, Q ^a is the charge accumulated in the integrating capacitor, and V ^C is the voltage across the integrating capacitor. is there.

[0073]   The implementation of equations (4)-(9) will be described later with reference to FIGS.

Referring to FIG. 1, array 10 comprises an array of lines arranged in rows along the x-axis and columns along the y-axis. The unit cell 12 is arranged at and connected to the x and y nodes of these lines. These lines carry electrical signals that control the integration time of each unit cell 12. For ease of identification, each unit cell 12 is designated by its position on the x, y axis. For example, (y = 0, x = 0
Unit cell 12 located at)) is identified as unit cell 12 (0,0) and (y = V
The unit cell located at -1, x = H-1) is identified as the unit cell 12 (V-1, H-1).

Array 10 further includes a plurality of circuits arranged on a horizontal axis and a vertical axis. In one preferred embodiment, read circuit 14 and row program loader 18 are arranged along a horizontal axis or y-axis, and row program / read decoder 16 is arranged along a vertical axis or x.
Located along the axis. The use of terms such as vertical and horizontal is intended for the sake of clarity, and it is within the scope of the present invention to arrange these circuits in different places.

In the preferred embodiment, the array of lines is a row read (RwRd) line, a row program (RwPrg) line, a column detect (ColSense) line, a column program (ColPrg) line, a reset (Rst) line, and an integration (RwRd) line. Int) line is included. Each line carries an associated signal. That is, the RwRd line carries the RwRd signal,
Others are the same.

The designation of the position of each line is represented by, and is generally designated by, its position on the x or y axis. That is, the ColPrg line located at x = 0 is shown as the ColPrg_0 line, and the RwPrg line located at y = i is shown as the RwPrg_i.

Int line : An Int (that is, integration) line is one line divided into a plurality of lines, and is connected to all the unit cells 12. The Int line carries the Int signal. The integration in all unit cells 12 is controlled by the Int signal. Preferably, charge integration is performed when the Int signal is high. Between integral sub-periods (I
The associated unit cell 12, which is programmed to integrate (when the nt signal is high), performs charge integration.

Even if the particular unit cell 12 is programmed to integrate during a particular sub-period, the integration will only occur when the Int signal is high. Conversely, even if the Int signal is high, integration will not occur if the particular unit cell 12 is programmed to not integrate.

Rst line : The Rst (that is, reset) line is one line divided into a plurality of lines, and is connected to all the unit cells 12. The Rst line carries the Rst signal that resets all the unit cells 12 in the array 10 simultaneously. Rst signal is unit cell 12
The transistor inside is turned on, the electric charge remaining after the previous reading is extracted, and the state of the integration capacitor is adjusted in preparation for the next integration time.

Alternatively, the reset does not necessarily have to be done explicitly, but may be done implicitly during the read phase. In that case, the Rst line and associated transistors are removed.

RwRd Line : In the preferred embodiment, the RwRd (ie, row-read) line is connected to the row program / read decoder 16, and the RwRd line is located over a range of RwRd_0 to RwRd_V-1. . Each RwRd line is connected to the associated unit cell 12 on its respective row. The RwRd line carries the row read (RwRd) signal that controls the reading of the associated unit cell. When the RwRd_i signal is high and all other RwRd signals are low, the contents of unit cell 12 (i, j) are read. Normally, the unit cell 12 is read after the end of the charge integration cycle.

RwPrg line : In the preferred embodiment, RwPrg (ie, row-progra
m)) line is connected to the row program / readout decoder 16 and the position designation of the RwRd line spans the range RwPrg_0 to RwPrg_V-1. Each RwPrg line is connected to the associated unit cell 12 on each row. The RwPrg line carries the row program (RwPrg) signal that controls programming of the associated unit cell. The programming of the unit cells 12 determines the charge integration sequence for each unit cell 12. Preferably, the programming is done row by row. That is, when the RwPrg_i signal is high and all other RwRd signals are low, the unit cell 12 in row i is programmed.

In the preferred embodiment, programming of the unit cell 12 is done prior to the start of reading or off-line. Thus, time consuming programming does not affect the integration or read timing of array 10.

The RwRd signal and the RwPrg signal function in cooperation with each other. When the RwRd signal is high, R
The wPrg signal is low and vice versa.

RdEn and PrgEn signals : The RwRd signal activates the RdEn (ie, read-enable) signal that allows the reading of the accumulated charge (current / voltage) of the associated unit cell 12 to be read. (Activate) Similarly, the RwPrg signal activates the PrgEn (ie, program-enable) signal that allows programming of the associated unit cell 12.

ColSense and ColPrg lines : In the preferred embodiment, ColSense (ie, line detection (colu
mn-sense)) and ColPrg (i.e., column-program) lines extend between the row program loader 18 and the read circuit 14. In a preferred embodiment, the ColSense and ColPrg lines are alternately active. That is, ColSen
ColPrg is inactive when the se line is active and vice versa. In this way, the same physical line can be used for both functions. Alternatively, the ColSense line and the ColPrg line can be physically separate lines.

The ColSense / ColPrg line position designation is from ColSense_0 / ColPrg_0 to ColSense_H-1.
/ ColPrg_H-1 range. Each ColSense / ColPrg line is connected to all associated unit cells 12 on the column.

In the preferred embodiment, the ColSense / ColPrg lines are common to programming and reading and carry the ColSense / ColPrg signals. The ColSense / ColPrg signal is a multiplexed input / output signal that alternates as the input signal during the charge integration time and as the output signal during the read cycle.

During the programming sequence, the ColSense / ColPrg signals are ColPrg_0 / ColPrg_V-1.
ColPrg, which acts as a line and is actively driven by the line program loader 18.
Provide a signal. The value of the ColPrg signal determines whether or not the unit cell 12 integrates the photocurrent charge in the next integration subperiod.

When the ColPrg signal is low, the unit cell 12 is preprogrammed to disallow charge integration. Conversely, when the ColPrg signal is high, the unit cell 12 is preprogrammed to allow charge integration. In another embodiment, the unit cell 12 is ColPrg.
It may be programmed to respond to the opposite polarity of the signal.

During the read cycle, the ColSense / ColPrg lines act as ColSense_0 / ColSense_H-1 and provide the ColSense signal. The line program loader 18 outputs three states (
read from the associated unit cell 12 is enabled,
The read signal is sent to the read circuit.

Row Program / Read Decoder 16 : Decoder 16 selects one or more RwRd lines and activates the RwRd signal. This enables the reading of the accumulated charge in the associated unit cell 12. In the preferred embodiment, the read phase of the selected unit cell 12 is such that the RwRd signal is high and at the same time RwPrg.
This is done when the signal is low and no row programming is taking place.

The row program / read decoder 16 activates a predetermined combination of line address (RwAdr) input signals to specify the appropriate RwRd line (eg, RwRd_z) to be selected for reading. The combination of such RwAdr signals is the number "z"
Generate a binary combination that represents.

On the contrary, in the programming phase of the array 10, the RwRd line becomes inactive and the RwPrg line becomes active, so that the unit cells 12 in the array 10 can be programmed row by row. Similar to the behavior of RwRd, it activates a given combination of RwAdr input signals to specify the appropriate row for programming.

The selection of the appropriate RwAdr signal is calculated as follows. If “a” is the number of RwAdr signals,

[0097]

[Equation 10]

[0098]

[Equation 11]

(A) If one of the combinations such that z ≧ V−1 is selected, all RwRd lines and RwPrg lines are not selected. (B) When all RwRd lines are deselected and the RwRd signal is low, the row program / read decoder 16 selects one of the RwPrg lines. Therefore, the specific R
For the wPrg_z line (where z = (RwAdr _a-1 , RwAdr _a-2 , ..., RwAdr ₁ , RwAdr ₀ ) ₂ ), all the unit cells 12 (z, j) on the RwPrg_z line are Selected and programmed simultaneously by the ColPrg_0 / ColPrg_H-1 lines connected to it.

In the preferred embodiment, a dynamic row program / read decoder 16 is recommended. As a result, the row clock (RwClk) is used for the internal decoder precharge. Precharge is done before each row selection. Internal pre-charge deselects all RwRd and RwPrg lines by pulling all lines low. Note that other selection / deselection timing mechanisms are possible and are within the scope of the invention.

Read Circuit 14 : The read circuit 14 enables the reading of the collected charge from each unit cell 12 in the array 10. The read circuit 14 has one sense amplifier (not shown) for each ColSense line or column. The sense amplifier detects the electrical signal from the unit cell being read (either charge, voltage or current) and converts the detected signal into a more robust video signal.

The RwRd signal enables read-out of each row on a row-by-row basis, and enables the sense amplifier to read the unit cell 12 on a row-by-row basis. The output from each sense amplifier is temporally multiplexed and sent to the output of the read circuit. A pixel clock (PrgClk) signal that cooperates with the read (RdOut) signal is received by the read circuit 14, which drives the read and adjusts the read timing of the unit cell 12. A signal representing each of the collected charges is converted into a video signal Vout and sequentially output through the output buffer 34.

Various implementation modes of the read circuit 14 are possible. For example, the video output can be speeded up by demultiplexing the video outputs and reading them simultaneously through multiple video outputs.

In another preferred embodiment, different read structures and different output sequences are implemented. For example, some pixels may be read in the same pixel period to increase the reading speed.

Row Program Loader 18 : Referring to FIG. 3, a preferred embodiment of the row program loader 18 is shown. The row program loader 18 integrates each of the unit cells 12
Facilitates programming into non-integrating state. The row program loader 18 is preferably loaded from a program memory or a charge integration program generator (not shown). This memory or charge integration program generator is array 1
It is either part of 0 or outside the structure and is put into the program loader 18.

In the preferred embodiment, a single line program is loaded into the internal memory of line program loader 18 via a plurality of external input lines 28. The input pin of each input line 28 is connected to one of a plurality of shift register inputs 30 used to shift in and input row programs. Each shift register 30 has k (or r) stages 31. Preferably, each shift stage 31 is a D flip-flop, and the input to stage 31 is shown as D, the output is shown as Q, and the clock input is shown as CK in FIG.

[0107]   The total number of stages 31 corresponds to the total number of ColPrg lines in array 10.

By way of example, array 10 includes p shift registers 30. Therefore, H
Is the number of ColPrg lines in the array (also the total number of stages 31), p is the number of input lines 28 to the row program loader 18 (also the number of shift registers 30), and p-1 registers If 30 has k stages 31 and one register 30 has r stages 31 (where r ≦ k),

[0109]

[Equation 12] Holds.

Example 1 : In one preferred embodiment of the row program loader 18, H = 768 columns in array 10
Included in each of the p = 16 input lines 28 is associated with a shift register 30
Connected to. Each of the 16 shift registers 30 has k = 48 stages 3
Including 1. Therefore, the relationship of 768 = 16 · 48 is established. In this example, r = 0
And therefore H = (p · k).

Example 2 : In another preferred embodiment of the row program loader 18, H = 756 columns are in array 1.
0, there are p = 16 input lines 28. The p input lines 28 are k
= 15 shift registers 30 having 48 stages 31 and one shift register 30 having r = 36 stages. Therefore, 756 =
[(16-1) · 48] + (1.36) = (15 · 48) +36 holds.

To speed up the row program loading, all p shift registers 30 are loaded simultaneously by p input lines 28. In the preferred embodiment of the present invention, input line 28 loads data into shift register 30 in order from least significant bit to most significant bit. In this way, when the program data is sequentially input with the least significant bit first and the most significant bit last, after k shifts,
The data will be stored in the shift register 30 in the correct order (from left to right).

However, an exception to this rule is the last shift register 30 with r stages 31 (r is less than or equal to k). Therefore, in order to synchronize the operation with the other p-1 shift registers 30, the data for the last shift register 30 is k-.
It must start with r garbage / don't care information bits, followed by r information bits.

The time T _LdRw taken to load all lines is

[0115]

[Equation 13] Or

[0116]

[Equation 14]

[0117] Becomes Here, the Intg function is the integer part of the function argument.

Example 3 : In this example of row program loader 18, H = 768 columns are included in array 10 and there are p = 32 input lines 28, each connected to an associated shift register 30. It Each shift register 30 includes k = 24 stages 31.

For the programming clock of 57.272 MHz (four times the frequency of the pixel clock, that is, 4.14.318 MHz = 57.272 MHz), T _p = (
The clock time) is 17.46 nsec. Therefore, the time T _LdRw required to load all lines is 419.04 nsec.

[0120]   419.04 nsec = 24 · 17.46 Or   419.04 nsec = [1 · (768/32)] · 17.46 That's why.

Shifting in the last bit of the row program sends the entire program to the line register LR, which preferably comprises a series of D flip-flops.

The data or program stored in the line register LR is loaded by row (LdRw)
It is sent over the line to a set of H tri-state buffers 32. Each tri-state buffer 32 drives the associated ColPrg line, enabling programming of the associated column.

As described above, the value of the ColPrg signal determines whether the unit cell 12 integrates the photocurrent charge in the integrating / non-integrating sub-period. Therefore, the data loaded into the ColPrg line by the buffer 32 is the next integral / value of the associated unit cell 12.
A series of values (0 and 1) that define the non-integrating sub-period.

Once the data has been transferred to the line register LR and programming of the associated column has begun, the shift register 31 is free and ready to receive data for program loading of the next line. Therefore, programming of the ColPrg_i line is done simultaneously with the subsequent loading of ColPrg_i + 1.

For an embodiment where there are V rows, the time taken to load the entire array 10 is given by:

[0126]

[Equation 15]

Example 4 : For the case described in Example 3, if the array 10 has V = 483 rows, then T _prg = 202.39632 μsec = 483 · [1 · (768/32)] · 17.46.

Still referring to FIGS. 4A and 4B, one line of programming performed by the row program loader 18 is illustrated. 4A and 4B
The signals shown in are received from or operate on the hardware shown in FIG. Thus, the signs are similar, the XfrRw (ie, transfer-row) line carries the XfrRw signal and the input line 28 carries the input data signal.

The top row of FIG. 4A shows the program clock (PrgClk) pulse. Pr
At each rising edge of the gClk pulse, the time period T _p begins. Therefore, the time period T _p spans between rising edges of the PrgClk pulse.

Each time the PrgClk signal falls, new data (Input_0, Input_1, ..., Input_
p-2, and Input_p-1) are provided at input 28. Each time PrgClk goes high, the data (Input_0, Input_1, ..., Input_p-2, and Input_p-1) is loaded into stage 31. Input line 28 continuously loads data (input signal) and shifts it from stage 31 to stage 31 until the entire array is loaded.

To make efficient use of time, each input line 28 loads an associated shift register 30 having k stages 31, as described in connection with FIG. Therefore, after k PrgClk signals, each input line 28 has completed loading k stages 31. It should be noted that FIG. 4A shows only four input signals associated with the four input lines 28 for clarity. However,
As will be appreciated by those skilled in the art, the present invention involves an appropriate number of input signals corresponding to the associated input lines 28 which provide signals to the row loader 18.

When all input signals are loaded into stage 31, the row transfer (XfrRw) signal (FIG. 4B) releases the connection from the row that has completed programming and moves to the next row designated for programming. Connect with. The XfrRw signal is preferably an externally controlled signal.

The row load (LdRw) line then issues the LdRw signal which enables the buffer 32 during programming. As shown in FIG. 4B, when the XfrRw signal releases row i-1 for loading, row L-1 is loaded by the LdRw signal.

Shown at the same time as the LdRw signal are the ColPrg_j signal, the RwAdr signal, and the RwPrg signal. The ColPrg signal is the data sent to the particular row via the buffer 32. The ColPrg signal contains data that specifies the program instruction for the associated column. That is, the ColPrg_j signal contains programming instructions for column j.

The RwAdr signal contains the address of the row to be loaded, allowing the data to be loaded into the appropriate row. The RwPrg signal contains data that specifies the program instruction for the appropriate associated line.

As mentioned above, the array 10 is configured as a matrix of columns and rows. Row loader 18 loads the data into the selected row and programming information is sent to all columns that block that row. Therefore, the affected unit cell 12 is a pixel in the selected row.

Referring to FIG. 5, a timing diagram for one programming sequence for the entire array 10 is shown. The top row of FIG. 5 shows a Prg signal that remains high for a time T _prg that is a composite of multiple times T _LdRW as defined in connection with FIG. 3 and Equation 13. T _prg is the time required for one programming sequence for the entire array 10.

When the series of XfrRw signals goes high, it releases the series of rows to be programmed. Simultaneously with the falling edge of each XfrRw signal, the associated LdRw signal goes high. Therefore, when the XfrRw signal releases row 0, the LdRw signal 0 goes high, which causes row 0
Is ready to receive the line register data.

With each start of the LdRw signal, all ColPrg and RwAdr signals change state,
Perform the appropriate task as described in.

As shown in FIG. 5, when the LdRw signal for a particular row goes high, only the RwPrg signal for the row associated with that particular row goes high. Therefore, RwPrg_0 starts programming row 0 at the same time as the rising edge of the LdRw_0 signal, and RwPrg_1 starts programming row 1 at the same time as the rising edge of the LdRw_1 signal. So line 0
The row programming progression from row to row V-1 can be seen in FIG.

The Int signal (bottom row of FIG. 5) is low during the programming sequence, disabling charge integration. Therefore, no integration takes place during the programming sequence and execution of programming is enabled without interfering with the integration process.

Referring to FIG. 6, a timing diagram of the programming and integration sequence of array 10 is shown. The array 10 is programmed and integrated q times, but the entire array 10 is programmed before each integration sub-period Tq.

As shown in FIG. 6, each programming sequence is followed by an integration sub-period. In the preferred embodiment of the present invention, the integral sub-period is halved every cycle and the second integral sub-period T _q-2 is half the first integral sub-period T _q-1 .

Each unit cell 12 performs an integration dominated by a unique set of u _m programming coefficients, defined by the coefficient vector (u _q-1 u _q-2 ... u ₂ u ₁ u ₀ ) ₂ . . The programming factor u _m defines the integrating or non-integrating state for each preprogrammed integration sub-period: integration is performed when u _m is high (1) and integration is performed when u _m is low. Do not be discouraged.

Therefore, the total integration time T is determined by the programming coefficient u _m and the basic time integration unit T ₀ , as shown in equation (6). Therefore, each unit cell 1
2 undergoes a unique and independently defined charge integration, ie charge integration time.

As shown in FIG. 6, when the Rst signal goes high, a single frame of programming / integration / readout is initiated. The first array programming cycle follows immediately after the Rst signal.

During the first charge integration, the highest programming coefficient u _{q−1, i, j} is programmed in each unit cell 12. The first array programming is followed by charge integration for the entire array 10. As described in patent application PCT / 1L00 / 00129, for unit cells 12 with multiple charge integration sub-periods, u _{q-1, i, j} =
In the case of 1, the unit cell 12 (i, j) performs charge integration during the time T _q−1 = 2 ^q−1 · T ₀ . However, when u _{q−1, i, j} = 0, integration is not performed in the unit cell 12 in this charge integration step. This cycle is followed by another cycle. This next cycle also begins with programming the entire array, but this time with the u _{q-2, i, j} coefficients. This is followed by another charge integration step, but this time for a time T _q-2 = 2 ^q-2 · T ₀ .

The sub-period charge integration continues until the last charge integration, where the array is programmed by the coefficients u _{0, i, j} such that the shortest integration T = T ₀ . At each charge integration, additional charge is accumulated in the integrating capacitor and held until the next charge integration. Effectively, the integration time for each pixel is different and is dominated by the programming factor u _m as defined by equation (6).

It should be noted that although the integration sub-period T _m here varies from the longest to the shortest, other variants of the timing schedule are possible and within the scope of the invention.

The programming / integration time is followed by the readout of the image sensor array.
The T total integration time, read time of the image sensor array T _Rd, T _{P rg} total programming time, time assigned T _FR in a single frame, and when the number of program / integration cycles q , (16) T _FR = T + q · T _Prg + T _Rd .

Example 5 : For the image sensor described in Examples 3 and 4, the number of program / integral cycles q = 10; T _Rd = 8 msec for reading the image sensor; T for integration
= 23.31 msec; T _prg from Example 4 is 202.39632 μsec. Since the frame rate for moving video is 30 frames per second, T _FR = 33.333 msec.
The time consumed by 10 program cycles is 2.023 msec.
Then, the following relationship holds: 33.333 msec = 23.31 msec + 10202.39632 μsec + 8 msec Since there are 10 integrations, 1023 different charge integration values that increase stepwise in 23.31 msec or less are possible.

From the above examples, it can be seen that each pixel can be independently programmed with a wide range of charge storage times programmed in time increments.
This is effective in capturing a wide dynamic range scene and is important in reducing quantization noise. The time consumed by programming can be designed short enough to have little effect on the maximum integration time.

Another useful aspect of the invention is the wide charge integration time dynamic range (DR _T ).
Is. The charge integration time dynamic range (DR _T ) is

[0154]

[Equation 16]

If (where T is the total integration time and T ₀ is the basic time integration unit), the following equation is obtained.

[0156]

[Equation 17]

[0157] If q >> 1, the following equation is obtained.

[0158]

[Equation 18]

[0159] integration time dynamic range DR _T parameter is one of characteristics as a key in order to achieve high dynamic range artificial retina. The wider the program load bus and / or the faster the program clock, the more programs /
Integral cycles are possible and thus a wider integration time dynamic range can be obtained.

In this manner, the array 10 is constructed and operated according to the embodiment of the present invention.
Provides multiple programming and charge integration sub-periods within a single integration time (or equivalently within a single frame). The presented example consisting of a circuit operating at a program clock of about 60 MHz is a state-of-the-art CMO.
It can be realized by S technology. However, care must be taken to eliminate the effect that the program clock can have on signal noise. The circuitry is carefully isolated and disconnected from the array as it is programmed through the row program loader 18 which is external to the array 10. For example, line program loader 18
Providing a suitable guard ring around the placement of the can be useful in achieving this end.

Interlaced Image Sensor TV type image sensors normally operate in interlaced mode. In interlaced mode, the frame output is split into two fields. In the first field period, lines 0, 2, 4 ,. ． ． Is read. In the second field period, lines 1, 3, 5 ,. ． ． Is read. Readout timing is TV
Aligned with the timing of the format (NTSC or PAL format). In the interlaced image sensor, a program / integrate cycle is performed for one field while reading is performed for the other field.

Referring to FIGS. 7 and 8, the interlaced CMOS image sensor array 5
Various aspects of implementing independent / per-pixel charge integration control for zero are shown.

FIG. 7 is a block diagram of the image sensor array 50. FIG. 8 shows a unit cell 52 used in the array 50. Elements that are similar to array 10 are similarly numbered and will not be described further.

In the preferred embodiment, the image sensor array 50 has H ColPrg / ColSense columns and V RwPrg / RwRd lines (rows), where V is an odd number. The programming of the odd ColPrg lines is preferably done at the same time as the reading of the even ColSense lines.

Therefore, for this preferred implementation, the unit cell 52 requires the ColPrg line to be separated from the ColSense line.

However, other aspects of the unit cell 52 are similar to the unit cell 12 and will not be described further.

The image sensor array 50 includes two row program / readout decoders 16E,
16D is included. One line decoder controls the reading while the other controls the programming.

The row program / read decoder 16E controls even-numbered read (RwRd) and program (RwPrg) lines. During the read cycle, the decoder 16E generates even-numbered RwRd lines (RwRd_0, RwRd_2, RwRd_4, RwRd_6 ....). In the program / integrate cycle, the decoder 16E has an even-numbered RwPrg line (RwPrg_0,
RwPrg_2, RwPrg_4, RwPrg_6 ....) is generated.

The decoder 16E operates by a plurality of signals, that is, read-even (RdEve).
n) signal and program-even (PrgEven) signal. When the RdEven signal is low and the PrgEven signal is high, the unit cell 52 on the even numbered RwPrg line is activated. Even RdRw when RdEven is high and PrgEven is low
The unit cell 52 on the line is activated. When both RdEven and PrgEven are low, the RwRd and RwPrg lines from decoder 16E are all low and therefore inactive.

The row program / read decoder 16D controls the odd-numbered read and program lines. During the read cycle, the decoder 16D produces odd read lines (RwRd_1, RwRd_3, RwRd_5, RwRd_7 ....). In the program / integrate cycle, the decoder 16D outputs the odd-numbered program lines (RwPrg_1, RwPrg_3,
RwPrg_5, RwPrg_7 ....) is generated.

The operation of the decoder 16 is controlled by a plurality of signals, that is, an odd-number read (read-odd: RdOdd) signal and an odd-number program (program-odd: PrgOdd) signal. RdOdd
Unit cell 52 on odd RwPrg line when signal is low and PrgOdd signal is high
Is activated. When RdOdd is high and PrgOdd is low, the unit cell 52 on the odd RdRw line is activated. Decoder 1 when both RdOdd and PrgOdd are low
The RwRd and RwPrg lines from 6D are all low and therefore inactive.

In the preferred embodiment, the RdEven signal is of opposite polarity to the RdOdd signal and the PrgEven signal is Pr.
It has the opposite polarity to the gOdd signal. However, in this example all RwRd lines and
Note that all lines have the same polarity when the RwPrg line is deactivated. Thus, when the decoder 16E produces an even program control signal, the decoder 16D produces an odd read control signal and vice versa.

To be consistent with the interlaced embodiment of the present invention, the read circuit 14 alternately reads the unit cells 52 on the even and odd RwRd lines. Preferably, the unit cells 52 on the even-numbered RwRd lines are read first, and then the unit cells 52 on the odd-numbered RwRd lines are read.

Since the program / integration cycle for the even-numbered unit cells 52 is performed at the same time as the reading of the odd-numbered unit cells 52 (and vice versa), the Rst signal and the Int signal are separated for the even field and the odd field. Is preferred.

Accordingly, the integral-even (IntEven) signal activates the integration of the unit cell 52 on the even-numbered Int line. The IntEven signal is inactivated during reading of the unit cell 52 on the even-numbered RwRd lines.

Further, an even reset (reset-even: RstEven) signal activates the reset of the unit cell 52 on the even-numbered Rst line. The Rst signal is inactivated during reading of the unit cells 52 on the even-numbered RwRd lines.

Odd integration (integrate-odd: IntOdd) signal and odd reset (reset-odd: RstO)
The dd) signal performs a similar function to the unit cells 52 on the odd numbered lines.

Referring to FIG. 9, a row program loader 58 is shown. Also shown in FIG. 10 is a timing diagram illustrating use of loader 58 in single row programming. FIG. 11 is a timing diagram of even field line programming. The same elements as those in the above-described embodiment are designated by the same reference numerals, and description thereof will be omitted below.

The flow shown in FIG. 9 is similar to the flow shown in FIG. 3 and functions as described above in connection with FIG. However, the unit cell 52 is a separate ColPrg
Note that we have a line and a ColSense line, so the three states are not needed and are not shown in FIG.

Further, the timings shown in FIGS. 10 and 11 are the same as those shown in FIGS. 4 and 5, respectively, and the same functions as those described above with reference to these figures are performed.

However, while FIG. 11 illustrates both the PrgEven signal and the PrgOdd signal, FIG. 5 illustrates only the Prg signal. But when the PrgEven signal is high
Since the PrgOdd signal is low and vice versa, a suitable high signal (PrgEven signal) functions similarly to the Prg signal as shown in FIG. 5 and is applicable to FIG.

Although not shown in FIG. 11, RwPrg lines 0, 2, 4 ,. ． ． Unit cell 5
2 is programmed, RwRd lines 1, 3, 5 ,. ． ． The upper unit cell is read. Immediately after programming the unit cells 52 of the even-numbered RwPrg lines, the IntEven signal goes high and charge integration in the even-row unit cells 52 begins. However, since IntOdd stays low, no charge integration is done in the odd row unit cells.

The programming cycle for each of the TPrg cycles is halved, whether even or odd, because only half the rows are programmed. That is, (18) T _Prg = Intg (V / 2 + 1) · Intg (H / p + 1) · T _{p The} programming cycle for an odd row field is similar to that for an even row field. Even if the total number of lines is odd, it takes a little shorter time because there is only one line to program.

Example 6 An interlaced readout image sensor is applied in the case described in Examples 3 and 4. Based on equation (20), it takes 101.40768 μsec to program the even row fields of the array.

Referring to FIG. 12, a timing diagram of the programming and integration cycle of array 50 for interlaced read is shown. It will be noted that the even and odd fields are programmed alternately before and after each other.

The charge integration of the even row fields is initiated by RstEven which discharges the integrating capacitors in the even row unit cells 52. Then, the even-row field unit cell 52
Undergoes q program / integral cycles. These cycles are, in principle,
Same as described above for the non-interlaced image sensor array 10,
It will not be detailed here.

In this particular case, even field programming is done in one field time and reading is done in the other. Therefore, (19) T _FL = T + _{qT Prg,} where T _FL is the field time.

Example 7 : An image sensor similar to that described in Examples 3 and 5, but of the interlaced read type is subjected to 10 program / integrate cycles. The frame rate is 30 frames per second and the field rate is 60 fields per second. In this case, T _FL = 16.666 msec, the time required for 10 program cycles is 1.014 msec, leaving 15.652 msec for integration. Since there are 10 cycles, 1023 different charge integrations are possible in 15.652 msec steps.

Although the active signal is high and the inactive signal is low in the above description, it will be apparent to those skilled in the art that reverse polarities and components are applicable and are included in the scope of the present invention.

The methods and apparatus disclosed above have been described in terms of particular hardware and software. However, these methods and apparatus are readily apparent to one of ordinary skill in the art using conventional techniques, without the need for independent experimentation with embodiments of the invention using commercially available hardware and software. It is fully explained to the extent practicable.

[Brief description of drawings]

FIG. 1 is a schematic diagram of an image sensor array structure for implementing non-interlaced video constructed and operative in accordance with a preferred embodiment of the present invention.

FIG. 2 is a schematic diagram showing an image sensor unit cell providing a plurality of integrating sub-periods for use with the structure shown in FIG.

FIG. 3 is a schematic diagram of a row program loader used in the structure shown in FIG. 1 constructed and operative in accordance with a preferred embodiment of the present invention.

FIG. 4A is a timing diagram for a single row programming as implemented using the structure shown in FIG.

FIG. 4B is a timing diagram for one row programming when implemented using the structure shown in FIG. 1.

FIG. 5 is a timing diagram of a programming sequence implemented in the structure shown in FIG.

FIG. 6 is a timing diagram of programming / integration intervals that function with the structure shown in FIG.

FIG. 7 is a schematic diagram of an image sensor array structure for implementation on interlaced video constructed and operative in accordance with an alternative preferred embodiment of the present invention.

FIG. 8 is a schematic diagram of an alternative image sensor used with the structure shown in FIG. 7 to provide multiple integrating sub-periods.

FIG. 9 is a schematic diagram of a row program loader used in the structure shown in FIG. 7 constructed and operative in accordance with an alternative preferred embodiment of the present invention.

10A is a timing diagram for single row programming implemented with the structure of FIG. 7. FIG.

10B is a timing diagram for single row programming implemented in the structure of FIG. 7. FIG.

FIG. 11   FIG. 8 is a timing diagram of even row programming implemented in the structure of FIG. 7.

12 is a timing diagram of interlaced read, program and integrate cycles implemented with the structure of FIG. 7. FIG.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG , ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, C A, CH, CN, CR, CU, CZ, DE, DK, DM , DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, K E, KG, KP, KR, KZ, LC, LK, LR, LS , LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, R U, SD, SE, SG, SI, SK, SL, TJ, TM , TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW F-term (reference) 4M118 AA02 AB01 BA14 DB03 DB09                       DD12 FA06                 5C024 CX43 GY31 HX31 HX35 HX55                       JX11 JX14

Claims (30)

[Claims] 1. A sensor array for generating an image captured at the end of a time frame, the unit cells for detecting the image by a plurality of in-frame charge integrations, and each of the unit cells individually. And a control means for controlling the sensor array. 2. The charge integration is a capacitor discharge.
The sensor array described in 1 .. 3. The sensor array of claim 1, wherein the unit cell is a programmable multiple charge integration unit cell having photocurrent integration and non-integration states. 4. The control means includes means for individually controlling charge integration of a plurality of times in a single frame capture of each unit cell, independently of charge integration of other cells. The sensor array according to claim 1, wherein: 5. The control means includes means for integrating, in each of the single frame captures, the charge of each of the unit cells included in the predetermined group of cells at approximately the same time and individually. The sensor array according to claim 1, wherein the sensor array comprises: 6. The control means includes a row selection line for transmitting a plurality of first signals to the unit cell, and a column selection line for transmitting a plurality of second signals to the unit cell, The sensor array of claim 1, wherein the second signal includes a program signal and a sense signal. 7. The sensor array of claim 1, wherein the control means includes means for programming the unit cell. 8. The sensor array of claim 7, wherein the means for programming includes means for programming a given group of cells at substantially the same time. 9. The sensor array of claim 8, wherein the group of cells is a line of cells. 10. The sensor array of claim 9, wherein the means for programming comprises means for sequentially programming the lines of cells. 11. The sensor array of claim 9, wherein the means for programming includes means for sequentially programming one or more of the lines containing the plurality of unit cells. 12. The sensor array of claim 4, wherein the control means includes means for providing N (N is 1 or more) charge integration sub-periods within the single frame capture. 13. The sensor array of claim 12, wherein the control means includes means for defining the charge integration sub-period. 14. The sensor array of claim 12, wherein the charge integration sub-periods have different lengths of time. 15. The sensor array according to claim 1, wherein said control means includes means for providing fine time resolution in clock time units. 16. The sensor array of claim 1, wherein the control means includes means for providing a wide dynamic range charge integration step. 17. The sensor array of claim 16, wherein the dynamic range is in the range of 2 ^N −1 integration time unit steps. 18. Each of the unit cells includes a photodetector, a charge storage element for storing charges from the photodetector, and a programmable memory for storing a charge integration state of the unit cell. The sensor array according to claim 1, comprising: 19. A method for detecting an image using a plurality of unit cells, comprising the steps of individually accessing each of the unit cells, calculating the charge integral of each unit cell, and calculating the charge integral of another unit cell. And a control process independent of integration. 20. The method according to claim 19, further comprising determining a charge integration time for each unit cell, and programming each unit cell based on the determined charge integration time. The method described in. 21. A method for improving an intra-scene dynamic range of an image sensor array including a plurality of unit cells, the process of individually accessing each of the unit cells, and controlling each unit cell individually. A method comprising the steps of: 22. The method of claim 21, wherein the individually controlling step comprises individually controlling a charge integration time of each of the unit cells. 23. The method of claim 21, wherein the step of individually controlling the charge integration time includes the step of individually programming each unit cell. 24. The method of claim 23, wherein the step of individually programming each unit cell includes the step of programming each unit cell based on a predetermined charge integration time. 25. The method of claim 23, wherein individually programming each unit cell comprises programming each unit cell with multiple charge integration sub-periods. 26. A method for improving an intra-scene dynamic range of an image sensor array including a plurality of unit cells, the method comprising: individually accessing each of the unit cells; A method comprising: programming, and individually controlling charge integration of the unit cells, wherein the accessing, programming and controlling steps are performed at a video rate. 27. A programmable image sensor including a plurality of unit cells for capturing an image, the first plurality (P) of input lines for carrying data, and the programmable image sensor connected to the cells. A second plurality (H) of columns (where P is less than or equal to H) and receives the data to program the array N times within a single frame of motion video; A programmable image sensor for selectively distributing the received data to the columns. 28. The programmable image sensor according to claim 27, wherein the data is programming data. 29. The programmable image sensor of claim 28, wherein the programming data comprises charge integrated / non-integrated state data for each of the plurality of unit cells. 30. The programmable image sensor of claim 28, wherein each of the plurality of programmable unit cells is individually controlled.