JP4355909B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor element in which one end face of a mesa-like pn junction or pin junction is formed by cleavage, and a method for manufacturing the same.

  A semiconductor element in which a pn junction layer or a pin junction layer is formed in a mesa shape is known (see, for example, Patent Document 1). Examples of this type of semiconductor element include a semiconductor light receiving element represented by a pn photodiode and a pin photodiode. Taking a pin photodiode as an example, its structure will be briefly described below.

  A pin photodiode has a p-type, i-type, and n-type junction layer (pin junction layer) formed by introducing impurities on a semiconductor substrate. These p-type layer, i-type layer, and n-type layer are divided into a clad layer, a light absorption layer, and a contact layer according to their functions. A portion where an electric field is applied when a voltage is applied to operate as a diode is called a depletion layer. The light absorption layer is formed of a semiconductor material having a sufficiently small band gap as compared with the energy of light to be received, and is often disposed in a portion to which an electric field is applied (= depletion layer). The pin junction layer is formed in a mesa shape having a predetermined size, and the entire mesa is covered with a protective film made of an insulating material. The p-type layer and the n-type layer are electrically separated from each other, and p and n electrodes are formed in each layer. In the pin photodiode having such a configuration, when an appropriate voltage is applied, a pair of electrons and holes is generated by light incident on the light absorption layer. Then, the generated electrons and holes move to the n-type layer and the p-type layer, respectively, and are taken out as photocurrents through the n-electrode and the p-electrode.

  The semiconductor light receiving element having the mesa structure as described above includes a surface incident type in which light is incident on the bonding layer from a direction perpendicular to the substrate surface, and a waveguide in which light is incident on the bonding layer from a direction parallel to the substrate surface. Broadly divided into types. The waveguide type light receiving element is further divided into an end face cleavage formation type and a non-end face cleavage formation type. Usually, in the manufacture of semiconductor light-receiving elements, a cleavage process is performed in which a wafer with a cut of a cleavage line (scribe line) is divided into bars (primary cleavage) and further divided into chips (secondary cleavage). It passes. A chip having a pn junction, a pin junction, or a depletion layer in the cleaved end face of the chip thus cleaved is called an end face cleave formation type, and a chip other than that is called a non-end face cleave formation type.

  Hereinafter, the structure of a conventional end face cleavage type semiconductor light-receiving element will be described with reference to FIGS. FIG. 5 is a cross-sectional structure diagram of a conventional edge-cleavage type semiconductor light-receiving element, and FIG. 6 is a plan view showing a part of a bar-shaped substrate before secondary cleavage. FIG. 7 is a perspective view of the bar-shaped substrate shown in FIG.

  As shown in FIG. 5, in the conventional semiconductor light receiving element, a pin junction layer in which an n-type layer 2, an i-type layer 3, and a p-type layer 4 are sequentially formed on a semiconductor substrate 1 is formed in a mesa shape by a known etching process. It has a structure. The mesa portion has a two-stage structure of mesa portions 100 and 101. The mesa portion 101 is provided to insulate the n-type layer 2 (n electrode) from the peripheral portion, and is a portion where the n-type layer 2 is left in a square shape when viewed from the top surface of the substrate. . The surface of the n-type layer 2 is almost flat. The mesa unit 100 is a light receiving unit including a pin junction layer (or a depletion layer) composed of the n-type layer 2, the i-type layer 3, and the p-type layer 4, and is located at the approximate center of the mesa unit 101. These mesa portions 100 and 101 are covered with the insulator film 5. A part of the surface of the p-type layer 4 and a part of the surface of the n-type layer 2 are exposed, and a p-electrode 6a and an n-electrode 6b are formed on these exposed surfaces, respectively.

  The semiconductor light receiving element (chip) having the structure shown in FIG. 5 is manufactured by cleaving the bar-shaped substrate 200 as shown in FIGS. The bar-shaped substrate 200 is configured to be divided into two chip portions 201 and 202 with a cleavage line A-A ′ as a boundary. In the central portion on the bar-shaped substrate 200, the mesa portions 100 and 101 shown in FIG. 5 are formed so as to straddle the chip portions 201 and 202, and further along the cleavage line AA ′ so as to sandwich this. A cleavage V-groove 103 is provided. In FIG. 6, the insulating film forming region 104 indicated by hatching is a range where the insulating film 5 shown in FIG. 5 can be formed.

  The bar-shaped substrate 200 is cleaved along the cleavage V-groove 103 to be divided into two chip portions 201 and 202. These chip portions have the cross-sectional structure shown in FIG. 5 at the cleavage end face. Thus, two semiconductor light receiving elements having the same structure are obtained from one bar-shaped substrate. Note that a protective film made of a dielectric film or the like is usually provided on the cleavage end face where the pin junction layer (depletion layer) is exposed to the outside by cleavage.

As the end face cleavage type semiconductor light receiving element having the above-described structure, for example, there are those described in Non-Patent Documents 1 and 2.
JP 2002-324911 A “10 Gbit / s high sensitivity, low-voltage-operation avalanche photodiodes withth in InAlAS multiplication layer and waveguide structure” Nakata, T .; Takeuchi, T.; Watanabe, I; Makita, K .; Torikai, T.; Electronics letters , Vol. 36, pp.2033-2034, 24, 24 Nov. 2000 "Waveguide photodiodes for 2.5-40 Gbps applications" Takeuchi, T .; Nakata, T .; Makita, K .; Tachigori, M .; Fukuchi, K .; Taguchi, K .; Lasers and Electro-Optics Society 1999 12th Annual Meeting LEOS '99. IEEE, Vol. 2, pp.870-871, 8-11 Nov. 1999

  However, the conventional end face cleavage type semiconductor light receiving element described above has the following problems.

  The mesa portion 100 is deformed (strain stress) so as to be bent at a portion corresponding to a cleavage line A-A ′ below the mesa portion 100 as a fulcrum. It has been obtained from the analysis results so far that such strain stress is one of the causes of the characteristic deterioration of the element. In particular, in an element in which the ratio of the height Mh to the width Mw (Mh / Mw) of the mesa unit 100 shown in FIG. 5 is large, the strain stress at the time of cleavage increases, so that the influence on the element characteristics by cleavage is larger. It will be a thing.

It is conceivable to reduce the strain stress that the mesa unit 100 receives during cleavage by increasing the thickness of the insulating film covering the mesa unit. However, since an insulating film needs to be formed under film-forming conditions that place importance on the insulating characteristics such as good electrical insulating characteristics and good bonding interface with a semiconductor for that purpose, In this case, SiO ₂ or SiN _x is used as the material. When a thick insulating film is formed by using these SiO ₂ and SiN _x under film forming conditions that place importance on insulating characteristics, the insulating film itself is cracked or peeled off due to the strain stress at the time of cleavage. In particular, when the ratio of the mesa height to the mesa width (Mh / Mw) is large, such a crack or peeling of the insulating film is likely to occur. As described above, it is very difficult to reduce the strain stress received by the mesa unit 100 by increasing the thickness of the normally used insulating film, and the deterioration of the characteristics of the element due to cleavage is inevitable. Experimentally, when an insulating film made of SiN _x is formed with a thickness of 300 nm under the condition of Mh / Mw ≧ 0.1, the element is estimated to be caused by an increase in internal crystal defects due to cleavage. As the characteristic deterioration, an increase in dark current was observed in the IV characteristics of the device.

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the above-described problems and can reduce deterioration of device characteristics due to cleavage.

  In order to achieve the above object, the semiconductor device and the manufacturing method of the present invention are mainly provided with a reinforcing film for reinforcing the strength against cleavage of the mesa joint on the insulating film covering the mesa joint. Features. Since the strength against cleavage at the mesa joint is increased by providing the reinforcing film, the strain stress received by the mesa joint at the time of cleavage is smaller than the conventional one, and the characteristic deterioration of the element due to the cleavage is lower than the conventional one. Reduce.

  Further, in the semiconductor element and the manufacturing method of the present invention, the reinforcing film is provided along the edge at a position separated from the edge on the cleaved end face side of the mesa joint by a predetermined distance. Further features. With such a configuration, the strength of the mesa-shaped joint on the wall open line is lower than that of other portions, and as a result, the stress in cleavage is concentrated in the vicinity of the cleaved portion of the mesa-shaped joint. As a result, it is possible to perform cleavage with a smaller force, and the influence (damage) on the element characteristics due to cleavage is smaller.

  As described above, according to the present invention, deterioration of element characteristics due to cleavage can be reduced, so that a semiconductor element excellent in reliability and stability can be provided.

  In addition, since the probability of device characteristic deterioration can be reduced, the yield in the device manufacturing process can be improved.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 shows a cross-sectional structure of a cleaved portion of the semiconductor light receiving element according to the first embodiment of the present invention. This semiconductor light receiving element has basically the same configuration as that shown in FIG. 5 except that the reinforcing film 7 is provided on the insulating film 5 so as to cover the mesa portion 100. Providing this reinforcing film 7 increases the strength of the mesa unit 100, thereby reducing the strain stress received by the mesa unit 100 during cleavage.

  Hereinafter, a specific structure of the semiconductor light receiving element of this embodiment will be described together with a manufacturing procedure thereof. In the following description, the effect of reinforcing the mesa unit 100 by the insulating film 5 and the reinforcing film 7 is the thickness of the mesa unit 101 on the flat part (the surface of the n-type layer 2) in the film forming process. However, since the thickness at the side wall of the mesa portion 100 is limited, the film forming conditions at the flat portion will be mainly described.

  First, an n-type layer 2, an i-type layer 3, and a p-type layer 4 are sequentially formed on a Si substrate that is a semiconductor substrate 1, and these layers are processed into a mesa shape having a predetermined size by a known etching process. Thus, the mesa parts 100 and 101 are obtained. The mesa unit 100 is formed so that Mα ≧ 0.1, where Mα (= Mh / Mw) is the ratio of the height Mh to the width Mw.

Next, the insulator film 5 is provided so as to cover the mesa portions 100 and 101. This insulator film 5 is a passivation film made of, for example, a dielectric film, a resin film, or the like, and is formed under film forming conditions that place importance on the above-described insulating characteristics. Specifically, when the insulator film 5 is formed of SiN or SiO ₂ , the insulator film 5 has a thickness Dh on the flat portion (the surface of the n-type layer 2) of the mesa portion 101.
10 nm ≦ Dh ≦ 300 nm
The thickness Ds at the side wall portion of the mesa 100 is
Ds <Dh
It is formed to satisfy the following conditions. Here, it is assumed that the film is formed under a film forming condition in which the thickness Ds is about Dh / 2, but the value is not particularly limited, and is appropriately changed depending on a mesa shape, a film material, a film forming apparatus, and the like. . The range of the thickness Ds is, for example, a range of Dh × (1/4 to 2/3). Since the insulating film 5 formed in this way has a structure that places importance on insulating characteristics, the strength reinforcing effect of the mesa portion 100 is small. Therefore, only the insulator film 5 cannot suppress the deterioration of the element characteristics due to cleavage.

Next, the reinforcing film 7 is formed on the insulator film 5 so as to cover the mesa unit 100. Here, the formation range of the reinforcing film 7 is the upper surface and side surfaces of the mesa unit 100 and the upper surface of the mesa unit 101, but is not limited thereto. The reinforcing film 7 can be formed in any range as long as it does not hinder element formation and can increase the strength of the mesa unit 100 and reduce the strain stress received by the mesa unit 100 during cleavage. There may be. When the width of the flat portion of the reinforcing film 7 is Fw and the thickness is Fd, the width Fw is
Fw ≧ 5 × Fd
It is desirable to satisfy the following conditions. The width Fw may be increased to the entire element width (about 150 μm). Although the film thickness Fd depends on the strength of the material of the film, by setting it to 0.5 μm or more, it is possible to ensure the strength capable of maintaining the element characteristics at the time of cleavage. Further, by setting the film thickness Fd to be 1.0 μm or more, the probability that the characteristics of the element are deteriorated due to cleavage can be further reduced, thereby improving the manufacturing yield. Examples of the material of the reinforcing film 7 include a semiconductor film, a resin film (such as polyimide and thermosetting resin benzocyclobutene (BCB)), and a dielectric film. In particular, when a semiconductor or SiON is used as the film material, the film can be formed with a stable film quality with a film thickness of 0.5 μm or more, which is also effective in this respect.

  Finally, openings were formed in the insulating film 5 and the reinforcing film 7 so that a part of the n-type layer 2 and a part of the p-type layer 4 were exposed, and a p-electrode 6a and an n-electrode 6b were formed in the openings. Thereafter, terminals for connection to the outside of the chip and wirings between the terminals and the electrodes 6a and 6b are formed.

  The above steps are actually performed on the entire chip portion on the wafer. On the wafer, a plurality of mesa portions 100 and 101 shown in FIG. 1 formed over two chips are formed over the entire wafer. FIG. 2 shows a part of the bar-shaped substrate after the primary cleavage (dividing the wafer into bars). In FIG. 2, the insulating film and the electrode are omitted for convenience.

  Referring to FIG. 2, the bar-shaped substrate 20 is configured to be divided into two chip portions 21 and 22 with a cleavage line A-A ′ as a boundary. The mesa portions 100 and 101 shown in FIG. 1 are formed in the central portion on the bar-shaped substrate 20 so as to straddle the cleavage lines AA ′, and further, the cleavage lines A so as to sandwich the mesa portions 100 and 101. A cleavage V-groove 103 is provided along -A ′. In FIG. 2, the reinforcing film forming region 105 indicated by oblique lines is a range where the reinforcing film 7 shown in FIG. 1 can be formed.

  The bar-shaped substrate 20 is cleaved along the cleavage V-groove 103 to be divided into two chip portions 21 and 22 (secondary cleavage). Since the strength of the mesa unit 100 is increased by the reinforcing film 7, the strain stress applied to the mesa unit 100 by the secondary cleavage is smaller than that of the conventional one, and as a result, the deterioration of the element characteristics due to the secondary cleavage is suppressed. can do. The sectional structure of the cleaved end faces of the chip parts 21 and 22 thus divided is the structure shown in FIG. In this way, two semiconductor light receiving elements (actually a plurality of semiconductor light receiving elements) having the same structure are obtained from one bar-shaped substrate. When cleaving, the back surface side of the bar-shaped substrate is usually polished to a thickness that facilitates cleavage. Further, since the pin junction layer (depletion layer) is exposed to the outside by cleavage, a protective film made of a dielectric film or the like is formed on the cleavage end surfaces of the chips 21 and 22.

In the semiconductor light receiving element of the present embodiment described above, when the insulating film 5 and the reinforcing film 7 are each laminated as a single layer, for example, when the insulating film 5 is an SiN _x film, the reinforcing film 7 is an SiO ₂ film. On the contrary, when the insulating film 5 is an SiO ₂ film, the reinforcing film 7 is an SiN _x film, so that strain stress can be reduced in both the insulating film 5 and the reinforcing film 7. Similar combinations include SiN _x / SiON, SiO ₂ / SiON, etc. when written in the order of insulating film / reinforcing film.

Further, the reinforcing film 7 may have a multilayer structure to increase the thickness. An example of such a multilayer structure is SiN _x / SiO ₂ / SiON.

  Compared with the insulating film 5, the reinforcing film 7 has less restrictions on the required film characteristics, particularly the insulating characteristics. Therefore, the film forming conditions can be set in a wider range than the film forming conditions for the insulating film 5. Therefore, the reinforcing film 7 can be easily formed thicker than the insulating film 5. For example, in the multilayer structure as described above, a dielectric film exceeding 1 μm in total can be formed as the reinforcing film 7. A greater reinforcing effect can be obtained by making the reinforcing film thicker, but considering the thickness, shape and size of the element, the thickness is the same as the height of the mesa portion 100 in terms of the total thickness (insulating film + reinforcing film). It is desirable to make it about.

  In addition, the manufacturing procedure mentioned above is an example, The order can be changed suitably. For example, the p-electrode 6a, the n-electrode 6b, the terminal and the wiring may be formed after the insulating film 5 is formed, and then the reinforcing film 7 may be formed. Further, the reinforcing film 7 may be removed after the cleavage step.

(Example)
Examples of the semiconductor light receiving element according to the first embodiment of the present invention will be described below.

First, an n-type layer 2 having a thickness of 2 μm, an i-type layer 3 having a thickness of 0.5 μm, and a p-type layer 4 having a thickness of 2 μm are stacked on the semiconductor substrate 1 in this order. Next, this laminated portion is formed in a mesa shape using a method such as wet etching or dry etching. At this time, the mesa unit 100 is formed so that the height Mh is 5 μm, the width Mw is 3 to 10 μm, and the aspect ratio Mα is 0.1 or more. Thereafter, a SiN film (or SiO ₂ film) to be the insulating film 5 is formed on the entire surface by PCVD or thermal CVD. At this time, the insulating film 5 is formed so that the layer thickness Dh in the flat portion is 250 nm.

  Next, an opening is provided in the insulating film 5 so that a part of the n-type layer 2 and a part of the p-type layer 4 are exposed. After forming the p-electrode 6a and the n-electrode 6b in each opening, gold plating is performed. Then, terminals and wirings for connection to the outside of the chip are formed. Then, a reinforcing film 7 made of SiON is formed so as to cover the mesa unit 100. At this time, the reinforcing film 7 is formed so that the film thickness Fd in the flat portion is 2 μm. When the reinforcing film 7 is formed of SiN, the film thickness Fd is set to 800 nm.

  With the above procedure, the element structure shown in FIG. 1 is formed on each chip portion on the wafer. This wafer is first cleaved to obtain the bar-shaped substrate shown in FIG. 2, and this is further cleaved to be divided into a plurality of chips. Then, a dielectric is deposited on the cleaved end face of the divided chip. This dielectric deposition protects the cleaved end face and prevents reflection of input light.

  When comparing the semiconductor light-receiving element manufactured in this example and a conventional semiconductor light-receiving element not having the reinforcing film 7, in the element of this example, the number of elements that caused a short failure was 5% or less of the total, The number of devices that caused dark current degradation with dark current of 10 nA or more when reverse bias 2 V was applied was 15% or less of the total, whereas in conventional devices, a short failure occurred with a probability of 20% or more. The number of elements that caused dark current deterioration was 30% or more of the whole. As described above, by adopting the structure of this embodiment, it is possible to suppress the occurrence rate of elements that cause a short circuit failure or dark current degradation in the cleavage process compared to the conventional case, and improve the yield of element manufacturing. I was able to.

(Second Embodiment)
In the first embodiment described above, the reinforcement film 7 is formed so as to cover the mesa portions 100 and 101, thereby increasing the overall strength of the mesa portion 100, and thereby the strain received by the mesa portion 100 during cleavage. In the semiconductor light receiving device according to the present embodiment, the stress is reduced, but the mesa portion 100 is reinforced so as to reinforce a portion excluding a region having a predetermined width along the edge on the end face side to be cleaved. A membrane 7 is provided. With this configuration, the strength of the mesa unit 100 on the wall open line is lower than that of other portions, and the stress in cleavage is concentrated in the vicinity of the cleaved portion of the mesa unit 100. Cleaving begins, and the influence on the device characteristics by cleavage can be made smaller. The manufacturing procedure is basically the same as in the case of the semiconductor light receiving element of the first embodiment described above, and therefore detailed description thereof is omitted here.

  FIG. 3 is a plan view showing a part of a bar-shaped substrate before the secondary cleavage, in which the semiconductor light receiving element of the second embodiment of the present invention is formed, and FIG. 4 is a perspective view thereof. In FIG. 3 and FIG. 4, the insulating film and the electrode are omitted for convenience.

  The bar-shaped substrate 30 has the same structure as the bar-shaped substrate 20 shown in FIG. 2 except that the pattern shape of the reinforcing film forming region 106 is different. The reinforcing film forming region 106 covers both edges along the longitudinal direction of the mesa unit 100 and is formed so as to straddle the mesa unit 100 along the cleavage line AA ′. In the upper part, the upper surface of the mesa unit 100 (in fact, the insulating film 5 exists) is exposed with a predetermined width. Further, the reinforcing film forming region 106 has a symmetrical configuration with respect to the cleavage line AA ′ as a boundary, and a distance d1 from the cleavage line AA ′ to the edge of the reinforcing film forming region 106 on one side. Just away.

The reinforcing film forming region 106 having the above shape is:
(1) A method of selecting a photosensitive material as a resin material and forming a pattern by development processing;
(2) A method of applying a pattern forming process by dry etching after patterning a resist, a dielectric film or the like on the resin upper surface after applying or vapor-depositing a resin film;
Such a method can be appropriately employed to remove the resin film on the cleavage line.

  In the above-described embodiment, since the strength of the mesa portion can be lowered on the cleavage line, the cleavage can be easily performed with less force. In addition, there are the following effects.

  In the case of using a resin as the material of the reinforcing film in the case of having a reinforcing film on the cleavage line AA ′ as in the first embodiment described above, the cleaved end face may be the resin depending on the type of resin. An optically sufficient flat surface may not be obtained at the portion. For this reason, in the light receiving element that optically utilizes the cleaved end face, the element characteristics may deteriorate. On the other hand, as shown in FIG. 3, in the case where the reinforcing film is not provided on the cleavage line AA ′, since the reinforcing film (resin portion) is not included in the cleavage end surface, optically. A cleaved end surface having a sufficiently flat surface can be formed. Therefore, it is possible to avoid deterioration of device characteristics (optical characteristics, appearance, etc.) caused by the cross section of the resin portion not being optically flat.

In the present embodiment, it is desirable that the distance d1 be sufficiently smaller than the length d2 of the mesa unit 100 to be cleaved (the distance from the cleaved surface to the portion farthest from the cleaved surface). By doing so, it is possible to easily cleave the mesa unit 100 while maintaining the strength of the mesa unit 100 by the reinforcing film. The distance d1 in this case is about 20% of the length d2 of the mesa unit 100, for example. That is, the distance d1 is
d1 ≦ 0.2 × d2
It is desirable to design such that the above condition is satisfied. However, in consideration of workability, the distance d1 is required to be at least 3 μm. Therefore, for example, when the length d2 is in the range of 10 to 50 μm, it is desirable to design d1 in the range of 3 to 10 μm.

  The configuration of the present embodiment described above is an example, and the configuration can be changed as appropriate. For example, the reinforcing film forming region 106 may have any pattern as long as the strength of the mesa unit 100 and the ease of cleavage described above can be realized. Specifically, in FIG. 3, the reinforcing film forming region 106 may cover the entire region of the mesa unit 100 excluding a predetermined range on the cleavage line A-A ′.

  In the present embodiment, an example in which a resin is used as the reinforcing film has been described. However, in place of the resin, a semiconductor or a dielectric is used, and an effective element can be obtained from both aspects of reinforcement against cleavage and ease of cleavage. Manufacturing is possible. Further, the reinforcing film may be removed after the cleavage step.

(Example)
Examples of the semiconductor light receiving element according to the second embodiment of the present invention will be described below.

First, an n-type layer 2 having a thickness of 2 μm, an i-type layer 3 having a thickness of 0.5 μm, and a p-type layer 4 having a thickness of 2 μm are stacked on the semiconductor substrate 1 in this order. Next, this laminated portion is formed in a mesa shape using a method such as wet etching or dry etching. At this time, the mesa unit 100 is formed so that the height Mh is 5 μm, the width Mw is 3 to 10 μm, and the aspect ratio Mα is 0.1 or more. Thereafter, a SiN film (or SiO ₂ film) to be the insulating film 5 is formed on the entire surface by PCVD or thermal CVD. At this time, the insulating film 5 is formed so that the layer thickness Dh in the flat portion is 250 nm.

  Next, an opening is provided in the insulating film 5 so that a part of the n-type layer 2 and a part of the p-type layer 4 are exposed. After forming the p-electrode 6a and the n-electrode 6b in each opening, gold plating is performed. Then, terminals and wirings for connection to the outside of the chip are formed. Then, a reinforcing film is formed by applying a resin so as to cover the mesa unit 100. At this time, in order to maintain the strength of the reinforcing film, the film thickness Fd in the flat portion after application of the resin (after treatment for those requiring baking) is set to 1.5 μm. Then, the photosensitive resin is used to remove the resin by a distance d1 on both sides from the cleavage line. Thus, a pattern similar to the reinforcing film forming region 106 shown in FIG. 3 is obtained.

  The element structure is formed in each chip portion on the wafer by the procedure as described above. The wafer is first cleaved to form the bar-shaped substrate shown in FIG. 3, and this is further cleaved to be divided into a plurality of chips. Then, a dielectric is deposited on the cleaved end face of the divided chip. This dielectric deposition protects the cleaved end face and prevents reflection of input light.

  Also in the semiconductor light-receiving element manufactured in this example, as in the case of the example of the first embodiment described above, the number of elements that caused a short failure was 5% or less of the whole, and the dark current when a reverse bias of 2 V was applied was The number of elements that caused dark current degradation of 10 nA or more was 15% or less of the total. Therefore, also in the device of this example, it was possible to suppress the occurrence rate of devices causing short circuit failure and dark current degradation in the cleavage process, and to improve the yield of device manufacture.

1 is a cross-sectional structure diagram of a semiconductor light receiving element according to a first embodiment of the present invention. It is a top view which shows a part of bar-shaped board | substrate which has the semiconductor light receiving element shown in FIG. It is a top view which shows a part of bar-shaped board | substrate which has a semiconductor light receiving element which is the 2nd Embodiment of this invention. FIG. 4 is a perspective view of the bar-shaped substrate shown in FIG. 3. It is a cross-sectional structure diagram of a conventional end face cleaving formation type semiconductor light receiving element. It is a top view which shows a part of bar-shaped board | substrate which has the semiconductor light receiving element shown in FIG. It is a perspective view of the bar-shaped board | substrate shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 n-type layer 3 i-type layer 4 p-type layer 5 Insulating film 6a p-electrode 6b n-electrode 7 Reinforcing film 20, 30, 200 Bar-shaped substrate 21, 22 Chip part 100, 101 Mesa part 103 V groove for cleavage 104 Insulating film forming region 105, 106 Reinforcing film forming region

Claims (19)

A semiconductor element having a mesa-like joint part in which a plurality of layers having different conductivity types are stacked on a semiconductor substrate, wherein one end face of the mesa-like joint part is formed by cleavage,
An insulating film covering the mesa joint,
A first film formed on the insulating film and having a composition different from that of the insulating film;
The first film is at least, the a on the insulating film formed on a part of the upper surface of the mesa-shaped junction is formed and on the insulating film formed on the side surface of the mesa-shaped joint cage, the position apart a distance from the edge of the side of a given said cleaved end face of the mesa-shaped joint portion, provided along the edge semiconductor element characterized Rukoto.   2. The semiconductor element according to claim 1, wherein the first film is a reinforcing film for reinforcing strength against the cleavage of the mesa joint.   The semiconductor element according to claim 1, wherein the first film is made of an insulating material.   4. The semiconductor device according to claim 1, wherein the mesa junction is configured such that a ratio of height to width is 0.1 or more. 5.   The mesa junction is formed on a flat portion, the first film is provided so as to cover the mesa junction and the flat portion, and the thickness of the first film on the flat portion is The semiconductor element according to claim 1, wherein is 0.5 μm or more.   The semiconductor element according to claim 1, wherein the first film is made of SiON. 6. The semiconductor device according to claim 1, wherein the insulating film is made of SiO ₂ , and the first film is made of SiON or SiN x. The insulating film is made of SiNx, the first film is made of SiON or SiO _2, the semiconductor device according to any one of claims 1 to 5.   The semiconductor element according to claim 1, wherein the first film is made of a resin. Wherein the predetermined distance is at least 3 [mu] m, the semiconductor device according to any one of claims 1 to 9. A step of forming a mesa-shaped joint in which a plurality of layers having different conductivity types are stacked across two chip regions separated by a cleavage line where cleavage is performed;
Covering the mesa joint with an insulating film;
Forming a first film having a composition different from the composition of the insulating film on the insulating film;
Cleaving two chip regions provided with the first film along the cleavage line,
The first film is formed on at least a part of the upper surface of the mesa-shaped joint and an upper part of the side surface of the mesa-shaped joint , and the cleaved end surface of the mesa-shaped joint A method of manufacturing a semiconductor device , comprising: a predetermined distance from a side edge of the semiconductor element along the edge . The method of manufacturing a semiconductor device according to claim 11 , wherein the first film is a reinforcing film for reinforcing strength against the cleavage of the mesa joint. The first film is a method of manufacturing a semiconductor device according to claim 11 or 12, characterized in that it consists of insulating material. The mesa junction is formed on a flat portion, the first film covers the mesa junction and the flat portion, and the thickness on the flat portion is 0.5 μm or more. providing method as claimed in any one of claims 11 to 13. Using SiON on the first film, The method according to any one of claims 11 to 14. Said SiO ₂ used for the insulating film, the first film using a SiON or SiNx, a method of manufacturing a semiconductor device according to any one of claims 11 to 14. The insulating film using the SiNx on the first film using a SiON or SiO _2, the method of manufacturing a semiconductor device according to any one of claims 11 to 14. A resin in the first layer, The method according to any one of claims 11 to 14. The method for manufacturing a semiconductor element according to claim 11 , wherein the predetermined distance is at least 3 μm.

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