JP2850766B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a light emitting element and a light receiving element.

[0002]

2. Description of the Related Art In recent years, as a technique for separating an input / output interface section and a power supply section of various electronic devices, electrical isolation using a photocoupler is often performed. This photocoupler is a hybrid type in which a light emitting element chip using a compound semiconductor such as GaAs and a light receiving element chip using silicon are incorporated in one package. It is also known that this photocoupler is integrated on one chip to make it monolithic (for example, see Japanese Patent Application Laid-Open No.
No. 6278). Further, in the monolithic photocoupler, the light emitting element side circuit and the light receiving element side circuit may have a dielectric isolation structure. That is, as shown in FIG. 12, the light emitting diode 100 and the phototransistor 1
13, a first island 105 surrounded by a dielectric isolation film 104a and a second island 105 surrounded by a dielectric isolation film 104b are formed on the substrate 103, as shown in FIG. And the island 106 of
The light emitting diode 100 is formed on the first island 105, and the second
The phototransistor 101 is formed on the island 106 and optically coupled by the waveguide forming member 107.

On the other hand, the withstand voltage between the primary side circuit (light emitting element chip) and the secondary side circuit (light receiving element chip) in the hybrid photocoupler needs to be 2500 volts or more, and the same applies to the monolithic photocoupler. Dielectric strength is required. As an example of the test method, as shown in FIG.
There is a method of connecting the cathode and the emitter / collector of the phototransistor 101 to apply a voltage between the light emitting diode 100 and the phototransistor 101. Then, it is necessary to maintain the insulation state even when the applied voltage of 2500 volts or more is applied.

[0004]

However, in order to satisfy the dielectric strength of 2500 volts or more in the monolithic photocoupler, as shown in FIG. In order to prevent dielectric breakdown, the thickness t of the field oxide film (silicon oxide film) 110 on the chip surface must be 3 μm or more. In other words, as shown in FIG. 13, electric field concentration occurs in regions Z1 and Z2 between wiring 109 and substrate 103. Therefore, it is necessary to arrange thick field oxide film 110 in order to prevent dielectric breakdown at these portions. is there. As described above, if the thickness t of the field oxide film 110 is set to 3 μm or more, problems such as warpage of the wafer and increase in cost arise.

An object of the present invention is to provide a semiconductor device in which a photo-coupler is made monolithic, in which a field oxide film for preventing dielectric breakdown between a substrate, a wiring and an electrode can be made thin. It is in.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a substrate; a plurality of islands formed on the substrate and including a semiconductor layer surrounded by a dielectric isolation film; A light emitting element and a light receiving element formed on an island other than the island on which the light emitting element is formed, and a light receiving element optically coupled to the light emitting element by a waveguide forming member. A gist of the present invention is a semiconductor device in which wirings and electrodes for connecting to the outside of the light receiving element are formed only inside the island.

According to a second aspect of the present invention, in the first aspect of the present invention, the dielectric isolation film of the island on which the light emitting element is formed and the dielectric isolation film of the island on which the light receiving element is formed have an area, A gist of the present invention is a semiconductor device whose thickness and dielectric constant are substantially equal.

According to a third aspect of the present invention, a high-concentration diffusion layer is formed in a portion of the semiconductor layer in contact with the dielectric isolation film in the first aspect of the invention, and the high-concentration diffusion layer is formed of the light-emitting element. Alternatively, a gist of the present invention is a semiconductor device connected to any of the wirings or electrodes of the light receiving element.

According to a fourth aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein the island is surrounded by a light confinement layer for preventing light from leaking between the island and the substrate. .

According to a fifth aspect of the present invention, there is provided a semiconductor device in which the island of the first aspect is surrounded by a thermal stress relaxation layer made of a material having substantially the same coefficient of thermal expansion as the island. .

[0011]

According to the first aspect of the present invention, when a high voltage is applied to the light emitting element and the light receiving element through the wiring and the electrode, a high potential difference is generated between the substrate and the wiring and the electrode. Since the electrodes are arranged only inside the island, no electric field concentration occurs outside the island, and the field oxide film formed outside the island may be thin.

According to the invention described in claim 2, according to claim 1,
In addition to the effects of the invention described in the above, the area, thickness, and dielectric constant of the dielectric isolation film on each island are substantially equal, and the capacitance by the dielectric isolation film on each island is equalized, and the dielectric The potential difference is equalized by the body separation membrane. Therefore, the thickness of the dielectric isolation film can be minimized.

According to the third aspect of the present invention, the first aspect is provided.
In addition to the effect of the invention described in the above, a high concentration diffusion layer disposed in a portion of the semiconductor layer in contact with the dielectric separation film is connected to any terminal of the element, and a current path is formed through the high concentration diffusion layer. Thereby, the resistance is reduced.

According to the invention described in claim 4, according to claim 1 of the present invention,
In addition to the effects of the invention described in (1), the island is surrounded by the light confinement layer, and the light is confined in the island by the light confinement layer, so that the light is efficiently used.

According to the invention described in claim 5, according to claim 1,
In addition to the effects of the invention described in (1), the islands are surrounded by the thermal stress relaxation layer, and variations and fluctuations in element characteristics are reduced.

[0016]

【Example】

(First Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A is a plan view of a monolithic photocoupler according to the present embodiment, and FIG.
3A shows an AA cross section. Silicon substrate 1 as base material
A silicon oxide layer 2 is formed on the upper surface of the substrate, and a polysilicon layer 3 is formed thereon. In this embodiment, a substrate is constituted by the silicon substrate 1 and the polysilicon layer 3.

On the upper surface side of the polysilicon layer 3, a recess 4a,
4b are formed, and dielectric isolation films 5a and 5b are formed on the surfaces of the concave portions 4a and 4b. The dielectric separation film 5a,
In this embodiment, a silicon oxide film having a thickness of about 2 μm is used as 5b, and the areas of both dielectric isolation films 5a and 5b are equal. Thus, the dielectric separation films 5a and 5b
Are made of the same material, have the same dielectric constant, and have substantially the same area and thickness.

In the recess 4a, an n-type single crystal silicon island 6 is formed.
a, and an n-type single-crystal silicon island 6b is formed in the recess 4b. The n-type impurity concentration of these single crystal silicon islands 6a and 6b is about 10 ¹⁶ cm ^-3 . Further, the single crystal silicon island 6b becomes a collector region of the phototransistor 18 which is a light receiving element. Here, the single crystal silicon forming the islands 6a and 6b and the polysilicon layer 3 forming the substrate have similar thermal expansion coefficients.

As described above, the space between the two single crystal silicon regions (6a, 6b) surrounded by the dielectric isolation films 5a, 5b is polysilicon (3) which is a material having a thermal expansion coefficient close to that of single crystal silicon. The structure is filled with.

An n-type high-concentration diffusion layer 7a is provided at a portion of the n-type single-crystal silicon island 6a in contact with the dielectric isolation film 5a.
Is formed with a thickness of about 1 μm, and the impurity concentration of the high concentration diffusion layer 7a is about 10 ¹⁹ cm ⁻³ . Similarly, an n-type high-concentration diffusion layer 7b having a thickness of about 1 μm is formed at a portion of the n-type single-crystal silicon island 6b in contact with the dielectric isolation film 5b, and the impurity concentration of the high-concentration diffusion layer 7b is 10 ¹⁹ cm. ^-3
It has become about.

A p-type diffusion region 8 is formed on the surface of the single crystal silicon island 6a, and an n-type diffusion region 9 extends in a band shape on the surface inside the single crystal silicon island 6a. On the p-type diffusion region 8 including the n-type diffusion region 9, n-type Al _x G
a _1-x As layer 10, n-type GaAs layer 11, and p-type GaAs
The layer 12 is laminated.

The n-type Al _x Ga _{1 -x} As layer 10 is made of AlA
It is made of a mixed crystal of s and GaAs, and is formed on the surface of the single crystal silicon island 6a by heteroepitaxial growth by MO-CVD. Here, the ratio x of AlAs
The larger is, the larger the refractive index difference from the n-type GaAs layer 11 is, and the higher the light confinement efficiency is. X is determined in consideration of the crystallinity of the epitaxial film. n-type GaAs
The s layer 11 is formed on the n-type Al _x Ga _{1 -x} As layer 10 by MO-
It is formed by epitaxial growth by a CVD method. Further, the p-type GaAs layer 12 is formed on the n-type GaAs layer 11 by epitaxial growth by MO-CVD. More specifically, n-type Al _x G
a _1-x As layer 10, n-type GaAs layer 11, and p-type GaAs
The layer 12 is continuously grown and patterned into a square shape by photolithography. The etching is performed with a mixed solution of sulfuric acid, a hydrogen peroxide solution, and water.

On the p-type GaAs layer 12 described above, Au-
A Zn electrode 13 is formed, and the Au-Zn electrode 13 is manufactured by a vacuum evaporation method. In this way, n is added to the single crystal silicon island 6a surrounded by the dielectric isolation film 5a.
-Type Al _x Ga _{1 -x} As layer 10, n-type GaAs layer 11, and p-type
A light-emitting diode 14 is formed as a light-emitting element composed of a stacked body with the type GaAs layer 12.

On the other hand, a p-type base region 15 is formed in a predetermined region on the surface of single crystal silicon island 6b, and an n-type emitter region 1
6 are formed. Further, an n-type diffusion region 17 is formed in a predetermined region on the surface of the single crystal silicon island 6b. The n-type emitter region 16, the p-type base region 15, and the n-type single crystal silicon island 6b form a phototransistor 18 having an n / p / n structure as a light receiving element.

As described above, the phototransistor 18 is formed on the single crystal silicon island 6b surrounded by the dielectric isolation film 5b. A field oxide film 19 is formed on the surface of the polysilicon layer 3 including the surfaces of the single crystal silicon islands 6a and 6b.
Is formed, and the field oxide film 19 is formed by thermal oxidation.
It is made of a silicon oxide film of about μm. This field oxide film 19 serves as a cladding layer (light reflecting layer) of an optical waveguide described later.
It has the required thickness. Also, the p-type base region 1
5, a thin silicon oxide film 20 is formed.

On the field oxide film 19, silicon oxide
On film 20 and n-type Al_xGa _1-xAs layer 10 · n
Around stacked body of p-type GaAs layer 11 and p-type GaAs layer 12
A silicon nitride film 21 is formed.
The film 21 is formed by a plasma CVD method and has a thickness of 1
It is about μm. The silicon nitride film 21 is a light emitting device.
It functions as a passivation film for the ions 14.

On the silicon nitride film 21 between the light emitting diode 14 and the phototransistor 18, a titanium oxide layer 22 is formed as a waveguide forming member, and the titanium oxide layer 22 has a thickness of 2 by ion plating. ~
It was formed to about 3 μm. This titanium oxide layer 2
2 causes the phototransistor 18 to
And optically coupled.

An aluminum wiring 23 is formed on the silicon nitride film 21 on the single crystal silicon island 6a.
It extends from the u-Zn electrode 13 in the single crystal silicon island 6a. Aluminum interconnection 24 is formed on silicon nitride film 21 on single crystal silicon island 6a, and aluminum interconnection 24 is electrically connected to n-type diffusion region 9 at contact portion 25 and at the same time contact portion 25 is formed. From the single crystal silicon island 6a. Further, the aluminum wiring 24 is electrically connected to the high concentration diffusion layer 7a through the contact portion 26. That is, the high concentration diffusion layer 7 a is connected to the cathode terminal of the light emitting diode 14.

Aluminum wiring 27 is formed on silicon nitride film 21 on single crystal silicon island 6b. Aluminum wiring 27 is in contact with n-type emitter region 16 and has a contact portion with n-type emitter region 16. From the single crystal silicon island 6b. An aluminum interconnection 28 is formed on silicon nitride film 21 on single crystal silicon island 6b. Aluminum interconnection 28 contacts n-type diffusion region 17 and contacts a single crystal from n-type diffusion region 17. It extends in the silicon island 6b. Further, this aluminum wiring 28 is electrically connected to high-concentration diffusion layer 7b through contact portion 29. That is, the high concentration diffusion layer 7b is connected to the collector terminal of the phototransistor 18.

The surfaces of the light emitting diode 14 and the phototransistor 18 are covered with a silicon oxide film 30. The silicon oxide film 30 is formed by a low pressure CVD method or a sputtering method and has a thickness of about 2 μm. Also, aluminum wiring 23, 2
Portions of the silicon oxide film 30 above the holes 4, 27, 28 are open, and this portion is
32, 33 and 33.

Thus, the aluminum wirings 23, 24, 27, 28 and the Au-Zn electrode 13 for connecting the light emitting diode 14 to the outside of the phototransistor 18 are formed only inside the single crystal silicon islands 6a, 6b. Have been.

Next, an outline of a manufacturing process of the monolithic photocoupler will be described. First, as shown in FIG. 2A, an n-type single crystal silicon substrate 6 having an impurity concentration of about 10 ¹⁶ cm ⁻³ is prepared, and a V groove 35 is formed on the surface thereof.
Then, as shown in FIG. 2B, the surface of the single crystal silicon substrate 6 is doped with n-type impurities by 10 ¹⁹
The high-concentration diffusion layer 7 is formed by diffusing to about cm ⁻³ and a depth of about 1 μm. A dielectric isolation film (silicon oxide film) 5 is formed on the surface by a thermal oxidation method to a thickness of about 2 μm. Subsequently, as shown in FIG.
A polysilicon layer 3 is formed on the substrate 1100 by a normal pressure CVD method.
Formed at about ° C. At this time, the thickness of the polysilicon layer 3 is formed to be two to three times the depth of the single crystal silicon islands 6a and 6b. Thereafter, the surface of the polysilicon layer 3 is mirror-polished.

Further, as shown in FIG. 2D, a mirror-polished silicon substrate 1 is prepared, a silicon oxide layer 2 is formed on the mirror surface, and this surface is directly bonded to the mirror surface of the polysilicon layer 3. . Subsequently, as shown in FIG. 2E, the back surface of the single crystal silicon substrate 6 is polished to separate each island.

Then, as shown in FIG. 1, the light emitting diode 14 and the phototransistor 18 are formed on each island, and the chip and the lead frame are wire-bonded by the bonding pads 31, 32, 33 and 34.

Next, the operation of the monolithic photocoupler thus configured will be described. When a voltage is applied between the anode and cathode of the light emitting diode 14, holes and electrons are injected, and recombine at the junction between the n-type GaAs layer 11 and the p-type GaAs layer 12 to emit light. At this time, since the high concentration diffusion layer 7a is at the cathode potential, the outer peripheral portion of the single crystal silicon island 6a can be made equal in potential.

Light emitted from the light emitting diode 14 reaches the p-type base region 15 in the phototransistor 18 through a titanium oxide layer 22 as a waveguide forming member. Then, the p-type base region 1 in the phototransistor 18
5 and the photocurrent generated at the pn junction in the n-type collector region (n-type single crystal silicon island 6b) is amplified and taken out as a collector and emitter current. At this time, in the phototransistor 18, a current flows between the emitter and the collector through the high concentration diffusion layer 7b, so that the collector resistance can be reduced.

Here, in this embodiment, the light emitting diode 1
4 and the aluminum wirings 23, 24,
27, 28 and the Au-Zn electrode 13 are kept out of the single crystal silicon islands 6a, 6b. Therefore,
When a high voltage is applied between the light emitting diode 14 and the phototransistor 18, the electric field concentration portion is
Since only a and 5b are provided, the withstand voltage of the field oxide film 19 does not need to be considered.

That is, as shown in FIG.
When the high voltage is applied between the light emitting diode 14 and the phototransistor 18, the aluminum wirings 23, 24, 27,
A high potential difference is applied between the gate electrode 28 and the polysilicon layer 3 to cause an electric field concentration in the field oxide film portion 36 below the aluminum wirings 23, 24, 27, 28. Therefore, the field oxide film 36 requires a dielectric breakdown voltage equal to or higher than that of the dielectric isolation films 5a and 5b, and requires 3 μm or more. However, as shown in FIG. 1, the aluminum wirings 23, 24,
27, 28 and the Au-Zn electrode 13 are connected to the islands 6a, 6b
The field oxide film 1 is formed only inside the
Since the above-mentioned potential difference is not applied to the field oxide film 9, only the dielectric separation films 5a and 5b are used as the electric field concentration portions.
9 does not have to be considered.

As shown in FIG. 12, the anode / cathode of the light emitting diode 100 is connected and the emitter / collector of the phototransistor 101 is connected so that the withstand voltage between the light emitting diode 100 and the phototransistor 101 is 2500 volts or more. There is a need to. In this embodiment, the dielectric isolation film 5a of the island 6a on which the light emitting diode 14 is formed and the island 6b on which the phototransistor 18 is formed
The area, thickness, and dielectric constant of the dielectric isolation film 5b are substantially the same. As a result, as shown in FIG. 4, the capacitance C1 on the light emitting diode 14 side and the capacitance C1 on the phototransistor 18 side are obtained.
When the light emitting diode 14 side is set to 0 volts and the phototransistor 18 side is set to 2500 volts, the potential of the polysilicon layer 3 is 1250 volts. Therefore, it is sufficient to secure 1250 volts as the withstand voltage by the dielectric isolation film films 5a and 5b in the both islands 6a and 6b.
The dielectric breakdown voltage at a and 6b becomes uniform. As a result, the thickness of the dielectric isolation films 5a and 5b can be reduced to the minimum.

As described above, in this embodiment, the aluminum wiring 23,
24, 27, 28 and the Au-Zn electrode 13
Since it is formed only inside a and 6b, it is not necessary to consider the withstand voltage of the field oxide film 19, the thickness of the field oxide film 19 can be reduced to about 1 μm, and there is a problem that the wafer is warped and the cost is increased. Can be avoided.

That is, the light emitting diode 14 (light emitting element)
When a high voltage is applied to the phototransistor 18 and the phototransistor 18 (light receiving element) through the aluminum wirings 23, 24, 27, 28 and the Au-Zn electrode 13, the polysilicon layer 3 (substrate) and the aluminum wirings 23, 24, 27, 28 and Au-
Although a high potential difference is generated with the Zn electrode 13, since the aluminum wirings 23, 24, 27, and 28 and the Au-Zn electrode 13 are arranged only inside the islands 6a and 6b, the island 6
Electric field concentration does not occur outside of the islands 6a and 6b.
Field oxide film 19 formed outside of a and 6b may be thin.

The island 6a on which the light emitting diode 14 is formed
Since the area, thickness, and permittivity of the dielectric isolation film 5a of the island 6b on which the phototransistor 18 is formed and the dielectric isolation film 5b of the island 6b are made substantially equal, the dielectric isolation film 5a, 5b Of the dielectric isolation films 5a and 5b can be minimized.

Further, high-concentration diffusion layers 7a and 7b are formed in portions that are in contact with the dielectric isolation films 5a and 5b, and these high-concentration diffusion layers 7a and 7b are connected to any terminal of the element (the light emitting diode 14 or the phototransistor 18). Of the high-concentration diffusion layer 7a,
The resistance is reduced by forming a current path through 7b. That is, the collector resistance of the phototransistor 18 can be reduced. Further, in the light emitting diode 14, the outer peripheral portion of the single crystal silicon island 6a can be set at the same potential. (Second Embodiment) Next, a second embodiment will be described focusing on differences from the first embodiment.

In this embodiment, as shown in FIG. 5, high melting point metal films 37a and 37b as optical confinement layers are formed between the dielectric isolation films 5a and 5b and the polysilicon layer 3. Rhodium (Rh), silicium (Ir), platinum (Pt), molybdenum (Mo), tungsten (W), or the like is used as the refractory metal films 37a and 37b.
The refractory metal films 37a and 37b are formed in the V-groove 3 in the single crystal silicon substrate 6 in FIG.
5 is formed, and after the dielectric isolation film 5 is formed, the refractory metal film 37 is disposed. In other words, the melting points of the refractory metal films 37a and 37b as the optical confinement layers are higher than the melting points of polysilicon and aluminum, and are also affected in the subsequent steps of forming polysilicon and aluminum. There is nothing.

The light emitted from the light emitting diode 14 (light emitting element) can be efficiently transmitted to the titanium oxide layer 22 (waveguide forming member) by the high melting point metal films 37a and 37b. In the phototransistor 18 (light receiving element), light from the light emitting diode 14 can be efficiently converted into an electric signal.

The refractory metal film 3 as a light confinement layer
7a and 37b are provided between at least one of the dielectric isolation films 5a and 5b and the polysilicon layer 3 or between the dielectric isolation films 5a and 5b and the single crystal silicon islands 6a and 6b. And the light emitting diode 1
4 (light-emitting element) and the phototransistor 18 (light-receiving element).

As described above, in this embodiment, the islands 6a and 6b
Is surrounded by the refractory metal films 37a and 37b as light confinement layers for preventing light from leaking to the substrate (3), so that light is confined in the island and light can be used efficiently. . (Third Embodiment) Next, a third embodiment will be described focusing on differences from the first embodiment.

In the first embodiment, the substrate is formed by using the bonding method. However, in this embodiment, as shown in FIG. 6, the substrate is formed by using only the polysilicon deposit without using the bonding method. I have. That is, in the manufacturing process shown in FIG.
After the polysilicon layer 3 is formed in (c), the back surface of the single crystal silicon substrate 6 is polished to form a plurality of islands. still,
The polysilicon layer 3 is 1100 ° C. by the normal pressure epitaxial method.
It is formed to a thickness of several 100 μm. (Fourth Embodiment) Next, a fourth embodiment will be described focusing on differences from the first embodiment.

In this embodiment, as shown in FIG. 7, the optical waveguide is made of a transparent resin (polyimide or the like) instead of titanium oxide.
8 is used. By using photosensitive polyimide as this transparent resin, patterning by photolithography is also possible. (Fifth Embodiment) Next, a fifth embodiment will be described focusing on differences from the first embodiment.

In this embodiment, as shown in FIG. 8, the dielectric isolation films 5a and 5b are divided into two layers, and the polysilicon layers 39a and 39b are arranged between them. In this case, the polysilicon layers 39a and 39b function as thermal stress relieving layers to relieve thermal stress and reduce variations and variations in element characteristics.

As described above, in the present embodiment, the islands 6a and 6b are formed as polysilicon layers 39a and 39b as thermal stress relaxation layers made of a material having substantially the same thermal expansion coefficient as the island (polysilicon layer 3).
Within the allowable stress range.
a, 5b) The film thickness can be increased, and the withstand voltage can be increased.

As an application example of this embodiment, SIPOS (semi-insulating polycrystalline silicon) may be used instead of polysilicon as the thermal stress relaxation layer, or polysilicon and SIPO may be used.
You may use both of S. (Sixth Embodiment) Next, a sixth embodiment will be described focusing on differences from the first embodiment.

In this embodiment, as shown in FIG. 9, photocouplers for eight channels are integrated on one chip.
That is, eight light-emitting elements (light-emitting diodes) 41 are arranged in one island 40, and eight light-receiving elements (photodiodes) 43 are arranged in another island 42. Each light emitting element 41 and light receiving element 43 are optically coupled by a waveguide forming member 48. Also in this case, wires (and electrodes) 44 and 45 are provided in the island, and are connected to the lead frame 47 by bonding wires 46 as shown in FIG.

Incidentally, reference numeral 44a in FIG.
, And corresponds to the aluminum wiring for cathode 24 in FIG. Reference numeral 45a denotes a common wiring (common electrode) of each light receiving element 43, which corresponds to the collector aluminum wiring 28 in FIG.

By doing so, as shown in FIG. 10, the wires (and electrodes) 4 are provided outside the islands 40 and 42.
In the case where 4, 45 are provided, a thick field oxide film is required, but in this embodiment, a thin field oxide film is sufficient.

As described above, in this embodiment, a plurality of light-emitting elements (light-emitting diodes) 41 are arranged in one island 40 and a plurality of light-receiving elements (photodiodes) 43 are arranged in another island 42. As a result, a multi-channel structure is provided by arranging a plurality of structures in which one light emitting element (light emitting diode) is arranged in one island and one light receiving element (photodiode) is arranged in another island. The cost can be reduced as compared with the case where the structure is changed.

The present invention is not limited to the above embodiments. For example, the structure shown in FIG. 1 (one light emitting element is arranged on one island and one light emitting element is arranged on another island) A large number of light receiving elements may be arranged in one chip. As a result, since multiple channels are formed by forming a plurality of sets of photocouplers on the same substrate, compared to a case where multiple channels are provided by providing a plurality of sets of a structure in which one set of photocouplers is arranged on one substrate. Thus, costs can be reduced.

In this case, by arranging the light confinement layer (the high melting point metal films 37a and 37b in FIG. 5) as in the second embodiment, light is transmitted to another element, which may adversely affect that element. Thus, mutual interference between elements can be prevented beforehand.

[0060]

According to the first aspect of the present invention, in a semiconductor device in which a photocoupler is monolithically formed, a field oxide film for preventing dielectric breakdown between a substrate, a wiring, and an electrode can be made thin. Demonstrates excellent effects.

According to the invention described in claim 2, according to claim 1
In addition to the effects of the invention described in (1), the withstand voltage in each island can be equalized, and the thickness of the dielectric isolation film can be minimized. According to the third aspect of the invention, in addition to the effect of the first aspect, the resistance can be reduced by forming a current path through the high concentration diffusion layer.

According to the invention set forth in claim 4, according to claim 1,
In addition to the effects of the invention described in (1), by surrounding the island with a light confinement layer, light can be used efficiently. According to the invention described in claim 5, in addition to the effect of the invention described in claim 1, by surrounding the island with the thermal stress relaxation layer, the withstand voltage can be increased.

[Brief description of the drawings]

FIGS. 1A and 1B show a monolithic photocoupler according to a first embodiment, wherein FIG. 1A is a plan view and FIG. 1B is a sectional view taken along line AA of FIG.

FIGS. 2A to 2E are cross-sectional views illustrating the steps of manufacturing the monolithic photocoupler of the first embodiment.

3A and 3B show a monolithic photocoupler for comparison in the first embodiment, wherein FIG. 3A is a plan view and FIG. 3B is a cross-sectional view taken along line BB of FIG.

FIG. 4 is an equivalent circuit diagram of the monolithic photocoupler in the first embodiment.

FIG. 5 is a sectional view of a monolithic photocoupler according to a second embodiment.

FIG. 6 is a sectional view of a monolithic photocoupler according to a third embodiment.

FIG. 7 is a sectional view of a monolithic photocoupler according to a fourth embodiment.

FIG. 8 is a sectional view of a monolithic photocoupler according to a fifth embodiment.

9A and 9B show a monolithic photocoupler according to a sixth embodiment, wherein FIG. 9A is a plan view, FIG. 9B is a front view,
(C) is a side view.

10A and 10B show a monolithic photocoupler for comparison of the sixth embodiment, wherein FIG. 10A is a plan view, FIG. 10B is a front view, and FIG. 10C is a side view.

FIG. 11 is a perspective view of a monolithic photocoupler according to a sixth embodiment.

FIG. 12 is an explanatory diagram for testing a monolithic photocoupler.

FIG. 13 is a sectional view illustrating a monolithic photocoupler employing a dielectric isolation structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 3 ... Polysilicon layer, 5a ... Dielectric separation film, 5b ... Dielectric separation film, 6a ... Single crystal silicon island, 6b ... Single crystal silicon island, 7a ... High concentration diffusion layer, 7
b: high concentration diffusion layer, 10: n-type Al _x Ga _{1 -x} As layer,
11 ... n-type GaAs layer, 12 ... p-type GaAs layer, 13 ...
Au-Zn electrode, 14 light emitting diode, 18 phototransistor, 22 titanium oxide layer, 23 aluminum wiring, 24 aluminum wiring, 27 aluminum wiring, 28 aluminum wiring, 37 high melting point metal film, 39a ... Polysilicon layer, 39b ... polysilicon layer

Claims (5)

(57) [Claims] A substrate, a plurality of islands formed on the substrate and including a semiconductor layer surrounded by a dielectric isolation film, a light emitting element formed on the island, and an island formed with the light emitting element And a light-receiving element formed on an island other than the light-emitting element and optically coupled to the light-emitting element by a waveguide forming member, wherein a wiring for connecting the light-emitting element and the outside of the light-receiving element and A semiconductor device, wherein an electrode is formed only inside the island. 2. The method according to claim 1, wherein the dielectric isolation film on the island on which the light emitting element is formed and the dielectric isolation film on the island on which the light receiving element is formed have substantially the same area, thickness, and permittivity. Item 2. The semiconductor device according to item 1. 3. A high-concentration diffusion layer is formed in a portion of the semiconductor layer in contact with the dielectric isolation film, and the high-concentration diffusion layer is connected to a wiring or an electrode of the light emitting element or the light receiving element. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 1, wherein the island is surrounded by a light confinement layer for preventing light from leaking between the island and the substrate. 5. The semiconductor device according to claim 1, wherein the island is surrounded by a thermal stress relaxation layer made of a material having substantially the same thermal expansion coefficient as the island.