JP2010267647A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve high-speed response characteristic by reducing the parasitic capacitance of a wiring to the top of mesa in a semiconductor device such as an element for optical communication having a mesa-type photodiode. <P>SOLUTION: In the semiconductor device, a laminate of an n-type cladding layer 12b, an absorbing layer 12c, a p-type cladding layer 12d and a p-type high concentration layer 12e is formed in a mesa type on an n-type high concentration layer 12a formed on the surface of a substrate 11 and used as a cathode of the photodiode. Side surfaces of the laminate and side surfaces of the n-type high concentration layer 12a each have a portion forming wall surfaces continuing to each other and reaching from the surface of the substrate 11 to the p-type high concentration layer 12e without causing a step difference. A wiring 19d for connecting layers between a horizontal wiring 19a disposed on the substrate 11 to the layer of the p-type high concentration layer 12e as an anode of the photodiode is disposed along the wall surfaces. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a mesa element portion.

  A light emitting element and a light receiving element that can be used for conversion between an electric signal and an optical signal in transmission / reception of optical communication are realized as semiconductor elements. For example, a light receiving element such as a PIN photodiode (PIN-PD) or an avalanche photodiode (APD) has been put to practical use as a device on the receiving side of optical transmission.

  In these light emitting elements and light receiving elements, a semiconductor layer (active region) constituting a light emitting region or a photoelectric conversion region can be formed in a mesa shape. FIG. 18 is a plan view of a conventional back-illuminated type light receiving element 10, and FIG. 19 is a vertical sectional view taken along a line BB shown in FIG. The light receiving element 10 has a photodiode portion 12 that performs circular mesa photoelectric conversion on a substrate 11. The photodiode section 12 has an n-type high concentration layer 12a laminated on the surface of the substrate 11 as a cathode, and a p-type high concentration layer 12e laminated on the top of a mesa type as an anode.

  The light receiving element 10 includes an n-side electrode 15a to which a cathode voltage is applied and a p-side electrode 15b to which an anode voltage is applied. The n-side electrode 15a is connected to the n-type high concentration layer 12a through the through hole 14a. In addition, the p-side electrode 15b is arranged at a position different from the photodiode part 12, and is connected to the p-side electrode 15b via a wiring extending from the p-side electrode 15b to a through hole 14b located at the top of the mesa forming the photodiode part 12. It is connected to the mold high concentration layer 12e.

  The wiring 19 connecting the p-side electrode 15b and the through hole 14b connects between the wiring 19a formed of a wiring layer laminated on the surface of the substrate 11 and the upper part of the mesa where the through hole 14b is located. It has a structure including the interlayer connection wiring 19b (step wiring structure). The n-side electrode 15a, the p-side electrode 15b, and the wiring 19 are formed by patterning a wiring layer such as a metal film, and the wiring layer is formed on the dielectric film 13 to prevent a short circuit with the base. Laminated.

JP 2007-288089 A Japanese Patent Laid-Open No. 11-330534

  The circular mesa portion of the photodiode portion 12 of the light receiving element 10 is located inside the n-type high concentration layer 12a in the planar arrangement. As a result, there is a distance between the circular edge of the mesa and the edge of the n-type high concentration layer 12a, and in the conventional stepped wiring structure, a part of the interlayer connection wiring 19b is on the upper surface of the n-type high concentration layer 12a. Arranged along. Accordingly, the area of the portion 18 where the n-type high concentration layer 12a to which the voltage is applied from the n-side electrode 15a and the wiring to which the voltage is applied from the p-side electrode 15b is close increases, and the parasitic capacitance of the portion 18 increases. To increase. This parasitic capacitance has a problem of deteriorating the response characteristics of the photodiode section 12. A similar problem occurs when another semiconductor device such as a light emitting element having a mesa type light emitting portion is configured using the stepped wiring structure as described above. In particular, in an optical semiconductor element that requires high-speed operation, such as a light-receiving element or a light-emitting element used in optical communication, reduction of parasitic capacitance is an important issue.

  The present invention has been made to solve the above-described problem. In a semiconductor device having a lower layer stacked on a substrate surface to which a voltage is applied and a wiring for supplying a voltage to an upper layer of a mesa, The purpose is to reduce the capacitance between the wiring and the lower layer.

  A semiconductor device according to the present invention includes a lower layer stacked on a substrate surface to which a first voltage is applied, an intermediate layer formed in a mesa shape on the lower layer, and a second voltage stacked on the intermediate layer. A semiconductor element including an upper layer to which an electric current is applied, and an interlayer connection wiring for supplying the second voltage to the upper layer from a wiring layer laminated on the substrate surface, and a side surface of the intermediate layer And the side surface of the lower layer has a portion that forms a wall surface continuously reaching the upper layer from the substrate surface, and the interlayer connection wiring is disposed along the wall surface.

  A semiconductor device according to a preferred embodiment of the present invention is a surface incident light receiving device, and the semiconductor element is a light receiving portion having an absorption layer for performing photoelectric conversion in the intermediate layer.

  Here, the lower layer may be a first conductivity type semiconductor layer, and the upper layer may be a second conductivity type semiconductor layer different from the first conductivity type. In this configuration, for example, the substrate is a semi-insulating semiconductor substrate that transmits light to be detected incident from the back side of the substrate to the substrate surface, the lower layer is an InP layer, and the upper layer and the absorption layer are InGaAs layers. Layer or an InAlGaAs layer.

  Further, in the above-described preferred aspect, the semiconductor element includes, in order from the lower layer side, the first conductivity type lower cladding layer having an impurity concentration lower than that of the lower layer, the absorption layer made of an i-type semiconductor layer, And a PIN type light receiving portion having the intermediate layer on which the second conductivity type upper clad layer having an impurity concentration lower than that of the upper layer is laminated. In this configuration, the substrate is a semi-insulating semiconductor substrate that transmits light to be detected incident from the back surface of the substrate to the substrate surface, the lower layer is an InP layer, and the upper layer is an InGaAs layer or an InAlGaAs layer, The lower cladding layer and the upper cladding layer can be InAlGaAs layers.

  According to the present invention, the parasitic capacitance of a semiconductor element can be reduced. Thereby, the responsiveness of the semiconductor element can be improved.

1 is a schematic plan view of a back-illuminated light receiving element according to an embodiment of the present invention. It is a typical vertical sectional view of the light receiving element according to the embodiment of the present invention along the line AA shown in FIG. It is a typical vertical sectional view in the main manufacturing process of the light receiving element according to the embodiment of the present invention. It is a typical vertical sectional view in the main manufacturing process of the light receiving element according to the embodiment of the present invention. It is a typical vertical sectional view in the main manufacturing process of the light receiving element according to the embodiment of the present invention. It is a typical vertical sectional view in the main manufacturing process of the light receiving element according to the embodiment of the present invention. It is a typical vertical sectional view in the main manufacturing process of the light receiving element according to the embodiment of the present invention. It is a typical vertical sectional view in the main manufacturing process of the light receiving element according to the embodiment of the present invention. It is a typical vertical sectional view in the main manufacturing process of the light receiving element according to the embodiment of the present invention. FIG. 4 is a schematic plan view of a light receiving element in the main manufacturing process shown in FIG. 3. FIG. 5 is a schematic plan view of a light receiving element in the main manufacturing process shown in FIG. 4. FIG. 6 is a schematic plan view of a light receiving element in the main manufacturing process shown in FIG. 5. FIG. 7 is a schematic plan view of a light receiving element in the main manufacturing process shown in FIG. 6. FIG. 8 is a schematic plan view of a light receiving element in the main manufacturing process shown in FIG. 7. FIG. 9 is a schematic plan view of a light receiving element in the main manufacturing process shown in FIG. 8. FIG. 6 is a vertical sectional view of a conventional light receiving element in a process corresponding to the manufacturing process shown in FIG. 5. It is a top view of the conventional light receiving element in the process corresponding to the manufacturing process shown in FIG. It is a top view of the conventional light receiving element of a back incidence type. FIG. 19 is a vertical sectional view of a conventional light receiving element along a line BB shown in FIG. 18.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

  FIG. 1 is a schematic plan view of a back-illuminated light receiving element 30 according to an embodiment of the present invention, and FIG. 2 is a schematic vertical cross section of the light receiving element 30 along a line AA shown in FIG. FIG. In the light receiving element 30, the same components as those of the light receiving element 10 illustrated in FIGS. 18 and 19 are denoted by the same reference numerals to facilitate comparison with the light receiving element 10.

  The light receiving element 30 includes a substrate 11, a photodiode portion 12, an n-side electrode 15 a, a p-side electrode 15 b, a dielectric film 13, and an antireflection film 16.

  The substrate 11 is made of a semi-insulating material. The substrate 11 has optical transparency, and is formed of, for example, indium phosphide (Fe—InP) doped with iron. For example, the substrate 11 is formed with a thickness of about 100 μm.

  The antireflection film 16 is laminated on the back surface of the substrate 11, suppresses the reflection of light on the substrate 11, and improves the light incident efficiency to the photodiode portion 12. For example, the antireflection film 16 is formed with a thickness of about 0.2 μm.

  In the present embodiment, the photodiode portion 12 is a PIN photodiode, and sequentially from the substrate 11 side, the n-type high concentration layer 12a, the n-type cladding layer 12b, the absorption layer 12c, the p-type cladding layer 12d, and the p-type. The high concentration layer 12e has a stacked structure. For example, the photodiode portion 12 is formed with a thickness of about 2.0 μm.

  The n-type high concentration layer 12a is a semiconductor layer formed by introducing n-type impurities at a high concentration and having a low resistance, and constitutes the cathode of the photodiode. Corresponding to the light receiving element 30 of the present embodiment being a back-illuminated type, the n-type high concentration layer 12a is formed of a material having optical transparency.

  The p-type high concentration layer 12e is a semiconductor layer formed by introducing a high concentration of p-type impurities and having a low resistance, and constitutes the anode of the photodiode. The absorption layer 12c is made of an i-type semiconductor layer and is formed with a low impurity concentration. The cladding layers 12b and 12d have an intermediate impurity concentration between the absorption layer 12c and the high concentration layers 12a and 12e. The portions of the photodiode portion 12 that are stacked on the n-type high concentration layer 12a (the n-type cladding layer 12b, the absorption layer 12c, the p-type cladding layer 12d, and the p-type high concentration layer 12e) are circular in shape. Formed in mesa shape.

  The n-side electrode 15 a and the p-side electrode 15 b are electrode pads made of a wiring layer stacked on the dielectric film 13. The dielectric film 13 is laminated below the wiring layer, and electrically insulates the wiring layer from other parts, for example, the n-type high concentration layer 12a, the p-type high concentration layer 12e, and the like. For example, the dielectric film 13 is formed with a thickness of about 0.6 μm.

  A through hole 14a is formed in the dielectric film 13 on the n-type high concentration layer 12a, and the wiring layer connected to the n-side electrode 15a and the n-type high concentration layer 12a are in ohmic contact with each other through the through hole 14a. The n-side electrode 15a and the n-type high concentration layer 12a are electrically connected.

  In the dielectric film 13, a through hole 14b is also formed on the p-type high concentration layer 12e, and the electrode 15c and the p-type high concentration layer 12e formed thereon are ohmic through the through hole 14b. Contact. The electrode 15c is connected to the p-side electrode 15b through the wiring 19, and the p-type high concentration layer 12e and the p-side electrode 15b are electrically connected.

  Corresponding to the formation region of the p-side electrode 15b, a convex portion is formed on the substrate 11, and the p-side electrode 15b is disposed on the upper surface of the convex portion. Although the p-side electrode 15b has a relatively large area, parasitic capacitance can be suppressed by maintaining the distance from the substrate 11 by the convex portion.

  On the other hand, the wiring 19 between the electrode 15c and the p-side electrode 15b has a portion that approaches the substrate 11 and the n-type high concentration layer 12a. Therefore, the parasitic capacitance of the wiring 19 is suppressed by reducing the wiring width. Specifically, the wiring 19 is connected along a portion (horizontal wiring 19a) arranged along the surface of the substrate 11 and the p-side electrode 15b and the horizontal wiring 19a arranged along the side surface of the convex portion. An interlayer connection wiring 19c and an interlayer connection wiring 19d arranged along the side surface of the photodiode portion 12 and connecting the horizontal wiring 19a and the electrode 15c are formed. In order to reduce the parasitic capacitance, these portions are basically set to be narrow in a range in which the wiring resistance does not hinder the operation of the light receiving element 30. In addition, since parasitic capacitance increases with the area of the wiring, consideration is given to shortening the wiring length. In this regard, according to the present invention, the interlayer connection wiring 19d has a portion along the side surface of the n-type high concentration layer 12a, but is configured not to have a portion along the upper surface of the n-type high concentration layer 12a. . As described above, the parasitic capacitance is reduced by reducing the length and area of the portion 18 disposed in the proximity of the n-type high concentration layer 12a in the interlayer connection wiring 19d. This improves the response speed of the photodiode.

  In order to form the interlayer connection wiring 19d as described above, a mesa portion (n-type cladding layer 12b, absorption layer 12c, p-type cladding layer 12d) stacked on the n-type high concentration layer 12a in the photodiode portion 12 is formed. The p-type high-concentration layer 12e) has a planar contour that has a portion that matches the contour of the n-type high-concentration layer 12a. The coincident portion of the contour of the planar shape of the mesa portion and the n-type high concentration layer 12a is such that the side surface of the mesa portion and the side surface of the n-type high concentration layer 12a are continuous with each other and the p-type height at the upper end of the mesa portion from the substrate 11 surface. A wall surface reaching the concentration layer 12e is formed. The interlayer connection wiring 19d is arranged along this wall surface, and thereby the horizontal wiring 19a and the horizontal wiring 19a are connected without passing through the portion along the upper surface of the n-type high concentration layer 12a as the interlayer connection wiring 19b of FIG. The p-side electrode 15b can be connected.

  For example, as shown in FIG. 2, the planar shape of the mesa portion is a rectangle that bridges between a circular portion having a size required for the photodiode portion 12 and the periphery of the circular portion and the n-type high concentration layer 12a. It can be made into the keyhole shape which combined the part.

  As described above, a convex portion is formed at the position of the p-side electrode 15b, and a convex portion is also formed at the position of the n-side electrode 15a correspondingly. For example, as a result, the n-side electrode 15a and the p-side electrode 15b have the same height, and wiring from the outside to these electrode pads becomes easy.

  Next, the manufacturing process of the light receiving element 30 will be described. 3 to 9 are schematic vertical cross-sectional views in the main manufacturing process of the light receiving element 30, and show a cross section at a position along the line AA shown in FIG. 1. 10 to 15 are schematic plan views in main manufacturing steps of the light receiving element 30, and the steps shown in FIGS. 10 to 15 are steps shown in FIGS.

  First, an n-type high concentration layer 12a having a thickness of about 0.5 μm and an n-type cladding layer having a thickness of 0.7 μm are formed on a flat semi-insulating substrate 11 having a thickness of about 450 μm by crystal growth or doping. 12b, an absorption layer 12c having a thickness of about 0.8 μm, a p-type cladding layer 12d having a thickness of about 0.7 μm, and a p-type high concentration layer 12e having a thickness of about 0.1 μm are sequentially stacked (see FIG. 3).

The substrate 11 is formed of a light-transmitting material as described above in response to the light receiving element 30 being a back-illuminated type. For example, as described above, Fe—InP is used. Further, n-type high-concentration layer 12a also has a light transmitting property, for example, an impurity concentration is formed by a 5.0 × ¹⁰ 18 ^{cm -3} of about indium phosphide (InP). The n-type cladding layer 12b has, for example, an impurity concentration of about 3.0 × 10 ¹⁷ cm ⁻³ and is formed of, for example, indium aluminum gallium arsenide (InAlGaAs) having a composition wavelength of about 1.2 μm. The absorption layer 12c is formed of indium gallium arsenide (InGaAs) having an impurity concentration of about 1.0 × 10 ¹⁵ cm ⁻³ . The absorption layer 12c can also be composed of an InAlGaAs layer or the like. The p-type cladding layer 12d is formed of, for example, InAlGaAs having an impurity concentration of about 3.0 × 10 ¹⁷ cm ⁻³ and a composition wavelength of about 1.2 μm. The p-type high concentration layer 12e is formed of InGaAs or the like having an impurity concentration of about 5.0 × 10 ¹⁹ cm ⁻³ .

  Then, square masks 17 are formed at two locations on the p-type high concentration layer 12e (see FIGS. 3 and 10). Specifically, the formation position of the mask 17 is the same as the position of the n-type high concentration layer 12a disposed in the portion where the n-side electrode 15a and the photodiode portion 12 are formed in the light receiving element 30 shown in FIGS. And the position of the convex part under the p-side electrode 15b. The mask 17 is formed by a photolithography technique using a material such as a photoresist or an oxide film, for example.

  Using this mask 17 as an etching mask, a first mesa etching process is performed, and the regions from the p-type high concentration layer 12e to the n-type high concentration layer 12a not covered with the mask 17 are removed. As a result, the surface of the substrate 11 is exposed in the region. After the etching is completed, the mask 17 is removed. 4 and 11 show the state after the end of the first mesa etching process.

  After the first mesa etching step, a second mesa etching step is performed. In this step, first, an etching mask is formed on the p-type high concentration layer 12e. This etching mask can be formed by the same means as the mask 17 described above. The etching mask is formed on the formation region of the convex portion below the n-side electrode 15a and the p-side electrode 15b in the light receiving element 30 shown in FIGS. 1 and 2 and the formation region of the key-shaped mesa portion of the photodiode portion 12, for example. Correspondingly formed.

  Further, in the second mesa etching step, the region from the p-type high concentration layer 12e to the n-type cladding layer 12b that is not covered with the etching mask is removed by etching. After the etching is completed, the etching mask is removed. 5 and 12 show the state after the end of the second mesa etching process. In this manner, the photodiode portion 12 that performs photoelectric conversion is formed on the light-transmitting substrate 11. Specifically, a rectangular plate-like n-type high-concentration layer 12a that is relatively large is formed on the substrate 11, and an n-type cladding layer 12b, an absorption layer 12c, and a p-type cladding layer 12d are further formed thereon. In addition, a mesa portion made of the p-type high concentration layer 12e and having an area smaller than that of the n-type high concentration layer 12a is formed. Although the mesa portion is generally cylindrical, as described above, the planar shape is a keyhole shape in which a rectangle (part 21 in FIG. 12) is added to a part of the circumference of the circle (part 20 in FIG. 12). It has the part 22b which protruded from the side surface of the part 22a. The protruding portion 22b reaches the end of the n-type high concentration layer 12a, and a side face 23 connected without a step is formed between the n-type high concentration layer 12a and the mesa portion.

  In the second mesa etching process, in addition to the photodiode portion 12, convex portions 24a and 24b below the n-side electrode 15a and the p-side electrode 15b are also formed.

  A dielectric film 13 is formed on the surface side of the substrate 11 on which the photodiode portion 12 and the like are formed by the second mesa etching process (see FIGS. 6 and 13).

The dielectric film 13 includes, for example, two layers of a silicon nitride (SiN) layer of about 0.26 μm and a silicon oxide (SiO ₂ ) layer of about 0.3 μm formed on the SiN layer. The

  A part of the dielectric film 13 is selectively removed by etching using a photolithography technique, and a through hole 14a reaching the n-type high concentration layer 12a is formed in a partial region on the n-type high concentration layer 12a. Further, a through hole 14b reaching the p-type high concentration layer 12e is formed in a partial region on the p-type high concentration layer 12e (see FIGS. 7 and 14).

  Thereafter, the n-side electrode 15a, the p-side electrode 15b, the electrode 15c, and the wiring 19 (horizontal wiring 19a and interlayer connection wirings 19c and 19d) are formed by a wiring layer made of metal (see FIGS. 8 and 15). Here, the interlayer connection wiring 19 d is arranged along the side surface 23. These electrodes and wirings are formed, for example, by a method such as vapor deposition. Of course, other plating methods may be used.

  Next, the substrate 11 is polished from the back side until the thickness reaches about 100 μm. Then, an antireflection film 16 is formed on the back surface of the substrate 11 (see FIG. 9). The antireflection film 16 is formed by, for example, a SiN layer of about 0.2 μm.

  The light receiving element 30 shown in FIGS. 1 and 2 is manufactured through the above steps. Here, in order to assist understanding of the structure and manufacturing process of the light receiving element 30 according to the present embodiment, the manufacturing process of the conventional light receiving element 10 shown in FIGS. 18 and 19 is different from the light receiving element 30 of the present embodiment. The points to be described will be explained. FIG. 16 is a schematic vertical sectional view of a conventional light receiving element 10, and FIG. 17 is a schematic plan view of the conventional light receiving element 10. 16 and 17 show a process corresponding to the manufacturing process of the light receiving element 30 shown in FIGS. 5 and 12. The conventional light receiving element 10 has a mesa portion on the n-type high concentration layer 12a only in a cylindrical shape (corresponding to the column portion 22a of the light receiving element 30), and has a protruding portion 22b reaching the end of the n type high concentration layer 12a. Therefore, there is a step between the side surface of the mesa portion and the side surface of the n-type high concentration layer 12a. As a result, as shown in FIG. 19, a portion along the upper surface of the n-type high concentration layer 12a is generated in the interlayer connection wiring 19b. On the other hand, in the light receiving element 30, as shown in FIGS. 5 and 12, the side surface of the protruding portion is aligned with the side surface of the n-type high concentration layer 12a to form one continuous side surface 23. Thereby, the interlayer connection wiring 19d can connect the level difference between the horizontal wiring 19a and the electrode 15c with a straight line without a step. Further, the difference in the manufacturing process between the light receiving element 30 and the light receiving element 10 is basically only the pattern of the etching mask in the second mesa etching process that defines the shape of the mesa part of the photodiode part 12, The present invention can be implemented without adding a special process to the manufacturing process.

  The present invention is not limited to the above embodiment. For example, the photodiode unit 12 according to the present invention may be other types of photodiodes such as an avalanche photodiode instead of the PIN photodiode as in the present embodiment.

  For example, the photodiode portion 12 does not have the n-type cladding layer 12b and the p-type cladding layer 12d, but the n-type high concentration layer 12a made of an InP layer, the absorption layer 12c made of an InGaAs layer or an InAlGaAs layer, and a p-type high concentration layer. 12e can be laminated.

  Further, the photodiode unit 12 may be replaced with a light receiving unit that performs general photoelectric conversion. That is, the photodiode unit 12 is only an example of a photoelectric conversion unit. Furthermore, the application range of the present invention is not limited to a light receiving element, but can be applied to an optical semiconductor element including a surface emitting light emitting element configured using a mesa structure such as a light emitting diode or a laser diode, and other semiconductor elements in general. .

  In addition, the material of each member which concerns on this invention is not limited to the above-mentioned thing. In addition, the specific numerical values shown in the above description are merely examples, and the structure of the light receiving element 30 according to the present invention is not limited to the above numerical values.

  DESCRIPTION OF SYMBOLS 11 Substrate, 12 Photodiode part, 12a n-type high concentration layer, 12b n-type cladding layer, 12c absorption layer, 12d p-type cladding layer, 12e p-type high concentration layer, 13 dielectric film, 14a, 14b through hole, 15a n-side electrode, 15b p-side electrode, 15c electrode, 16 antireflection film, 17 mask, 19 wiring, 19a horizontal wiring, 19c, 19d interlayer connection wiring, 22a cylindrical portion, 22b protruding portion, 23 side surface, 24a, 24b convex portion .

Claims (6)

A lower layer stacked on a substrate surface to which a first voltage is applied; an intermediate layer formed in a mesa shape on the lower layer; and an upper layer stacked on the intermediate layer and applied with a second voltage. In a semiconductor device having a semiconductor element and an interlayer connection wiring for supplying the second voltage from a wiring layer laminated on the substrate surface to the upper layer,
The side surface of the intermediate layer and the side surface of the lower layer have a portion that forms a wall surface that reaches the upper layer continuously from the substrate surface,
The interlayer connection wiring is disposed along the wall surface;
A semiconductor device characterized by the above. The semiconductor device according to claim 1,
The semiconductor device is a surface incidence type light receiving device,
The semiconductor device is a light receiving portion having an absorption layer for performing photoelectric conversion in the intermediate layer. The semiconductor device according to claim 2,
The lower layer comprises a first conductivity type semiconductor layer,
The upper layer comprises a semiconductor layer of a second conductivity type different from the first conductivity type;
A semiconductor device characterized by the above. The semiconductor device according to claim 3.
The semiconductor element has, in order from the lower layer side, the first conductivity type lower cladding layer having an impurity concentration lower than that of the lower layer, the absorption layer made of an i-type semiconductor layer, and an impurity concentration lower than that of the upper layer. A semiconductor device comprising: a PIN type light receiving portion having the intermediate layer on which the second conductivity type upper clad layer is stacked. The semiconductor device according to claim 3.
The substrate is a semi-insulating semiconductor substrate that transmits detection target light incident from the back surface of the substrate to the substrate surface;
The lower layer comprises an InP layer;
The upper layer and the absorption layer are composed of an InGaAs layer or an InAlGaAs layer;
A semiconductor device characterized by the above. The semiconductor device according to claim 4,
The substrate is a semi-insulating semiconductor substrate that transmits detection target light incident from the back surface of the substrate to the substrate surface;
The lower layer comprises an InP layer;
The upper layer comprises an InGaAs layer or an InAlGaAs layer,
The lower cladding layer and the upper cladding layer are composed of InAlGaAs layers,
The absorption layer comprises an InGaAs layer;
A semiconductor device characterized by the above.

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