JP4352584B2 - Memory circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a storage circuit device that is accessed by a CPU with a constant data bus size, and an error correction circuit that corrects an error when a correctable error is detected when the stored data is read. It relates to what has a part.
[0002]
[Prior art]
For example, in a memory system in which the CPU reads data stored in a memory such as a DRAM, there is a possibility that an error (so-called soft error) may randomly occur when α rays are incident on a memory cell of the DRAM. Therefore, when high reliability is required for such a memory system, an ECC (Error Chcking and Correcting) circuit may be added.
[0003]
When the CPU reads data from the memory, the ECC circuit generates a plurality of test data (syndrome bits) by taking an exclusive OR with respect to a certain combination of these data bits. The generated syndrome bits are stored at the same address as the data in the memory.
[0004]
When the CPU reads data (referred to as information data) from the memory, the inspection data generated corresponding to the information data is also read at the same time. At this time, the ECC circuit generates an error code from the read information data and inspection data, and detects whether or not there is an error in the information data based on the value of the error code. When a 1-bit error that can be corrected is detected, the error is corrected. It is also possible to detect that an error of 2 bits or more has occurred in the read data.
[0005]
[Problems to be solved by the invention]
By the way, when the ECC function as described above is added to the memory system, an extra memory capacity is required to store the inspection data. For example, when the inspection data is generated with 5 bits for the information data bus size of 16 bits (2 bytes), the inspection data is generated with 6 bits when the data bus size is 32 bits (4 bytes). Therefore, there is a problem that the system becomes larger due to the increase in capacity and the cost is increased.
[0006]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a memory circuit device capable of suppressing an increase in the capacity of the memory circuit unit when an error correction circuit unit is provided.
[0007]
[Means for Solving the Problems]
According to the memory circuit device of the first aspect, the memory circuit unit is configured to be accessed with a bus size that is a multiple of the data bus size when the CPU accesses the memory circuit unit. An error correction circuit unit for performing error correction is provided. When the CPU tries to read the information data from the storage circuit unit, the access control unit reads the information data from the storage circuit unit with a multiple bus size including the data. The data to be read is selected and output on the data bus of the CPU. Further, the access control unit delays the timing of the acknowledge signal output to the CPU until the data correction processing by the error correction circuit unit is completed.
[0008]
That is, the number of bits of inspection data generated by the error correction circuit unit increases by one bit when the number of bits of information data (referred to as data other than inspection data actually required) is doubled. The number of bits of inspection data generated for the information data capacity decreases as the data bus size for writing and reading increases.
[0009]
For example, if the bus size of the information data is 1 byte (B) and the number of words is W, the capacity is B × W. Here, if the number of bits of inspection data generated by the error correction circuit unit for one byte is s, the capacity required for the inspection data is s × W. If the bus size of the information data is 2 ^x bytes (x is a natural number), the number of words becomes W / 2 ^x , and the number of bits required for the inspection data increases by “x”, so the capacity required for the inspection data is ( s + x) × W / 2 ^x .
[0010]
In this case, x is added to the coefficient of W in the numerator, whereas the denominator increases by 2 to the power of x, so that the capacity required for the inspection data is definitely reduced. Therefore, by configuring as in the first aspect, even when the error correction circuit unit is provided and the reliability of the information data stored in the storage circuit unit is improved, the capacity required for the storage circuit unit can be increased compared to the conventional case. Thus, the circuit area can be reduced and the whole can be made compact, and the manufacturing cost can be reduced.
[0011]
According to the memory circuit device of the second aspect, the access control unit holds the information data that the CPU outputs on the data bus when the CPU intends to newly write information data to the memory circuit unit. When information data equal to the data bus size of the storage circuit unit is held, the information data and the inspection data generated by the error correction circuit unit are stored in the storage circuit unit.
[0012]
That is, when the CPU tries to write new information data to the storage circuit unit in which no information data is stored, the access control unit reads the information data output by the CPU on the data bus by one address. Hold every time. If the information data equal to the data bus size of the storage circuit unit is held, the corresponding inspection data is generated by the error correction circuit unit, so that the data bus size between the CPU and the storage circuit unit is different. In addition, the information data and the inspection data can be stored in the storage circuit unit.
[0013]
According to the storage circuit device of the third aspect, the access control unit executes the read-modify-write cycle when the CPU tries to rewrite the information data stored in the storage circuit unit. That is, once the information data is read from the storage circuit unit with an address including the data portion to be rewritten by the CPU, and the data portion output by the CPU is replaced, the error correction circuit unit obtains the inspection data for the required data bus size. Can be generated.
[0014]
According to the memory circuit device of the fourth aspect, the memory circuit unit is constituted by the flash memory. Conventionally, an error correction function is generally added to improve the reliability of a memory such as a DRAM. In recent years, a flash memory is often used as a program memory of a CPU, and in that case, rewriting is performed at a relatively high frequency in a development stage or the like. Then, there is a possibility that the threshold voltage VT of each cell transistor may vary, and there is a possibility that an error occurs in the data due to the variation. Therefore, it is effective to improve the reliability by adding an error correction circuit unit even when the memory circuit unit is constituted by a flash memory.
[0015]
According to the memory circuit device of the fifth aspect, the memory circuit unit, the error correction circuit unit, and the access control unit are formed on the same semiconductor substrate. In other words, an error correction circuit unit and an access control unit are configured as a one-chip IC with a built-in memory circuit unit, and the CPU connected outside the memory handles the memory circuit device in the same way as a normal memory. It becomes possible. Therefore, an increase in circuit area due to the addition of the function can be suppressed as much as possible.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram showing an electrical configuration of the memory circuit device. The memory circuit device 1 includes a flash memory (memory circuit unit) 2, an ECC circuit unit (error correction circuit unit) 3, a controller (access control unit) 4, a read buffer (hereinafter referred to as an R buffer, access control unit) 5U and 5L and write latches (hereinafter referred to as W latches, access control units) 6U and 6L are formed on the same semiconductor substrate and configured as a one-chip IC.
[0017]
A CPU 7 is connected to the outside of the memory circuit device 1. The data bus size of the CPU 7 is 8 bits, and the 8-bit data bus (D 7 to D 0) is connected to the memory circuit device 1.
[0018]
The flash memory 2 is a rewritable nonvolatile storage means that can erase data in units of blocks and rewrite data in units of pages. The capacity of the flash memory 2 has 1 k bits of 16 bits × 64 words as a storage area for information data, and 5 bits of test data generated by the ECC circuit unit 3 based on the value of the information data. The storage area has 320 bits of 5 bits × 64 words. The flash memory 2 includes a row selection circuit 2L and a column selection circuit 2C for selecting memory cells arranged in a matrix based on addresses output from the CPU.
[0019]
Here, if 1k bits are assigned as 8 bits (1 byte) .times.128 words, addresses are assigned to 7 bits A6 to A0 (127 to 0). On the other hand, since the data bus size of the flash memory 2 is 16 bits (2 bytes), the upper 6 bits (A6 to A1) of the address are given to the flash memory 2.
[0020]
In the flash memory 2, a control program for the CPU 7 is written in advance by the CPU 7 as information data through the W latches 6U and 6L. That is, the controller 4 outputs latch signals and enable signals to the W latches 6U and 6L, so that when the CPU 7 outputs information data to be written to the address of A0 = 0, the 8-bit data is output by the W latch 6L. When the information data written to the address of A0 = 1 is output, the 8-bit data is latched by the W latch 6U. Then, the W latches 6U and 6L are enabled to cause the ECC circuit unit 3 to generate 5-bit inspection data, and information data and inspection data are simultaneously written in the flash memory 2.
The CPU 7 reads and executes a control program stored in the flash memory 2 to control an external device (not shown).
[0021]
The R buffers 5U and 5L have an 8-bit configuration, and are used to select data to be output on the 8-bit data bus of the CPU 7 when the CPU 7 reads information data from the flash memory 2 (details will be described later). ). That is, the input side of the R buffer 5U is connected to the upper side (D15 to D8) of the 16-bit data bus of the flash memory 2, and the input side of the R buffer 5L is connected to the lower side (D7 to D0) of the data bus. It is connected. The output sides of the R buffers 5U and 5L are connected to the 8-bit data bus (D7 to D0) of the CPU 7.
[0022]
When the information data is read from the flash memory 2 by the CPU 7, the controller 4 reads the inspection data from the flash memory 2 together with the information data. Then, when the ECC circuit unit 3 generates an error code from the read information data and inspection data, the ECC circuit unit 3 detects whether or not there is an error in the information data. That is, if the value of the error code is “0”, there is no error in the information data. If the error code is other than “0” and matches a predefined error code, a 1-bit error (1 bit error) has occurred in the information data, and if it does not match the error code, the information An error of 2 bits or more (2-bit error) has occurred in the data.
[0023]
When the ECC circuit unit 3 detects a 1-bit error as described above, the ECC circuit unit 3 corrects the error (inverts the bit value). Further, only a 2-bit error can be detected.
[0024]
The controller 4 is provided with an address output by the CPU 7 and various control signals, and outputs a control signal to the flash memory 2 and the ECC circuit unit 3 and outputs an enable signal to the R buffers 5U and 5L. . Further, when the CPU 7 performs a read cycle for the memory circuit device 1, an acknowledge signal (ACK) is output at an appropriate timing.
[0025]
The controller 4 is given a 1-bit error detection signal ERR1 from the ECC circuit unit 3, and when a 1-bit error is detected in the information data, the data correction processing by the ECC circuit unit 3 is completed. Until this is done, the output timing of the acknowledge signal is delayed.
[0026]
Next, the operation of this embodiment will be described. When the CPU 7 performs a read cycle for the memory circuit device 1, the cycle proceeds as follows. However, not all signals actually used are mentioned, and only the part related to the gist of the present invention will be described.
[0027]
<When there is no error in the information data>
(1) When the CPU 7 outputs the addresses A6 to A0 and starts the read cycle, the controller 4 decodes the address and determines that it is a read access to the memory circuit device 1. Then, a read control signal (Chip Enable, Output Enable, etc.) is output to the flash memory 2.
[0028]
(2) Then, the upper 6 bits (A6 to A1) of the address are given from the flash memory 2, and 16-bit information data is read out.
(3) The ECC circuit section 3 performs error detection based on the 16-bit information data read from the flash memory 2 and the 5-bit test data.
[0029]
(4) If the ECC circuit unit 3 does not output the 1-bit error detection signal ERR1 within a predetermined period, the controller 4 outputs an enable signal to one of the R buffers 5U and 5L according to the value of the address A0. . That is, if the access address of the CPU 7 is XXXXXX (binary), the R buffer 5L is enabled, and the data on the lower side (D7 to D0) of the data bus of the flash memory 2 is 8 bits of the CPU7. Output to the data bus. If the access address is xxxxxxx, the R buffer 5U is enabled and the data on the upper side (D15 to D8) of the data bus of the flash memory 2 is output to the 8-bit data bus of the CPU 7. The
[0030]
(5) Subsequently, the controller 4 outputs an acknowledge signal to the CPU 7. When recognizing the acknowledge signal, the CPU 7 latches and reads the data read from the memory circuit device 1. Then, the address output is stopped and the read cycle is terminated.
[0031]
<If there is an error in the information data>
Steps {circle around (1)} to {circle around (3)} are the same as when there is no error, and at {circle around (4)}, the ECC circuit section 3 outputs a 1-bit error detection signal ERR1 within a predetermined period. Then, the ECC circuit unit 3 corrects the data value in which the 1-bit error has occurred. Then, in (5), the controller 4 delays the output timing of the acknowledge signal to the CPU 7 by the time for which the ECC circuit unit 3 performs error correction, and outputs the delayed signal.
[0032]
In the above description, the operation of the ECC circuit unit 3 is well known, and the timing chart for error detection and error correction does not replace that disclosed in the data sheet of the ECC IC.
[0033]
Here, the capacity required for storing the inspection data in the flash memory 2 is 5 × 64 = 320 bits because the number of words is 64 with respect to the number of bits 5. Further, when the data bus size of the storage circuit unit is set to the same 8 bits with respect to the data bus size of 8 bits of the CPU 7 as in the prior art, the number of words is 128 with respect to the number of bits of 4 × 4 ×. 128 = 512 bits are required.
[0034]
Therefore, the total capacity reduction rate is
(1024 + 320) / (1024 + 512)
= 1344/1536 = 12.5 (%)
It becomes. That is, the capacity of the flash memory 2 is reduced by about 12.5%.
[0035]
As described above, according to the present embodiment, the flash memory 2 is configured so that the data bus size of the CPU 7 is accessed in 16 bits, and the controller 4 is configured so that the CPU 7 receives data from the flash memory 2. When trying to read data, the data is read from the flash memory 2 with 16 bits, and the data that the CPU 7 is to read is selected from these data and output onto the data bus of the CPU 7. Further, the 5-bit inspection data corresponding to the 16-bit information data is also read from the flash memory 2, and when a 1-bit error occurs in the information data, the ECC circuit unit 3 corrects it.
[0036]
Therefore, even when the ECC circuit unit 3 is provided and the reliability of the information data stored in the flash memory 2 is improved, the capacity required for the flash memory 2 is reduced as compared with the conventional case, the circuit area is reduced, and the entire data is stored. It is possible to reduce the manufacturing cost. Further, when writing to the flash memory 2 is performed at a high frequency or there is a possibility that the reliability may be lowered due to the influence of the increase in capacity, the ECC circuit unit 3 is added to improve the reliability. It becomes possible to make it.
[0037]
Further, according to the present embodiment, when the CPU 7 writes information data in the flash memory 2 in advance, the controller 4 holds the information data output by the CPU 7 on the data bus by the W latches 6U and 6L, and the ECC circuit unit. 3 is stored in the flash memory 2 together with the inspection data generated by the CPU 3, the information data and the inspection data can be stored in the flash memory 2 even when the CPU 7 and the flash memory 2 have different data bus sizes. .
[0038]
Further, according to the present embodiment, the flash memory 2, the ECC circuit unit 3, the controller 4, the R buffer 5 and the W latch 6 constituting the memory circuit device 1 are formed on the same semiconductor substrate. The CPU 7 can handle the memory circuit device 1 in the same manner as a normal memory. And the increase in the circuit area by adding a function can be suppressed as much as possible.
[0039]
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
A one-chip control LSI may be configured by forming the CPU 7 and the memory circuit device 1 on the same semiconductor substrate.
The memory circuit device is not limited to one in which each component is formed on the same semiconductor substrate, and each may be configured on a normal circuit board (printed board or the like) with a discrete IC. At this time, if the storage circuit unit is configured by flash memory and the flash memory is configured to be detachable from the circuit board by using a socket or the like, writing of information data and inspection data to the flash memory is performed by a ROM. You may go with a writer. In this case, a configuration corresponding to the W latches 6U and 6L for writing is not necessary .
[0040]
The data bus size is not limited to the above embodiment. For example, when the bus size of the CPU 7 is 16 bits, the bus size of the flash memory 2 may be 32 bits.
The flash memory 2 is not limited to the flash memory 2 and may be an EEPROM or a DRAM. When the CPU rewrites the data in the memory circuit unit as in the case of using a DRAM, a read-modify-write cycle is performed at the time of data writing to read 16-bit data, and either one of the 8 bits is read. New inspection data may be generated in a state where the data is replaced with data output by the CPU and written back to the storage circuit unit.
Further, even when a 1-bit error is detected during the read cycle, the corrected data value may be written back by performing a read modify write cycle.
Means for notifying the outside when the frequency of occurrence of these errors exceeds a certain level by supplying a detection signal of 1-bit error or 2-bit error output by the ECC circuit unit 3 to the CPU 7 (for example, LED ) To prompt the user to replace the memory circuit device 1 or the flash memory 2 or the memory circuit unit corresponding thereto.
[Brief description of the drawings]
FIG. 1 is a functional block diagram showing an electrical configuration of a memory circuit device according to an embodiment of the present invention.
1 is a memory circuit device, 2 is a flash memory (memory circuit unit), 3 is an ECC circuit unit (error correction circuit unit), 4 is a controller (access control unit), 5U and 5L are buffers (access control units), 6U, 6L indicates a latch (access control unit), and 7 indicates a CPU.

Claims (5)

A storage circuit device that is accessed by a CPU with a constant data bus size,
A storage circuit configured to be accessed with a bus size that is a multiple of the data bus size;
When the information data stored in the storage circuit unit is read, the inspection data generated and stored corresponding to the information data is simultaneously read to detect whether the information data has an error. An error correction circuit unit that corrects the error when a correctable error is detected;
When the CPU tries to read information data from the storage circuit unit, the CPU reads the information data from the storage circuit unit with a multiple bus size including the information data, and the CPU reads from the data. An access control unit that controls to select and output information data to be output on the data bus of the CPU ,
The access control unit delays the timing of an acknowledge signal output to the CPU until data correction processing by the error correction circuit unit is completed . The access control unit holds information data that the CPU outputs on the data bus when the CPU intends to newly write information data to the storage circuit unit, and sets the data bus size of the storage circuit unit. 2. The storage circuit device according to claim 1, wherein when the same information data is held, the information circuit and the inspection data generated by the error correction circuit unit are stored in the storage circuit unit. The access control unit, when the CPU tries to rewrite information data stored in the storage circuit unit, executes a read-modify-write cycle for the storage circuit unit. 3. The memory circuit device according to 1 or 2. The memory circuit device according to claim 1, wherein the memory circuit unit includes a flash memory. 5. The memory circuit device according to claim 1, wherein the memory circuit unit, the error correction circuit unit, and the access control unit are formed on the same semiconductor substrate.

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