JP2001337866A - Storage circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage circuit device which can supress an increase in capacity of a storage circuit division when an error checking and correction circuit division is provided. SOLUTION: A flash memory 2 is composed to be able to access by 16-bit to an 8-bit data bus size of a CPU 7, a controller 4 reads out data by 16-bit from the flash memory 2 when the CPU 7 reads out data from the flash memory 2, and R latchs 5U, 5L select data which the CPU 7 intends to read out from the data to output them on a data bus of the CPU 7. 5-bit checked data corresponding to the 16-bit information data is also read out from the flash memory 2 for correcting by an ECC circuit division 3 when a 1-bit error occurs in the information data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage circuit device which is accessed by a CPU with a fixed data bus size, and detects a correctable error when stored data is read out, and detects the error. And an error correction circuit for correcting the error.

[0002]

2. Description of the Related Art For example, in a memory system in which a CPU reads data stored in a memory such as a DRAM, an error (a so-called soft error) can occur randomly when α rays enter a memory cell of the DRAM. There is. Therefore, when high reliability is required for such a memory system, ECC (Error Chcking a
nd Correcting) circuit may be added.

The ECC circuit generates a plurality of check data (syndrome bits) by taking an exclusive OR of a certain combination of the data bits when the CPU reads data from the memory. The generated syndrome bit is stored at the same address in the memory as the data.

When the CPU reads data (referred to as information data) from the memory, the inspection data generated corresponding to the information data is also read at the same time. At this time, the ECC circuit generates an error code from the read information data and the inspection data, and detects whether or not the information data has an error based on the value of the error code. When a correctable 1-bit error is detected, the error is corrected. Further, it is possible to detect that an error of two bits or more has occurred in the read data.

[0005]

When the ECC function as described above is added to a memory system, an extra memory capacity is required to store test data. For example, when test data is generated with 5 bits for an information data bus size of 16 bits (2 bytes), when the data bus size becomes 32 bits (4 bytes), the test data is generated with 6 bits. Therefore, there has been a problem that the system is increased in size due to an increase in the capacity and the cost is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a storage circuit device capable of suppressing an increase in the capacity of a storage circuit unit when an error correction circuit unit is provided. It is in.

[0007]

According to the storage circuit device of the present invention, the storage circuit unit is accessed with a bus size that is a multiple of the data bus size when the CPU accesses the storage circuit unit. And an error correction circuit unit for performing error correction on the storage circuit unit. When the CPU attempts to read the information data from the storage circuit unit, the access control unit reads the information data from the storage circuit unit with a multiple bus size including the data, and the CPU reads the information data from the information data. The data to be read is selected and output on the data bus of the CPU.

That is, the number of bits of the check data generated by the error correction circuit unit increases by one bit when the number of bits of the information data (referred to as data other than the check data, which is actually required) is doubled. The total number of bits of test data generated for the same information data capacity decreases as the data bus size for writing and reading increases.

For example, if the bus size of information data is 1 byte (B) and the number of words is W, the capacity is B ×
W. Here, assuming that the number of bits of the test data generated for one byte by the error correction circuit unit is s, the capacity required for the test data is s × W. If the bus size of the information data is ^2x bytes (x is a natural number), the number of words is W / ^2x , and the number of bits required for the test data increases by "x". s + x) × W / 2 ^x .

In this case, since x is added to the coefficient of W in the numerator, the denominator increases by 2 to the power of x, so that the capacity required for the inspection data is surely reduced. Therefore, claim 1
Thus, even when the error correction circuit section is provided to improve the reliability of the information data stored in the storage circuit section, the capacity required for the storage circuit section is reduced as compared with the related art, and the circuit area is reduced. Can be reduced and the whole can be made small, and the manufacturing cost can be reduced.

According to the storage circuit device of the second aspect, the access control unit holds the information data output from the CPU on the data bus when the CPU attempts to newly write information data to the storage circuit unit. I do. Then, when information data equal to the data bus size of the storage circuit unit is held, the information data and the inspection data generated by the error correction circuit unit are stored in the storage circuit unit.

That is, when the CPU attempts to newly write information data to the storage circuit unit in a state where no information data is stored, the access control unit sets the CP.
U holds information data output on the data bus for each address. Then, if information data equal to the data bus size of the storage circuit section is held, the corresponding check data is generated by the error correction circuit section, so that the data bus size of the CPU and that of the storage circuit section are different. Also, the information data and the inspection data can be stored in the storage circuit unit.

According to the storage circuit device of the third aspect, the access control unit executes a read-modify-write cycle when the CPU attempts to rewrite the information data stored in the storage circuit unit. That is, the information data is temporarily read from the storage circuit unit using the address including the data part to be rewritten by the CPU, and the data part output by the CPU is replaced, so that the error correction circuit unit can check the test data for the required data bus size. Can be generated.

According to the storage circuit device of the fourth aspect, the storage circuit unit is constituted by a flash memory. Conventionally, an error correction function is generally added to improve the reliability of a memory such as a DRAM. In recent years, flash memories are often used as program memories of CPUs, in which case rewriting is performed relatively frequently in a development stage or the like. Then, there is a possibility that a variation occurs in the threshold voltage VT of each cell transistor, and there is a possibility that an error occurs in data due to the variation. Therefore, even when the storage circuit section is configured by a flash memory, it is effective to add the error correction circuit section to improve the reliability.

According to the storage circuit device of the fifth aspect, the storage circuit unit, the error correction circuit unit, and the access control unit are formed on the same semiconductor substrate. That is, the error correction circuit unit and the access control unit are configured as a one-chip IC built in together with the storage circuit unit, and the CPU connected outside thereof treats the storage circuit device as a normal memory. It becomes possible. Therefore, an increase in the circuit area due to the addition of the function can be suppressed as much as possible.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram showing an electrical configuration of the storage circuit device. Storage circuit device 1
Are a flash memory (storage circuit unit) 2, an ECC circuit unit (error correction circuit unit) 3, a controller (access control unit) 4, a read buffer (hereinafter referred to as an R buffer, an access control unit) 5U, 5L, and Write latches (hereinafter referred to as W latches, access control units) 6U, 6L
And these are formed on the same semiconductor substrate and configured as a one-chip IC.

A CPU 7 is provided outside the storage circuit device 1.
Is connected. The data bus size of the CPU 7 is 8 bits, and the 8-bit data bus (D7 to D0)
Are connected to the storage circuit device 1.

The flash memory 2 is a rewritable nonvolatile storage means, which can erase data in block units and rewrite data in page units. The capacity of the flash memory 2 has a 16-bit × 64-word configuration of 1 k bits as a storage area for the information data, and a 5-bit test data generated by the ECC circuit unit 3 based on the value of the information data. The storage area has 320 bits of 5 bits × 64 words. The flash memory 2 includes a row selection circuit 2L and a column selection circuit 2C for selecting memory cells arranged in a matrix based on addresses output from the CPU.

Here, if 1 k bits are configured as 8 bits (1 byte) .times.128 words and addresses are assigned, there are 7 bits A6 to A0 (127 to 0). On the other hand, since the data bus size of the flash memory 2 is 16 bits (2 bytes), the upper 6 bits (A6 to A1) of the address are given to the flash memory 2.

In the flash memory 2, the control program of the CPU 7 stores W latches 6U and 6L as information data.
Via the CPU 7 in advance. That is,
The controller 4 outputs a latch signal and an enable signal to the W latches 6U and 6L, so that the CPU 7 sets A0 = 0.
When the information data to be written to the address of
The 8-bit data is latched by the W latch 6L,
When the information data to be written to the address of A0 = 1 is output, the 8-bit data is latched by the W latch 6U. Then, the W latches 6U and 6L are enabled to cause the ECC circuit unit 3 to generate 5-bit inspection data, and the information data and the inspection data are simultaneously written into the flash memory 2. The CPU 7 reads out and executes a control program stored in the flash memory 2 to control an external device (not shown).

Each of the R buffers 5U and 5L has an 8-bit configuration, and is used to select data to be output on an 8-bit data bus of the CPU 7 when the CPU 7 reads information data from the flash memory 2 (details). Will be described later). That is, the input side of the R buffer 5U is connected to the upper side (D15 to D15) of the 16-bit data bus of the flash memory 2.
8), and the input side of the R buffer 5L is connected to the lower side (D7 to D0) of the same data bus. The output sides of the R buffers 5U and 5L are
It is connected to bit data buses (D7 to D0).

When information data is read from the flash memory 2 by the CPU 7, the controller 4
The inspection data is stored in the flash memory 2 together with the information data.
Read from Then, when an error code is generated from the read information data and the inspection data, the ECC circuit unit 3 detects whether or not the information data has an error. That is, if the value of the error code is "0", there is no error in the information data. If the error code is other than "0" and matches an error code defined in advance, a one-bit error (one-bit error) has occurred in the information data. This means that an error of two bits or more (two-bit error) has occurred in the data.

When the ECC circuit unit 3 detects a one-bit error as described above, the ECC circuit unit 3 corrects the error (inverts the bit value). Further, only a 2-bit error can be detected.

The controller 4 is supplied with an address output from the CPU 7 and various control signals. The controller 4 outputs control signals to the flash memory 2 and the ECC circuit unit 3,
An enable signal is output to R buffers 5U and 5L. Further, when the CPU 7 performs a read cycle for the storage circuit device 1, an acknowledge signal (ACK) is output at an appropriate timing.

The controller 4 is supplied with a 1-bit error detection signal ERR1 from the ECC circuit unit 3. When a 1-bit error is detected in the information data, the ECC circuit unit 3 corrects the data. Until the processing is completed, the output timing of the acknowledge signal is delayed.

Next, the operation of this embodiment will be described.
When the CPU 7 performs a read cycle for the storage circuit device 1, the cycle proceeds as follows. However, not all the signals actually used are described, and only a portion related to the gist of the present invention will be described.

<When there is no error in the information data> When the CPU 7 outputs the addresses A6 to A0 and starts the read cycle, the controller 4 decodes the addresses and determines that the read access is to the storage circuit device 1. . Then, a read control signal (Chip Enable, Output Enable, etc.) is output to the flash memory 2.

Then, the upper 6 bits (A6 to A1) of the address are given from the flash memory 2 to 16 bits.
The bit information data is read. The ECC circuit unit 3 performs error detection based on the 16-bit information data read from the flash memory 2 and the 5-bit inspection data.

If the ECC circuit unit 3 does not output the one-bit error detection signal ERR1 within a predetermined period, the controller 4 outputs an enable signal to one of the R buffers 5U and 5L according to the value of the address A0. . That is, CPU
If the access address of X7 is XXXXX0 (binary), the R buffer 5L is enabled and the data on the lower side (D7 to D0) of the data bus of the flash memory 2 is transferred to the 8-bit data bus of the CPU 7. Is output to If the access address is XXXXXX1, the R buffer 5U is enabled and the data on the upper side (D15 to D8) of the data bus of the flash memory 2 is transferred to the CPU.
7 to the 8-bit data bus.

Subsequently, the controller 4 outputs an acknowledge signal to the CPU 7. When recognizing the acknowledge signal, the CPU 7 latches and reads the data read from the storage circuit device 1. Then, the output of the address is stopped, and the read cycle ends.

<In the case where there is an error in the information data> is the same as in the case where there is no error.
The C circuit unit 3 outputs a one-bit error detection signal ERR1 within a predetermined period.
Is output. Then, the ECC circuit unit 3 corrects the data value in which the one-bit error has occurred. Then, the controller 4 delays the timing of outputting the acknowledgment signal to the CPU 7 by an amount of time during which the ECC circuit unit 3 performs error correction, and outputs the delayed signal.

In the above, the operation of the ECC circuit unit 3 is well known, and the timing charts for error detection and error correction do not substitute those disclosed in the data sheet of the IC for ECC. .

Here, since the number of bits is 5 and the number of words is 64, the capacity required for storing the inspection data in the flash memory 2 is 5 × 64 = 320 bits. Further, when the data bus size of the storage circuit unit is set to the same 8 bits for the data bus size of the CPU 7 as in the related art, the number of words is 128 for 4 bits, so that 4 × 128 = 512 bits are required.

Accordingly, the total capacity reduction rate is (1024 + 320) / (1024 + 512) = 134
4/1536 = 12.5 (%). That is, the capacity of the flash memory 2 is about 12.5
This means that the percentage has been reduced.

As described above, according to this embodiment, the flash memory 2 is configured so that the data bus size of the CPU 7 is accessed by 16 bits with respect to 8 bits.
When the CPU 7 attempts to read data from the flash memory 2, the controller 4 reads data from the flash memory 2 in 16 bits, selects data to be read by the CPU 7 from those data,
The data is output to the data bus of PU7. In addition, the 5-bit inspection data corresponding to the 16-bit information data is also read from the flash memory 2, and when a 1-bit error occurs in the information data, the ECC circuit unit 3 corrects the error.

Accordingly, even when the reliability of the information data stored in the flash memory 2 is to be improved by providing the ECC circuit section 3, the capacity required for the flash memory 2 is reduced as compared with the conventional case, and the circuit area is reduced. As a result, the entire device can be configured to be small, and the manufacturing cost can be reduced. In addition, when writing to the flash memory 2 is performed at a high frequency or when there is a possibility that the reliability may be reduced due to the effect of the increase in capacity, the reliability is improved by adding the ECC circuit unit 3. It is possible to do.

According to this embodiment, the controller 4
When the CPU 7 writes information data in the flash memory 2 in advance, the CPU 7 holds the information data output on the data bus by the W latches 6U and 6L,
Since the data is stored in the flash memory 2 together with the inspection data generated by the circuit unit 3, even if the data bus sizes of the CPU 7 and the flash memory 2 are different,
Information data and inspection data can be stored in the flash memory 2.

Further, according to the present embodiment, the storage circuit device 1
Is formed on the same semiconductor substrate, so that a CPU connected to the outside thereof is formed.
7 enables the storage circuit device 1 to be handled in the same manner as a normal memory. Further, an increase in circuit area due to the addition of the function can be suppressed as much as possible.

The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible. A one-chip control LSI may be configured by forming the CPU 7 and the storage circuit device 1 on the same semiconductor substrate. The storage circuit device is not limited to one in which each component is formed on the same semiconductor substrate, and each may be formed on a normal circuit board (such as a printed circuit board) using a discrete IC. At this time, when the storage circuit section is configured by a flash memory and the flash memory is configured to be detachable from a circuit board by using a socket or the like, writing of information data and inspection data to the flash memory is performed by using a ROM. You may go with a writer. In that case, a configuration corresponding to the W latches 6U and 6L for writing becomes unnecessary. For example, when high speed is not required for access to the storage circuit device 1, the output timing of the acknowledgment signal returned from the controller 4 to the CPU 7 includes a time necessary for performing 1-bit error correction in advance. Is also good. In that case, the ECC circuit unit 3
Does not need to be supplied to the controller 4.

The data bus size is not limited to the above embodiment.
For example, when the bus size of the CPU 7 is 16 bits, the bus size of the flash memory 2 may be 32 bits. The flash memory 2 is not limited to the flash memory 2 and may be an EEPROM or a DRAM.
Also, when the CPU sometimes rewrites data in the storage circuit section, as in the case of using a DRAM, a read-modify-write cycle is performed at the time of writing data, and the CPU performs one cycle of writing.
New inspection data may be generated with the 6-bit data read out and one of the 8-bit data replaced with the data output by the CPU, and written back to the storage circuit unit. Further, even when a one-bit error is detected during a read cycle, a read-modify-write cycle may be performed to write back the corrected data value. A means for giving a detection signal of a one-bit error or a two-bit error output from the ECC circuit unit 3 to the CPU 7 to notify the CPU 7 when the frequency of occurrence of these errors becomes higher than a certain value (for example, an LED) ) May be provided to urge the user to replace the storage circuit device 1 or the flash memory 2 or a storage circuit unit corresponding thereto.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating an electrical configuration of a storage circuit device according to an embodiment of the present invention.

[Explanation of symbols]

1 is a storage circuit device, 2 is a flash memory (storage circuit unit), 3 is an ECC circuit unit (error correction circuit unit), 4 is a controller (access control unit), 5U and 5L are buffers (access control unit), 6U, 6L denotes a latch (access control unit), and 7 denotes a CPU.

Claims (5)

[Claims] 1. A storage circuit device that is accessed by a CPU with a fixed data bus size, wherein the storage circuit unit is configured to be accessed by a bus size that is a multiple of the data bus size. When the information data stored in the storage circuit portion is read, the inspection data generated and stored corresponding to the information data is simultaneously read to detect whether or not the information data has an error, An error correction circuit that corrects the error when a correctable error is detected; and when the CPU attempts to read information data from the storage circuit, the error correction circuit has a multiple bus size including the information data. The information data is read out from the storage circuit section, and the information data which the CPU is about to read is selected from the data, and the information data is read from the data bus of the CPU. A storage circuit device comprising: an access control unit that controls output to the storage circuit. 2. The information processing apparatus according to claim 2, wherein the access control unit holds information data output from the CPU on a data bus when the CPU attempts to newly write information data to the storage circuit unit. 2. The storage circuit according to claim 1, wherein when the information data equal to the data bus size is held, the information data and the inspection data generated by the error correction circuit are stored in the storage circuit. apparatus. 3. The access control unit executes a read-modify-write cycle for the storage circuit unit when the CPU attempts to rewrite information data stored in the storage circuit unit. The storage circuit device according to claim 1 or 2, wherein: 4. The storage circuit device according to claim 1, wherein said storage circuit unit is configured by a flash memory. 5. The storage circuit according to claim 1, wherein said storage circuit unit, said error correction circuit unit, and said access control unit are formed on the same semiconductor substrate. apparatus.