JP4335234B2 - Analog / digital conversion circuit - Google Patents

Description

  The present invention relates to an analog / digital conversion circuit capable of avoiding the influence of noise generated according to the loop characteristics of an analog / digital conversion circuit on an input signal of a complete zero level on an output signal in an audible band. .

  For analog / digital conversion circuits that convert analog signals to digital signals, which are mounted on audio equipment, etc., noise generated according to the loop characteristics of the analog / digital conversion circuit (hereinafter referred to as the analog / digital conversion circuit) However, the influence of such noise on the output signal in the audible band is a problem.

  As countermeasures against the above-described cyclic noise, two methods as described below have been conventionally taken.

  One method is to mix signals outside the band of the analog / digital conversion circuit as dither. For example, a signal having a large frequency of about 100 KHz is mixed as a dither for an analog / digital conversion circuit having a band of 20 KHz. Thus, even when the input signal is at a complete “0” level, it is the same as when the input signal is 100 KHz. Therefore, the cyclic noise component can be pushed out of the audible band.

  Another method is to add a DC offset to the input signal. For example, a DC offset is added to the input signal up to about 100 KHz for an analog / digital conversion circuit with a band of 20 KHz. Thus, even when the input signal is at a complete “0” level, it is the same as when the input signal is 100 KHz. Therefore, the cyclic noise component can be pushed out of the audible band.

  However, in the above-described method of mixing dither, it is necessary to generate dither and to remove dither at the output stage of the analog / digital conversion circuit. A circuit for generating and removing such a dither needs to be provided in the analog / digital conversion circuit, which causes a problem that the circuit design of the analog / digital conversion circuit becomes complicated.

  On the other hand, in the method of adding the DC offset to the input signal, it is necessary to provide a high-pass filter in the output stage of the analog / digital conversion circuit in order to eliminate the influence of the DC offset in the output stage of the analog / digital conversion circuit. Therefore, similarly to the above-described method of mixing dither, there arises a problem that the circuit design of the analog / digital conversion circuit becomes complicated.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide an analog / digital that can reduce the influence of cyclic noise on an output signal in an audible band with a simple circuit design. It is to provide a conversion circuit.

In order to solve the above problems, the analog / digital conversion circuit of the present invention drives the high-side output element and the low-side output element alternately based on the analog / digital-converted digital signal to thereby generate the digital signal. Analog / digital having a balance adjusting means capable of setting the time for turning on the high-side output element to be different from the time for turning on the low-side output element. A conversion circuit, characterized in that the balance adjustment means is used to bring a DC offset into the same state as any of the high-side output element and the low-side output element .

Further, in the analog / digital conversion circuit of the present invention, in addition to the above-described configuration, the balance adjusting unit drives the high-side output element and the low-side output element at different potentials, so that the high-side output element and the low-side output element It is preferable that one of the low-side output elements is in the same state as a state where a DC offset is applied.

Further, in the analog / digital conversion circuit of the present invention, in addition to the above configuration, the balance adjusting means is in the same state as a state where a DC offset is applied to either the high side output element or the low side output element. Thus, it is preferable to push the spectrum generated by the cyclic noise generated according to the loop characteristics of the analog / digital conversion circuit to the input signal of 0 level completely outside the audible band.

  That is, the analog / digital conversion circuit amplifies the digital signal by alternately driving the high-side output element and the low-side output element using switching means based on the analog / digital converted digital signal. Output.

  By the way, in the analog / digital conversion circuit, there is a problem that the noise (cyclic noise) generated according to the loop characteristics of the analog / digital conversion circuit with respect to a complete zero level input signal has an influence on the output signal in the audible band. Has been.

  Therefore, in the present invention, in particular, by setting the time for turning on the high-side output element to be different from the time for turning on the low-side output element, a completely zero-level input signal can be obtained. On the other hand, the spectrum generated by the cyclic noise generated according to the loop characteristics of the analog / digital conversion circuit is pushed out of the audible band.

According to the above configuration, the time for turning on the high-side output element can be set different from the time for turning on the low-side output element. That is, the high-side output element and the low-side output element can be driven with different potentials. Therefore, the same state as that in which a DC offset is applied to either the high-side output element or the low-side output element can be obtained.

  As a result, the spectrum generated by the cyclic noise can be pushed out of the audible band. The balance between the time for turning on the high-side output element and the time for turning on the low-side output element can be adjusted inside the analog / digital conversion circuit. There is no need to provide a special circuit in the input stage.

  Therefore, it is possible to provide an analog / digital conversion circuit capable of reducing the influence of cyclic noise on an audible band output signal with a simple circuit design.

The analog / digital converter circuit of the present invention, in addition to the above structure, the upper Symbol balance adjusting means, an input terminal and an output terminal of the plus side, with and an input terminal and an output terminal on the negative side, Between the positive side input terminal and the output terminal, and between the negative side input terminal and the output terminal, a resistor, a capacitor connected in series with the resistor, and a feedback connection to the resistor are connected. Each circuit having a diode is connected, while the time constant determined by the resistor and the capacitor connected between the positive input terminal and the output terminal, and the negative side It is preferable that a time constant determined by the resistor and the capacitor connected between the input terminal and the output terminal is different .

  According to the above configuration, the balance adjusting unit forms an integrating circuit including a resistor and a capacitor, and a diode is feedback-connected to the resistor. Also, a time constant determined by a resistor and a capacitor connected between the positive input terminal and the output terminal in the balance adjusting means, and a connection between the negative input terminal and the output terminal in the balance adjusting means. The time constant determined by the resistance and the capacitor is different.

  Therefore, when a clock pulse at the positive input terminal of the balance adjusting means is input, the rising timing is delayed by a time ΔT1 from the clock pulse at the positive output terminal, and the falling timing is the same as the clock pulse. A clock pulse is output.

  Further, a clock pulse obtained by inverting the clock pulse input to the positive input terminal is input to the negative input terminal. Then, the negative output terminal outputs a clock pulse whose rising edge is delayed by the time ΔT2 from the inverted clock pulse and whose falling timing is the same as that of the inverted clock pulse.

  Here, the time constant determined by the resistor and the capacitor connected between the positive input terminal and the output terminal, and the resistor and the capacitor connected between the negative input terminal and the output terminal Since the time constant to be determined is different, the above ΔT1 and ΔT2 have different values.

  That is, the time during which the voltage is in the high state differs between the clock pulse output from the plus output terminal of the balance adjusting unit and the clock pulse output from the minus output terminal. Therefore, the switching means uses the clock pulse output from the positive output terminal of the balance adjusting means and the clock pulse output from the negative output terminal as signals for driving the high-side output element and the low-side output element. In this case, the time for turning on the high side output element and the time for turning on the low side output element can be set differently.

Therefore, it is possible to set the same state as a state where a DC offset is applied to either the high-side output element or the low-side output element and push the spectrum generated by the cyclic noise out of the audible band. Further, the configuration for avoiding the cyclic noise can be realized by a simple configuration in which the balance adjusting means is configured by a resistor, a capacitor, and a diode.

  As a result, it is possible to provide an analog / digital conversion circuit capable of reducing the influence of cyclic noise on an audible band output signal with a simpler circuit design.

The analog / digital converter circuit of the present invention, in addition to the above structure, the upper Symbol balance adjusting means, an input terminal and an output terminal of the plus side, with and an input terminal and an output terminal on the negative side, While delaying the rising edge of the digital signal input to the positive input terminal by time ΔT1, the digital signal is output to the positive output terminal without delaying the falling edge of the digital signal, and the negative input terminal It is preferable that the rising edge of the digital signal input to is delayed by a time ΔT2, which is a time different from ΔT1, while the falling edge of the digital signal is output to the negative output terminal without delaying .

According to the above configuration, the clock pulse at the positive input terminal of the balance adjustment unit is input, and the clock pulse obtained by inverting the clock pulse is input to the negative input terminal. The clock pulse output from the output terminal and the clock pulse output from the negative output terminal have different times during which the voltage is in the high state.

  Therefore, the switching means uses the clock pulse output from the positive output terminal of the balance adjusting means and the clock pulse output from the negative output terminal as signals for driving the high-side output element and the low-side output element. In this case, the time for turning on the high side output element and the time for turning on the low side output element can be set differently.

Therefore, it is possible to set the same state as a state where a DC offset is applied to either the high-side output element or the low-side output element and push the spectrum generated by the cyclic noise out of the audible band.

  Therefore, it is possible to provide an analog / digital conversion circuit capable of reducing the influence of cyclic noise on an audible band output signal with a simple circuit design.

As described above, the analog / digital conversion circuit of the present invention amplifies the digital signal by alternately driving the high-side output element and the low-side output element based on the analog / digital converted digital signal. An analog / digital conversion circuit comprising switching means for outputting , and comprising balance adjusting means capable of setting the time for turning on the high-side output element to be different from the time for turning on the low-side output element In this case, the balance adjusting means is used to bring the DC offset into the same state as any of the high-side output element and the low-side output element .

According to said structure, it can be set as the same state as the state which gave DC offset to either the high side output element or the low side output element. As a result, the spectrum generated by the cyclic noise can be pushed out of the audible band.

  Also, the balance between the time for turning on the high-side output element and the time for turning on the low-side output element can be adjusted inside the analog / digital conversion circuit, and the output stage and input of the analog / digital conversion circuit can be adjusted. There is no need to provide a special circuit in the stage.

  Therefore, it is possible to provide an analog / digital conversion circuit capable of reducing the influence of cyclic noise on an audible band output signal with a simple circuit design.

  One embodiment of the present invention will be described with reference to FIGS. 1 to 3 as follows.

  As shown in FIG. 2, the analog / digital conversion circuit 1 of the present embodiment includes an analog / digital converter (hereinafter simply referred to as an AD converter) 2, a dead time control circuit (balance adjustment means) 3, a level shifter, and the like. A circuit 4, a first gate driver circuit (switching means, one-side switching means) 5, a second gate driver circuit (switching means, the other-side switching means) 6, and a plurality of output FETs (Field Effect Transistors) 7).

  The AD converter 2 modulates an analog signal differentially input from the outside into a PDM (Pulse Duration Modulation) digital signal. The dead time control circuit 3 adjusts the rising timing and falling timing of the pulse of the PDM digital signal input from the AD converter 2 and outputs the adjusted signal to the level shift circuit 4. The detailed configuration of the dead time control circuit 3 will be described later.

  The level shift circuit 4 shifts the level of the output signal from the dead time control circuit 3. Further, the plus output from the level shift circuit 4 is inputted to the High side of the first gate driver circuit 5 described later and the Low side of the second gate driver circuit 6 described later. On the other hand, the minus output from the level shift circuit 4 is input to the Low side of the first gate driver circuit 5 and the High side of the second gate driver circuit 6.

  The first gate driver circuit 5 drives output FETs (one-side high-side output element, one-side low-side output element) 7... Connected to the high-side output and the low-side output, respectively. Similarly, the second gate driver circuit 6 drives output FETs (the other side high side output element, the other side low side output element) 7... Connected to the high side output and the low side output, respectively. .

  With the above configuration, the analog / digital conversion circuit 1 outputs the analog signal input to the AD converter 2 to the output FET 7... Connected to the first gate driver circuit 5 and the output connected to the second gate driver circuit 6. The digital signals are output from the FETs 7. A high frequency component is removed from the digital signal from the output FETs 7 by the low-pass filter 8, and the digital signal is output to the external load 9.

  Next, a detailed configuration of the dead time control circuit 3 which is a feature of the present invention will be described.

  As shown in FIG. 1, a resistor R1, a diode D1, a capacitor C1, and an AND gate U1 are connected between a plus side input and a plus side output in the dead time control circuit 3. Similarly, a resistor R2, a diode D2, a capacitor C2, and an AND gate U2 are connected between the negative side input and the negative side output in the dead time control circuit 3.

  Note that the circuit configuration between the plus side input and the plus side output in the dead time control circuit 3 and the circuit configuration between the minus side input and the minus side output are the same. A circuit configuration between the input and the plus side output will be described as a representative.

  Between the positive side input and the positive side output in the dead time control circuit 3, the diode D1 is feedback-connected to the resistor R1. One contact of the capacitor C1 is connected between the output of the resistor R1 and the AND gate U1. On the other hand, the other contact of the capacitor C1 is grounded.

  With the above configuration, the capacitor C1 is charged with a response characteristic determined by the time constant R1C1 with respect to the digital signal input from the AD converter 2 to the plus side of the dead time control circuit 3. On the other hand, when the capacitor C1 is discharged, the discharge current passes through the diode D1, so that the discharge is instantaneously performed.

  That is, as shown in FIG. 3, when comparing the plus-side input waveform and the plus-side output waveform in the dead time control circuit 3, the rise of the output waveform is delayed by a certain time with respect to the rise of the input waveform. Become. On the other hand, since the capacitor C1 is discharged instantaneously, when the plus-side input waveform and the output waveform are compared, the falling edge has the same timing.

  The rise time lag in the input / output waveform is referred to as dead time, and is shown as ΔT1 in FIG. This dead time ΔT1 is determined by the time constant R1C1 of the circuit connecting the positive input / output in the dead time control circuit 3.

  Similarly, when the input waveform on the negative side is compared with the output waveform, the rise of the output waveform is delayed by the dead time ΔT2 with respect to the input waveform, and the fall of the output waveform has the same timing as the fall of the input waveform. The dead time ΔT2 is determined by the time constant R2C2 of the circuit connecting the negative input / output in the dead time control circuit 3.

  During the period of the dead time ΔT1, both the plus side output and the minus side output of the dead time control circuit 3 are at the low level. Similarly, during the period of dead time ΔT2, both the positive and negative outputs are at the low level. That is, during the dead times ΔT1 and ΔT2, the High-side output FETs 7 and the Low-side output FETs 7 of the first and second gate driver circuits 5 and 6 are both turned off.

  When the dead times ΔT1 and T2 are not provided as described above, the rising and falling timings of the input waveform and the output waveform to the dead time control circuit 3 are the same, and the rising and falling delays of the output FETs 7 are delayed. Thus, the timing for simultaneously turning on the High-side output FET 7 and the Low-side output FET 7 is generated. Thus, if the high-side output FET 7 and the low-side output FET 7 are simultaneously turned on, the circuit elements are destroyed, which is not preferable.

  Further, ΔT1 and ΔT2 are set to different values in order to avoid cyclic noise. More specifically, the time constant R1C1 for determining ΔT1 and the time constant R2C2 for determining ΔT2 are set to different values. Hereinafter, the reason why the time constants R1C1 and R2C2 are set to different values will be described.

  When ΔT1 and ΔT2 are the same value, the time constant R1C1 and the time constant R2C2 are the same value. In this case, the voltage input on the plus side to the dead time control circuit 3 is integrated by the resistor R1 and the capacitor C1, and then output at a potential which is ½ of the input voltage. Similarly, the voltage input to the negative side of the dead time control circuit 3 is integrated by the resistor R2 and the capacitor C2, and then output at a potential that is ½ of the input voltage. Note that, as described above, the reason why the output voltage is output at a potential which is ½ of the input voltage is that the output voltage becomes an average value of the input voltage.

  That is, the plus side output and the minus side output from the dead time control circuit 3 are the level shift circuit 4 (FIG. 2), the first gate driver circuit 5 (FIG. 2), and the second gate driver circuit 6 (FIG. 2). ), The high-side output FETs 7... And the low-side output FETs 7... Are driven at the same potential.

  In such a case, the cyclic noise is output at the same potential from the High-side output FETs 7... And the Low-side output FETs 7.

  However, when ΔT1 and ΔT2 are different values, the plus side output and the minus side output of the dead time control circuit 3 have different potentials. Therefore, the plus side output and the minus side output from the dead time control circuit 3 are the level shift circuit 4 (FIG. 2), the first gate driver circuit 5 (FIG. 2), and the second gate driver circuit 6 (FIG. 2) in the subsequent stage. ), The high-side output FETs 7 and the low-side output FETs 7 are driven at different potentials.

  That is, when ΔT1 and ΔT2 are different values, the state is the same as when a DC offset is applied to either the high-side output FET 7 or the low-side output FET 7. Therefore, the spectrum generated by the cyclic noise can be pushed out of the audible band.

  As described above, the analog / digital conversion circuit 1 according to the present embodiment alternately drives the high-side output FET 7 and the low-side output FET 7 on the basis of the analog / digital converted digital signal. In the analog / digital conversion circuit including the first gate driver circuit 5 or the second gate driver circuit 6 that amplifies and outputs the digital signal, the time for turning on the High-side output FET 7 and turning on the Low-side output FET 7 are turned on. A dead time control circuit 3 is provided for adjusting the balance with the time for setting.

  According to the above configuration, the dead time control circuit 3 can set the time for turning on the High-side output FET 7 to be different from the time for turning on the Low-side output FET 7. That is, the high-side output FET 7 and the low-side output FET 7 can be driven at different potentials. Therefore, a DC offset can be applied to either the high-side output FET 7 or the low-side output FET 7.

  As a result, the spectrum generated by the cyclic noise can be pushed out of the audible band. The balance between the time for turning on the High-side output FET 7 and the time for turning on the Low-side output FET 7 can be adjusted inside the analog / digital conversion circuit 1. There is no need to provide a special circuit in the output stage or the input stage.

  Therefore, it is possible to provide the analog / digital conversion circuit 1 capable of reducing the influence of the cyclic noise on the audible band output signal with a simple circuit design.

  Further, the analog / digital conversion circuit 1 of the present embodiment includes a first gate driver circuit 5 that alternately drives the high-side output FET 7 and the low-side output FET 7 in the analog / digital conversion circuit 1 configured as described above. And a second gate driver circuit 6 for alternately driving the high-side output FET 7 and the low-side output FET 7, and a first gate driver circuit for inputting a signal for driving the high-side output FET 7. 5 is connected to an input to the second gate driver circuit 6 for inputting a signal for driving the low-side output FET 7, while a signal for driving the low-side output FET 7 is input. The second gate for inputting a signal for driving the input line to the first gate driver circuit 5 for driving the output FET 7 on the high side. The dead time control circuit 3 turns on the high-side output FET 7 in the first gate driver circuit 5 and turns on the low-side output FET 7 in the on-state. And the balance between the time for turning on the High-side output FET 7 and the time for turning on the Low-side output FET 7 in the second gate driver circuit 6 are adjusted.

  According to the above configuration, the time for turning on the High-side output FET 7 in the first gate driver circuit 5 by the dead time control circuit 3 is different from the time for turning on the Low-side output FET 7. Can be set. Similarly, the time for turning on the High-side output FET 7 in the second gate driver circuit 6 and the time for turning on the Low-side output FET 7 can be set differently.

  That is, in the first gate driver circuit 5, the high-side output FET 7 and the low-side output FET 7 can be driven at different potentials. Therefore, a DC offset can be applied to either the high-side output FET 7 or the low-side output FET 7 in the first gate driver circuit 5. Similarly, either the Low-side output FET 7 or the High-side output FET 7 in the second gate driver circuit 6 can be in a state where a DC offset is applied.

  As a result, the spectrum generated by the cyclic noise can be pushed out of the audible band. The balance between the time for turning on the High-side output FET 7 and the time for turning on the Low-side output FET 7 can be adjusted inside the analog / digital conversion circuit 1. There is no need to provide a special circuit in the output stage or the input stage.

  Further, input lines to the high-side output FET 7 in the first gate driver circuit 5 and the low-side output FET 7 in the second gate driver circuit 6 are connected, and the low-side output FET 7 in the first gate driver circuit 5. The input line to the high-side output FET 7 in the second gate driver circuit 6 is connected. Therefore, the four output elements can be driven by two input signals, and the circuit design can be simplified.

  Therefore, it is possible to provide the analog / digital conversion circuit 1 capable of reducing the influence of the cyclic noise on the audible band output signal with a simpler circuit design.

  In addition, in the analog / digital conversion circuit 1 of the present embodiment, the dead time control circuit 3 includes a plus-side input terminal and output terminal, a minus-side input terminal and output terminal, and a plus-side input terminal and output terminal. Between the input terminal and the output terminal and between the negative input terminal and the output terminal, a resistor R1 (R2), a capacitor C1 (C2) connected in series with the resistor R1 (R2), and a resistor A circuit having a diode D1 (D2) feedback-connected to R1 (R2) is connected to each other, while a resistor R1 and a capacitor C1 connected between an input terminal on the plus side and an output terminal And a time constant R2C2 determined by a resistor R2 and a capacitor C2 connected between the negative input terminal and the output terminal. It is different.

  According to the above configuration, the dead time control circuit 3 constitutes an integrating circuit composed of the resistor R1 (R2) and the capacitor C1 (C2), and the diode R1 (D2) is feedback-connected to the resistor R1 (R2). Has been. In addition, a time constant R1C1 determined by a resistor R1 and a capacitor C1 connected between a positive input terminal and an output terminal in the dead time control circuit 3, and a negative input terminal in the dead time control circuit 3 The time constant R2C2 determined by the resistor R2 and the capacitor C2 connected between the output terminals is different.

  Therefore, when the clock pulse at the positive input terminal of the dead time control circuit 3 is input, the rising timing is delayed by the time ΔT1 from the positive pulse to the positive output terminal, and the falling timing is the same as the clock pulse. A clock pulse is output.

  Further, a clock pulse obtained by inverting the clock pulse input to the positive input terminal is input to the negative input terminal. Then, the negative output terminal outputs a clock pulse whose rising edge is delayed by the time ΔT2 from the inverted clock pulse and whose falling timing is the same as that of the inverted clock pulse.

  Here, a time constant R1C1 determined by the resistor R1 and the capacitor C1 connected between the positive input terminal and the output terminal, and a resistor R2 connected between the negative input terminal and the output terminal. Since the time constant R2C2 determined by the capacitor C2 is different, the above ΔT1 and ΔT2 have different values.

  That is, the time during which the voltage is in a high state differs between the clock pulse output from the plus output terminal of the dead time control circuit 3 and the clock pulse output from the minus output terminal. Therefore, the clock pulse output from the plus output terminal of the dead time control circuit 3 and the clock pulse output from the minus output terminal are used to drive the high-side output FET 7 and the low-side output FET 7. Is output to the first gate driver circuit 5 or the second gate driver circuit 6 so that the time for turning on the High-side output FET 7 is different from the time for turning on the Low-side output FET 7. Can be set.

  Therefore, a DC offset is applied to either the High-side output FET 7 or the Low-side output FET 7, and the spectrum generated by the cyclic noise can be pushed out of the audible band. Further, a configuration for avoiding cyclic noise is realized by a simple configuration in which the dead time control circuit 3 is configured by a resistor R1 (R2), a capacitor C1 (C2), and a diode D1 (D2). Can do.

  As a result, it is possible to provide the analog / digital conversion circuit 1 that can reduce the influence of the cyclic noise on the audible band output signal with a simpler circuit design.

  The analog / digital conversion circuit 1 according to the present embodiment is the same as the analog / digital conversion circuit 1 having the above-described configuration. The dead time control circuit 3 includes a positive input terminal and an output terminal, a negative input terminal and an output. The digital signal input to the positive input terminal is delayed by the time ΔT1, and the digital signal output is output to the positive output terminal without delay. At the same time, the rising edge of the digital signal input to the minus side input terminal is delayed by a time ΔT2 which is a time different from the above ΔT1, while the falling edge of the digital signal is output to the plus side output terminal without delaying. To do.

  According to the above configuration, the dead time control circuit 3 is inputted by inputting the clock pulse at the positive input terminal of the dead time control circuit 3 and inputting the clock pulse obtained by inverting the clock pulse to the negative input terminal. The clock pulse output from the positive output terminal 3 and the clock pulse output from the negative output terminal have different times during which the voltage is in the high state.

  Therefore, the clock pulse output from the plus output terminal of the dead time control circuit 3 and the clock pulse output from the minus output terminal are used to drive the high-side output FET 7 and the low-side output FET 7. If the signal is output to the switching means, the time for turning on the High-side output FET 7 and the time for turning on the Low-side output FET 7 can be set differently.

  Therefore, a DC offset is applied to either the High-side output FET 7 or the Low-side output FET 7, and the spectrum generated by the cyclic noise can be pushed out of the audible band.

  Therefore, it is possible to provide the analog / digital conversion circuit 1 capable of reducing the influence of the cyclic noise on the audible band output signal with a simple circuit design.

  The analog / digital conversion circuit of the present invention includes an analog signal input unit, an AD conversion unit that converts the analog signal into a digital signal, and a pair of a high-side output element and a low-side output element. An analog / digital conversion circuit comprising: switching means for amplifying and outputting a signal output from the AD converter; and dead time control means for preventing a through current from flowing through the switching means. The time control means may be provided with a balance adjusting means for adjusting the balance of voltage application time applied to the high-side output element and the low-side output element.

  In the analog / digital conversion circuit according to the present invention, in the analog / digital conversion circuit having the above configuration, the switching means includes one output means for alternately outputting a high-side output element and a low-side output element, and a high-side output. And the other output means for alternately outputting the element and the low side output element, the high side output element of one output means, the low side output element of the other output means, and the high side output element of the other output means Alternatively, the output means may be balanced output switching means for amplifying and outputting the signal output from the AD conversion section by being alternately connected to the low side output element.

  The analog / digital conversion circuit according to the present invention may be configured such that the balance adjusting means uses a delay characteristic due to a capacitor and a resistor and an instantaneous response characteristic of a feedback diode. Good.

  In the analog / digital conversion circuit of the present invention, in the analog / digital conversion circuit having the above-described configuration, the balance adjusting means delays ΔT1 time at the rising edge of the positive input, and does not delay at the falling edge of the positive input. A configuration may be adopted in which a time difference is provided between ΔT1 and ΔT2, with a delay of ΔT2 time at the time of rising, and without delaying at the falling time of the negative input.

  The analog / digital conversion circuit of the present invention comprises switching means for amplifying and outputting the digital signal by alternately driving a high-side output element and a low-side output element based on the analog / digital converted digital signal. The analog / digital conversion circuit includes a balance adjustment unit that adjusts a balance between a time for turning on the high-side output element and a time for turning on the low-side output element. Also good.

  That is, the analog / digital conversion circuit amplifies the digital signal by alternately driving the high-side output element and the low-side output element using switching means based on the analog / digital converted digital signal. Output.

  By the way, in the analog / digital conversion circuit, there is a problem that the noise (cyclic noise) generated according to the loop characteristics of the analog / digital conversion circuit with respect to a complete zero level input signal has an influence on the output signal in the audible band. Has been.

  In view of this, the above configuration particularly includes balance adjusting means for adjusting the balance between the time for turning on the high-side output element and the time for turning on the low-side output element.

  According to the above configuration, the time for turning on the high-side output element and the time for turning on the low-side output element can be set differently by the balance adjusting means. That is, the high-side output element and the low-side output element can be driven with different potentials. Therefore, a DC offset can be applied to either the high-side output element or the low-side output element.

  As a result, the spectrum generated by the cyclic noise can be pushed out of the audible band. The balance between the time for turning on the high-side output element and the time for turning on the low-side output element can be adjusted inside the analog / digital conversion circuit. There is no need to provide a special circuit in the input stage.

  Therefore, it is possible to provide an analog / digital conversion circuit capable of reducing the influence of cyclic noise on an audible band output signal with a simple circuit design.

  In the analog / digital conversion circuit of the present invention, in the analog / digital conversion circuit having the above configuration, the switching means alternately drives the one side high-side output element and the one side low-side output element. Side switching means, and other side switching means for alternately driving the other side high side output element and the other side low side output element, and for inputting a signal for driving the one side high side output element. The input line to the one side switching means and the input to the other side switching means for inputting a signal for driving the other side low side output element are connected, while the one side low side output element is driven. An input line to the one side switching means for inputting a signal to be transmitted, and the other An input line to the other side switching means for inputting a signal for driving the side high side output element, and the balance adjusting means has a time to turn on the one side high side output element, The balance of the time for turning on the one side low side output element and the balance of the time for turning on the other side high side output element and the time for turning on the other side low side output element are adjusted. There may be.

  According to the above configuration, the time for turning on the one side high side output element and the time for turning on the one side low side output element can be set differently by the balance adjusting means. Similarly, the time for turning on the other side high-side output element and the time for turning on the other side low-side output element can be set differently.

  That is, the one-side high-side output element and the one-side low-side output element can be driven with different potentials. Therefore, a DC offset can be applied to either the one-side high-side output element or the one-side low-side output element. Similarly, a DC offset can be applied to either the other-side low-side output element or the other-side high-side output element.

  As a result, the spectrum generated by the cyclic noise can be pushed out of the audible band. The balance between the time for turning on the high-side output element and the time for turning on the low-side output element can be adjusted inside the analog / digital conversion circuit. There is no need to provide a special circuit in the input stage.

  Further, input lines to the one side high side output element and the other side low side output element are connected, and input lines to the one side low side output element and the other side high side output element are connected. Therefore, the four output elements can be driven by two input signals, and the circuit design can be simplified.

  Therefore, it is possible to provide an analog / digital conversion circuit capable of reducing the influence of cyclic noise on an audible band output signal with a simpler circuit design.

It is a circuit diagram which shows the dead time control circuit in one Embodiment of the analog / digital conversion circuit of this invention. FIG. 2 is a block diagram illustrating an analog / digital conversion circuit including the dead time control circuit of FIG. 1. 3 is a timing chart showing waveforms of input / output signals to the dead time control circuit of FIG. 1.

Explanation of symbols

1 Analog / digital conversion circuit 3 Dead time control circuit (balance adjustment means)
5 First gate driver circuit (switching means, one side switching means)
6 Second gate driver circuit (switching means, other side switching means)
7 Output FET (High side output element, Low side output element, One side / other side high side output element, One side / other side low side output element)
C1 capacitor C2 capacitor D1 diode D2 diode R1 resistor R2 resistor

Claims (4)

In an analog / digital conversion circuit comprising switching means for amplifying and outputting the digital signal by alternately driving a high-side output element and a low-side output element based on the analog / digital converted digital signal ,
An input terminal and an output terminal for driving the high-side output element, an input terminal and an output terminal for driving the low-side output element, and an input terminal for driving the high-side output element and the magnitude of the rise time deviation in output waveform at the output terminal, balance adjustment for setting the size and the different values of the deviation of the rise time of the input and output waveforms at the input and output terminals on the side for driving the low-side output element and a means,
The analog / digital conversion circuit is
The magnitude of the rise time shift in the input / output waveform at the input and output terminals driving the high side output element and the rise time in the input / output waveform at the input terminal and output terminal driving the low side output element. By setting the magnitude of the deviation to a different value,
An analog / digital conversion circuit configured to be in the same state as a state where a DC offset is applied to any of the high-side output element and the low-side output element . The analog / digital conversion circuit is
The magnitude of the rise time shift in the input / output waveform at the input and output terminals driving the high side output element and the rise time in the input / output waveform at the input terminal and output terminal driving the low side output element. By setting the magnitude of the deviation to a different value,
The spectrum generated by cyclic noise generated according to the loop characteristic of the analog / digital conversion circuit with respect to a complete zero level input signal is configured to push the spectrum out of the audible band. 2. The analog / digital conversion circuit according to 1. Between the input terminal on the side driving the high-side output element and the output terminal, and between the input terminal on the side driving the low-side output element and the output terminal,
Resistance,
A capacitor connected in series with the resistor;
While a circuit having a diode feedback-connected to the resistor is connected to each other,
A time constant determined by the resistor and the capacitor connected between the input terminal and the output terminal on the side driving the high-side output element, and an input terminal and an output terminal on the side driving the low-side output element 3. The analog / digital conversion circuit according to claim 1, wherein time constants determined by the resistor and the capacitor connected to each other are different from each other . The rising edge of the digital signal input to the input terminal on the side driving the high-side output element is delayed by the amount of rise time shift in the input / output waveform at the input terminal and output terminal on the side driving the high-side output element. On the other hand, while outputting to the output terminal on the side that drives the high-side output element without delaying the falling of the digital signal,
While delaying the rise of the digital signal input to the input terminal on the side driving the low-side output element by the magnitude of the rise time shift in the input / output waveform at the input terminal and output terminal on the side driving the low-side output element 4. The analog / digital conversion circuit according to claim 1, wherein the analog / digital conversion circuit outputs the signal to an output terminal on a side that drives the low-side output element without delaying a falling edge of the digital signal .

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