JP4327944B2 - Electronic endoscope device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic endoscope apparatus that performs signal processing on an output signal of a solid-state imaging device, reduces power consumption in a non-reading period, and corrects a DC bias that varies due to power consumption.
[0002]
[Prior art]
In recent years, there have been various proposals for an electronic endoscope apparatus using a solid-state imaging device such as a charge imaging device (CCD). The electronic endoscope apparatus includes an endoscope provided with a solid-state image pickup device that picks up an image of a subject in an elongated insertion portion, a drive signal to the solid-state image pickup device, and an image pickup signal from the solid-state image pickup device. And a video processor for processing the video signal, and the video signal from the video processor is displayed on a color monitor.
[0003]
In such an electronic endoscope apparatus, in order to reduce the size of the insertion portion distal end (insertion portion rigid length) of the endoscope, a solid-state imaging device with a built-in buffer circuit is disclosed in Japanese Patent Application Laid-Open No. 10-262919 ( This is proposed in Japanese Patent Application No. 9-71632). In Japanese Patent Laid-Open No. 10-262919, the power consumption of the source follower is reduced by switching the source resistance of the source follower of the output amplifier, which is a heat source built in the solid-state image pickup device, to prevent heat generation of the solid-state image pickup device. It is.
[0004]
Further, in Japanese Patent Application No. 10-184819 filed earlier by the applicant of the present application, there is provided means for reducing the DC level difference caused by switching the source resistance of the source follower of the output amplifier built in the solid-state image sensor. An electronic endoscope apparatus having the same has been proposed.
[0005]
A conventional electronic endoscope apparatus similar to the electronic endoscope apparatus proposed in Japanese Patent Application Laid-Open No. 10-262919 and Japanese Patent Application No. 10-184819 will be described with reference to FIGS.
[0006]
An electronic endoscope apparatus 1 ′ shown in FIG. 6 includes an electronic endoscope 2 having a solid-state imaging device (CCD) 10, a light source apparatus 3 that supplies illumination light for irradiating a subject, and a drive signal to the CCD 10. A video processor 4 ′ that captures and processes an imaging signal via a transmission cable 18 and a color monitor 5 ′ that displays a video signal generated by the video processor 4 ′.
[0007]
The electronic endoscope 2 has a thin insertion portion 6, and a thick operation portion 8 is formed at the rear end of the insertion portion 6. A light guide 7 that transmits illumination light is inserted into the insertion portion 6, and a rear end of the light guide 7 is detachably connected to the light source device 3, and illumination light from the lamp 13 passes through the condenser lens 12. To the rear end surface of the light guide 7. This illumination light is transmitted through the light guide 7 and further irradiated from the distal end surface attached to the distal end portion 31 to a subject such as an affected part in the body cavity via the illumination lens 14.
[0008]
An objective lens 9 is provided at the distal end portion 31 of the insertion portion 6 and connects the subject image to its focal plane. The CCD 10 is disposed on this focal plane. The subject is optically color-separated by a color filter on the entire surface of the CCD chip of the CCD 10.
[0009]
It is photoelectrically converted by the CCD 10 and accumulated as charges corresponding to the subject image optically color-separated. In the CCD 10, accumulated charges are read out by applying a CCD drive signal from a CCD driver 16 provided in the video processor 4 ′ via a cable 17.
[0010]
The read signal (also referred to as an imaging signal) is amplified by an output amplifier 33 (see FIG. 7A) that is an impedance reduction unit provided in the CCD 10, and then inserted into the insertion unit 6 and the operation unit 8. The video signal is input to the video processor 4 ′ connected to the end of the transmission cable 18 through the transmission cable 18 wired inside.
[0011]
The terminal of the transmission cable 18 of the video processor 4 ′ is connected to a resistor R1 and a switch S in order to reduce the power consumption of the output amplifier 33 built in the CCD 10 disposed at the distal end portion 31 of the electronic endoscope 2. It is connected to a termination circuit grounded through a series connection and a resistor R2 having a large constant. The switch S is turned on only during the readout period of the imaging signal output from the CCD 10.
[0012]
The output of this termination circuit is supplied to the analog switch 52 and the sample hold circuit 51. The analog switch 52 selects the output from the termination circuit during the read period and selects the output from the sample hold circuit 51 during the non-read period. To the preamplifier 20.
[0013]
The preamplifier 20 is provided to compensate for a level drop in the transmission cable 18 and is amplified to a predetermined signal level. The imaging signal amplified by the preamplifier 20 is input to a CDS circuit (correlated double sampling circuit) 23. The CDS circuit 23 removes reset noise of the CCD 10 included in the image pickup signal, and then supplies it to the A / D converter 24. The A / D converter 24 converts the imaging signal into digital data, generates a digital video signal in the digital video processing unit 25, converts it into an analog video signal in the D / A converter 26, and supplies it to the color monitor 5 ′. Is projected.
[0014]
The CCD driver 16, switch S, sample hold circuit 51, analog switch 52, CDS circuit 23, A / D converter 24, digital video processing unit 25, and D / A converter 26 are controlled signals from the control circuit 21. Thus, each operation and signal processing are controlled.
[0015]
A CCD power supply Vcc generated from an internal power supply circuit (not shown) of the video processor 4 ′ is supplied via a cable 22 to the CCD 10 provided in the insertion portion 6 of the electronic endoscope 2.
[0016]
The CCD 10 employed in the electronic endoscope 2 will be described in detail with reference to FIG. The CCD 10 shown in FIG. 7 employs an interline transfer method, and the light receiving unit 40 is configured by photodiodes arranged in a matrix. Reference numeral 41 denotes a read gate, and the read gate 41 is provided with a vertical transfer CCD 42. The vertical transfer CCD 42 is provided on the horizontal transfer CCD 43. An output gate 44 is formed at one end of the horizontal transfer CCD 43. A read gate terminal LG is connected to the read gate 41.
[0017]
The vertical transfer CCD 42 is four-phase driven, and φV1 to φV4 are generated by the CCD driver 16 of the processor 4 ′ and supplied via the cable 17. The horizontal transfer CCD 43 is a two-phase drive. Similarly, φH1 to φH2 are generated by the CCD driver 16 and supplied via the cable 17. Further, φR is generated by the CCD driver 16 and supplied to the output gate 44 via the cable 17.
[0018]
The output gate 44 is connected to the input terminal of the output amplifier 33, and a power supply voltage is applied via the output gate terminal OG. In recent CCDs 10, there are a power supply voltage applied to the gate terminal OG generated internally, and a power supply voltage applied externally through a bleeder.
[0019]
The output amplifier 33 is configured using a field effect transistor, and includes an amplifying transistor Q1, a transistor Q2 serving as a current source connected between the source electrode of the transistor Q1 and the ground line, and a reset transistor Q3. And an amplifying transistor Q4, a transistor Q5 serving as a current source connected between the source electrode of the transistor Q4 and the earth line, and a low impedance conversion transistor Q6 serving as an output stage.
[0020]
The output gate 44 is connected to the gate electrode of the transistor Q1 and the source electrode of the reset transistor Q3. The drain electrodes of the transistors Q1 and Q4 are connected to the power supply terminal Vcc, and the drain electrode of the reset transistor Q3 is also connected to the power supply terminal Vcc via the terminal RD. A power supply voltage of about 15 V is applied to the power supply terminal Vcc.
[0021]
A reset pulse φR is applied to the gate electrode of the reset transistor Q3. The transistor Q2 has a gate electrode and a source electrode connected in common and connected to the ground line, and a drain electrode connected to the source electrode of the transistor Q1. The source electrode of the transistor Q1 is connected to the gate electrode of the transistor Q4.
[0022]
The source electrode of the transistor Q4 is connected to the drain electrode of the transistor Q5. The source electrode and gate electrode of the transistor Q5 are connected in common and connected to the earth line. The source electrode of the transistor Q4 is connected to the gate electrode of the transistor Q6, and the drain electrode of the transistor Q6 is connected to the power supply terminal VDD. The power supply terminal VDD is connected to the power supply terminal Vcc.
[0023]
The source electrode of the transistor Q6 is connected to the output terminal Vout. The ground line is connected to the ground line of the video processor 4 'via the terminal GND.
[0024]
The transistors Q1 and Q2 constitute a first-stage source follower, the transistors Q4 and Q5 constitute a second-stage source follower, and the transistor Q6 constitutes an output source follower.
[0025]
Charges generated by the photodiodes in each column arranged on the light receiving unit 40 in a matrix are transferred to the vertical transfer CCD 42 via the read gate 41. A power supply voltage is applied to the read gate 41 via the read gate terminal LG, and charges generated in the photodiode are read for each field or frame period. The gate terminal LG may be generated by bleedering VDD with a resistor as in the case of the OG terminal, or may be generated inside the CCD.
[0026]
The charges generated in the photodiode of the light receiving unit 40 are read and transferred to the vertical transfer CCD 42 at a predetermined timing by transfer pulses φV1 to φV4 input to the vertical transfer CCD42. The charges transferred to the vertical transfer CCD 42 are supplied to the horizontal CCD 43 for each horizontal scanning line. The horizontal transfer CCD 43 sends out the charges transferred from the vertical transfer CCD 42 pixel by pixel. Charge delivery from the horizontal transfer CCD 43 is transferred to the output gate 44 by transfer pulses of φH1 to φH2. The charge transferred to the output gate 44 is supplied to the gate electrode of the transistor Q1. The source electrode of the reset transistor Q3 is connected to the gate electrode of the transistor Q1, and the gate electrode of the transistor Q1 is reset at the timing of the reset pulse φR supplied to the gate electrode of the reset transistor Q3. In other words, the reset transistor Q3 is turned on / off by the reset pulse φR, and the charge supplied from the output gate 44 to the gate electrode of the transistor Q1 is reset in synchronization with the reset pulse φR of the reset transistor Q3. During reset, the charge of one pixel is transferred from the output gate 44 and supplied to the gate of the transistor Q1.
[0027]
An imaging signal controlled by the reset operation of the reset transistor Q3 from the output gate 44 and supplied to the gate electrode of the transistor Q1 is current-amplified by a first-stage source follower including the transistors Q1 and Q2, and the transistor The current is further amplified by a second-stage source follower composed of Q4 and transistor Q5, and supplied to the gate electrode of transistor Q6.
[0028]
This transistor Q6 is an output source follower, converts the output from the transistor Q4 of the second-stage source follower into a low impedance, and terminates the video processor 4 ′ from the Vout terminal via the transmission cable 18. To be supplied.
[0029]
The termination circuit section of the video processor 4 ′ includes a power reduction means comprising a series circuit of a resistor R 1 and a switch S and a resistor R 2. The resistors R1 and R2 of the power consumption reducing means are set to R1 << R2.
[0030]
The operation of the power consumption reducing means will be described with reference to FIG. During the readout period of the video signal supplied via the transmission cable 18, the switch S is turned on based on the control signal from the control circuit 21, and the source resistance of the transistor Q6 of the output amplifier 33 is reduced. (R1 // R2) In the non-reading period, the switch S is turned off so that the source resistance of the transistor Q6 becomes very large (R2). Thus, the drain current of the transistor Q6 can be controlled and power consumption can be reduced.
[0031]
However, when the drain current of the transistor Q6 is controlled, the DC bias varies. The mutual admittance gm of the field effect transistor (MOSFET) is expressed by ΔID / ΔVGS, and the change in VGS is proportional to the drain current. Therefore, as the drain current increases during the read period, VGS increases, and as a result, DC Bias decreases. On the other hand, the drain current decreases during the non-read period, and as a result, the DC bias increases. That is, as shown in FIG. 7B, the video signal of the termination circuit of the video processor 4 'undergoes a DC bias fluctuation with a width of Vdc during the reading period and the non-reading period.
[0032]
Since this Vdc has a relatively large amplitude with respect to the original output signal of the CCD 10, it is necessary to take a wide dynamic range in consideration of Vdc in the next stage circuit.
[0033]
In order to remove this Vdc, the sample hold circuit 51 holds the potential of the optical black period (OB period), and the switch 52 holds the non-read period in which the Vdc bias varies from the OB period in the sample hold circuit 51. The dynamic range of the next stage is narrowed by replacing with the OB potential.
[0034]
The suppression of the Vdc bias fluctuation will be described with reference to FIG. FIG. 8 is a diagram showing a circuit of a signal input stage of the video processor 4 ′. The switch S is formed by a switching circuit including a transistor 53, a capacitor C1, and resistors R3 and R4. It is turned on / off by a control signal from the control circuit 21. The capacitor C2 and the resistor R5 in the next stage are for terminating the transmission cable 18 in an AC manner, and the constant of the resistor R5 is selected to be equal to the characteristic impedance of the transmission cable 18.
[0035]
The signal at the point a in FIG. 5 that is AC terminated is supplied to the fixed contact a of the switch 52 and the sample hold circuit 51. The sample hold circuit 51 holds the potential of the OB period in accordance with the sample hold pulse from the control circuit 21. The switch 52 selects the signal after the AC termination in the reading period and the output of the sample hold circuit 51 in the non-reading period according to the control signal. As a result, the signal at the point b in the figure on the output side of the switch 52 becomes a signal in which the bias fluctuation of Vdc is reduced.
[0036]
[Problems to be solved by the invention]
However, the amplitude of the output signal of the CCD 10 changes between when a bright subject is imaged and when a dark subject is imaged in the bias fluctuation correction between the readout period and the non-readout period by the conventional power consumption reduction means of the CCD 10 described above. For this reason, the APL (average video level) of the imaging signal after AC termination varies. Due to this APL variation, the dynamic range of the sample-and-hold circuit and the preamplifier needs to be wide corresponding to the APL variation.
[0037]
Furthermore, a sag is generated because the DC component is removed by the capacitor C2 when the AC termination is performed. Usually, this sag is removed by the CDS circuit 23. However, since the DC bias of the signal after the AC termination is fluctuating, the zag component becomes very large and shading may occur.
[0038]
The present invention has been made in view of the above circumstances, and can cope with APL fluctuations due to fluctuations in the amplitude of a video signal due to the brightness of a subject imaged by a CCD without expanding the dynamic range. An object of the present invention is to provide an electronic endoscope apparatus that can be reliably removed.
[0039]
[Means for Solving the Problems]
  The electronic endoscope apparatus of the present invention isA first resistor having a predetermined resistance value; a switch connected in series with the first resistor; the first resistor connected in series; and the first resistor provided in parallel with the switch. A second resistor having a resistance value greater than the resistance value ofFrom the solid-state imaging unitDoes not read the image signalDuring non-read periodBy turning off the switchThe power consumption reducing means for reducing the power consumption of the output unit of the solid-state imaging unit; andFrom means to reduce power consumptionofImagingSignalOnly for a predetermined clamping periodClampAnd charge the capacitor with the potential of the imaging signal obtained by clampingDochargeMeans,An operational amplifier for inputting the potential charged to the capacitor by the charging unit and the clamp potential during the predetermined clamping period so that the potential charged to the capacitor and the clamp potential are equal; and the imaging In the readout period for reading out the signal, the clamp potential output from the operational amplification means is selected, and in the non-readout period, the selection means for selecting the imaging signal obtained by the clamping;Said power consumption reducing meansThe selection meansas well aschargeAnd control means for generating timing pulses necessary for the means.
[0040]
  The electronic endoscope apparatus of the present inventionchargeThe means is characterized by clamping outside the non-read period by the timing pulse.
[0041]
  Also, the electronic endoscope apparatus of the present inventionThe charging means further includes a second capacitor for charging the output potential of the operational amplifier means, and clamps the imaging signal for a predetermined clamping period based on the potential charged in the second capacitor. DoIt is characterized by that.
The necessary timing pulse of the electronic endoscope apparatus according to the present invention includes a timing pulse of a signal designating the clamp period to the charging unit, and a reading period or a period of the power consumption reducing unit and the selecting unit. It includes a timing pulse of a signal designating the non-reading period.
[0042]
As a result, even if the APL fluctuation of the image pickup signal due to the brightness of the subject occurs, the video signal of a certain level is used, so that the dynamic range of the CDS circuit or the like does not need to be expanded and the sag is reliably removed. An electronic endoscope apparatus can be provided.
[0043]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 to 4 relate to an embodiment of the present invention, FIG. 1 is a block diagram showing the overall configuration of the electronic endoscope apparatus of the embodiment, and FIG. 2 is a diagram of a video processor of the electronic endoscope apparatus. FIG. 3 is a waveform diagram for explaining the operation, and FIG. 4 is a circuit connection diagram showing the configuration of the preamplifier.
[0044]
The electronic endoscope apparatus 1 according to the embodiment of the present invention shown in FIG. 1 has the same parts as those of the conventional electronic endoscope apparatus 1 ′ shown in FIG. Is provided with a clamp circuit 50 instead of the sample-and-hold circuit 51 and the analog switch 52 on the input side of the preamplifier 20 of the video processor 4 ′, and a clamp pulse is applied from the control circuit 21 to the clamp circuit 50. The video processor 4 is provided with a means for eliminating the DC level difference by switching the input signal to the negative input terminal (inverted input terminal) of the preamplifier 20 with a control signal for turning on / off the switch S.
[0045]
As shown in FIG. 1, an electronic endoscope apparatus 1 according to an embodiment of the present invention includes an electronic endoscope 2 having a CCD 10 as a solid-state imaging device, and a photogenerator 3 that supplies illumination light to irradiate a subject. A cable 17 that supplies a drive signal to the CCD 10, a video processor 4 that takes in an image signal from the CCD 10 via a transmission cable 18, and processes the image signal, and a video signal output from the video processor 4 And a color monitor 5 for displaying.
[0046]
The electronic endoscope 2 has a thin insertion portion 6, and a thick operation portion 8 is formed at the rear end of the insertion portion 6. A light guide 7 for transmitting illumination light is inserted into the insertion portion 6. The rear end of the light guide 7 is detachably connected to the light source device 3, and illumination light from the lamp 13 passes through the condenser lens 12. To the rear end surface of the light guide 7. This illumination light is transmitted through the light guide 7 and irradiated to a subject such as an affected part in the body cavity through an illumination lens 14 attached to the distal end portion 31.
[0047]
The objective lens 9 is provided at the distal end portion 31 of the insertion portion 6, and the CCD 10 is disposed on the focal plane connecting the subject images. The subject is optically color-separated by a color filter in front of the CCD chip of the CCD 10.
[0048]
Charges corresponding to the subject image optically color-separated by photoelectric conversion by the CCD 10 are accumulated. In the CCD 10, accumulated charges are read out when a CCD drive signal from a CCD driver 16 provided in the video processor 4 is applied via a cable 17.
[0049]
The read accumulated charge (hereinafter referred to as an imaging signal) is amplified by an output amplifier 33 (see FIG. 7 a) that is an impedance reduction means provided inside the CCD 10, and then is inserted into the insertion unit 6 and the operation unit 8. The signal is supplied to the preamplifier 20 through the clamp circuit 50 in the video processor 4 connected to the termination circuit portion of the transmission cable 18 via the transmission cable 18 wired to the cable.
[0050]
The output of the preamplifier 20 is converted into a digital signal by an A / D converter 24 after reset noise is removed by a correlated double sampling (hereinafter referred to as a CDS circuit) 23. The digital signal converted by the A / D converter 24 is converted into a video signal by the digital video processing 25, and unnecessary areas (other than the mask 5A of the color monitor 5) are masked. The masked video signal is converted into an analog signal by the D / A converter 26 and output from the output connector of the video processor to the color monitor-5. The operation of the endoscope 2 is performed.
[0051]
Next, the current consumption reducing means comprising the resistor R1, the switch S, and the resistor R2 of the termination circuit unit to which the CCD 10 arranged in the video processor 4 is connected by the transmission cable 18, the configuration of the clamp circuit 50 and the preamplifier 20 are shown. The operation will be described.
[0052]
As shown in FIG. 2, the current consumption reducing means comprising the resistor R1, the switch S and the resistor R2 comprises resistors R1 and R2, resistors R3 and R4 constituting the switch S, a capacitor C1, and a transistor 53. Yes. Here, the resistors R1 and R2 are set to R1 << R2. The control signal input to the capacitor C1 and the resistor R4 is supplied with a control signal that is at an H level during a period in which a necessary signal exists (readout period) and an L level during a period in which an unnecessary signal exists (non-readout period). (See FIG. 3A).
[0053]
When this control signal is at the H level, the transistor 53 is turned on, and the source resistance of the output amplifier 33 (see FIG. 7a) built in the CCD 10 is determined by (DC resistance of the transmission cable 18) + R1 // R2. The
[0054]
On the other hand, when the control signal is at the L level, the transistor 53 is turned off, and the source resistance of the output amplifier 33 becomes (the DC resistance of the transmission cable 18) + R2.
[0055]
Generally, the direct current resistance of the transmission cable 18 is several Ω, and can be ignored here. Therefore, since the relationship between the resistors R1 and R2 is R1 << R2, it can be approximated to the resistor R1 when the transistor 53 is on and to the resistor R2 when the transistor 53 is off. That is, during the H level read period, the source resistance of the output amplifier 33 decreases and the drain current increases. As a result, the gate-source voltage increases and the bias value Vdc decreases. On the other hand, during the L level non-reading period, the source resistance increases, the drain current decreases, and as a result, the gate-source voltage decreases, and the bias value Vdc increases (see FIG. 3B).
[0056]
The video signal, which is the output of the output amplifier 33 processed by the current consumption reducing means, is DC removed by the capacitor C2, and the transmission cable 18 is AC-terminated by the resistor R5 and supplied to the clamp circuit 50. The
[0057]
The clamp circuit 50 is connected to a normal input terminal (hereinafter referred to as a + input terminal) of the preamplifier 20 via a series circuit of a first buffer AM1, a capacitor C3, and a second buffer AM2, and the capacitor C3 The connection point of the second buffer AM2 is grounded via a series circuit of the first switch SW1 and the capacitor C4, and the connection point of the second buffer AM2 and the + input terminal of the preamplifier 20 is the second connection point. The switch SW2 and the capacitor C5 are grounded via a series circuit, and one fixed contact of the third switch SW3 is connected. The connection point of the first switch SW1 and the capacitor C4 is the third switch The connection point of the second switch SW2 and the capacitor C5 is connected to the other fixed contact of SW3 via a low-pass filter LPF. The operational amplifier OP1 is connected to the inverting input terminal (hereinafter referred to as “−input terminal”), the normal rotation input terminal (hereinafter referred to as “+ input terminal”) of the operational amplifier OP1 is connected to the reference power supply VREF, and the output terminal is Connected to the other fixed contact of the third switch SW3, the movable contact of the third switch SW3 is connected to an inverting input terminal (hereinafter referred to as -input terminal) of the preamplifier 20, and The movable contacts of the second switches SW1 and SW2 are supplied with a clamp signal for on / off operation, and the movable contact of the third switch SW3 is one of the fixed contacts based on the control signal from the control circuit 21. It is the structure which performs connection switching to.
[0058]
The operation of the clamp circuit 50 is such that the DC signal is removed by the capacitor C2 and the resistor R5, which are the termination circuit of the transmission cable 18, and the video signal shown in FIG. The This video signal is buffered by the first buffer AM1, and then the direct current component is removed by the capacitor C3. The first switch SW1 is turned on for the H level period of the clamp signal shown in FIG. Clamped to potential. The video signal clamped by the capacitor C4 is buffered again by the second buffer AM2 and supplied to the preamplifier 20, and is also supplied to the capacitor C5 via the second switch SW2 during the H level period of the clamp signal. Is charged as an average level potential. The video signal charged to the capacitor C5 as an average level potential is supplied to the operational amplifier OP1 through the low pass filter LPF. The operational amplifier OP1 compares the clamp potential VREF with the average level potential of the capacitor C5 and feeds back an error to the capacitor C4. Thus, direct current reproduction is performed so that the average level potential charged in the capacitor C5 becomes equal to the clamp potential VREF, and a video signal shown in FIG. 3D is generated at a point b in the figure.
[0059]
That is, the output of the third switch SW3 is such that the clamp potential VREF is at the H level of the control signal from the control circuit 21 and the transistor 53 is at the L level of the control signal during the read period when the transistor 53 is turned on. A video signal clamped at the clamp potential VREF is output during the non-reading period in which it is turned off. As an output signal of the third switch SW3, a signal shown in FIG. 3E is supplied to the negative input terminal of the preamplifier 20 at a point c in the figure.
[0060]
In other words, if there is a difference in the average video level of the imaging signal generated by the CCD 10 due to the brightness of the subject, the third switch SW3 is set as a video signal whose average video level is clamped at VREF by the clamp circuit 50. Thus, the preamplifier 20 can be supplied.
[0061]
The preamplifier 20 is composed of a differential amplifier as shown in FIG. In this preamplifier 20, a pair of transistors Q100 and Q101 are connected in a differential manner, and the emitter electrodes of both transistors Q100 and Q101 are connected by a resistor R100 and are connected to a negative power source -Vss via resistors R102 and R103. The collector electrode of the transistor Q100 is connected to the power source + Vcc, and the collector electrode of the transistor Q101 is connected to the power source + Vcc via the resistor R101. The base electrode of the transistor Q100 is a + input terminal (normal input terminal), and the base electrode of Q101 is a-input terminal (inverted input terminal).
[0062]
The third switch SW3 is connected to the negative input terminal. The third switch SW3 is a two-input / one-output switch. One of the two inputs has a clamped signal input to the + input terminal of the preamplifier 20, and the other input has a clamp potential. VREF is supplied. An output signal is supplied to the CDS circuit 23 from the collector electrode of the transistor Q101. Note that the same signal as the control signal from the control circuit 21 used in the power consumption reduction circuit is used as the switch switching signal of the third switch SW3.
[0063]
As a result, during the non-reading period in which the DC bias varies, the third switch SW3 is selected such that the output from the buffer amplifier AM2 is supplied. At this time, the first and second switches SW1 and SW2 are turned on by a clamp signal, and a video signal in which the non-reading period is held at VREF is supplied to the + input terminal and the transistor Q101− input terminal of the transistor Q100. Thus, the same signal clamped to the same VREF level is canceled by the transistors Q100 and Q101 and is not output from the collector electrode.
[0064]
On the other hand, during the readout period in which the DC bias does not vary, the third switch SW3 selects the clamp potential VREF and supplies it to the -input terminal of the transistor Q101, and is input to the + input terminal of the transistor Q100. A video signal in the readout period is supplied from the second buffer amplifier AM2, amplified by the ratio of the emitter resistance R100 and the collector resistance R101 of the transistor Q101, and the signal shown in FIG. To the next stage CDS circuit 23.
[0065]
As a result, the image clamped to VREF by the clamp circuit 50 even if the average image level generated by the contrast of the subject supplied to the + input terminal of the transistor Q100 fluctuates among the image signals imaged and generated by the CCD 10. Since the signal is amplified and supplied to the CDS circuit 23 by the ratio of the emitter resistor R100 and the resistor R101, it is not necessary to widen the input dynamic range of the CDS circuit 23. Can also be reduced.
[0066]
Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 5, the same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0067]
In the conventional electronic endoscope apparatus, since the video signal imaged and generated by the CCD 10 is terminated by the terminating resistor R5 after the DC component is removed by the capacitor C2, sag is likely to occur in the video signal.
[0068]
For this reason, in this other embodiment, the switch S is configured based on the control signal from the control circuit 21 in which the imaging signal generated by the CCD 10 is transmitted by the transmission cable 18 and the current consumption reducing means. The transistor 53 is turned on / off to reduce the power consumption, the DC component is removed by the capacitor C2, and the signal in which the AC termination of the transmission cable 18 is made by the resistor R5 is buffered by the source follower of the transistor Q54. And input to the + input terminal of the preamplifier. On the other hand, the average potential of the output signal from the transistor Q54 is charged to the capacitor C5 during the readout period when the clamp signal is at the H level by the first switch SW1. The video signal with the average potential charged in the capacitor C5 is supplied to the active filter in the next stage.
[0069]
This active filter has an operational amplifier OP1, a resistor 10 arranged between the + input terminal and the output terminal of the operational amplifier OP1, and a series connection of a resistor R11 and a capacitor C10 arranged in parallel, and the output terminal of the operational amplifier OP1 is The VREF potential is arranged at the negative input terminal of the operational amplifier OP1 and is connected to the connection point of the resistor R5 and the capacitor C4. The VREF potential is input to the other fixed contact of the third switch SW3. It is the composition which becomes.
[0070]
The average potential charged in the capacitor C5 during the period when the first switch SW1 is turned on by the clamp signal is compared with VREF by the operational amplifier OP1 and band-limited by an active filter comprising resistors R10, R11 and a capacitor C10. Is done. When an error occurs as a result of the comparison by the operational amplifier OP1, the video signal is fed back to the capacitor C4 so that the error signal component of VREF and the capacitor C5 is held in the capacitor C4. AC terminated with electric potential.
[0071]
The buffer output of the transistor Q54 input to the preamplifier 20 is input to one fixed contact of the third switch SW3, and the movable contact is switched and controlled based on the control signal from the control circuit 21, so that the video signal The buffer output of the transistor Q54 is selected during the non-reading period when the DC level varies, and VREF is selected during the reading period when the DC level does not vary. The output of the third switch SW3 is supplied to the negative input terminal of the preamplifier 20.
[0072]
As a result, during the non-reading period in which the DC level fluctuates, the output of the preamble 20 is such that the in-phase video signal in which the first switch SW1 is turned on and the clamp potential of the capacitor C4 is held at VREF is input to the + input terminal and the −input. Since it is supplied to the terminal, the sag is removed by the in-phase signal supplied to the + and-input terminals, and the video signal is amplified by the output video signal and VREF of the CCD 10 during the readout period when there is no DC level fluctuation. Is output.
[0073]
Therefore, the average video level fluctuation due to the luminance change of the video signal due to the brightness of the subject does not occur, it is not necessary to expand the dynamic range of the CDS circuit 23 arranged on the output side of the preamplifier 20, and the circuit scale can be reduced. . Also, sag due to AC termination can be reduced.
[0074]
[Appendix]
As described above in detail, according to the embodiment of the present invention, the following configuration can be obtained.
(1) a solid-state imaging unit;
Input means for inputting an output signal of the solid-state imaging unit;
Provided in a path from the solid-state imaging unit to the input unit, and in a non-reading period of the solid-state imaging unit, a power consumption reduction unit for reducing the power consumption of the output unit of the solid-state imaging unit;
Clamping means for clamping the output signal of the input means;
Control means for generating timing pulses necessary for the power consumption reduction means and the clamping means;
An electronic endoscope apparatus comprising:
[0075]
(2) The electronic endoscope apparatus according to appendix 1, wherein the clamping means clamps outside the non-reading period by the timing pulse.
[0076]
(3) a solid-state imaging unit;
Input means for inputting an output signal of the solid-state imaging unit;
Provided in a path from the solid-state imaging unit to the input unit, and a power consumption reduction unit for reducing the power consumption of the solid-state imaging unit during a non-reading period of the solid-state imaging unit;
Clamping means for clamping the output signal of the input means;
Unnecessary signal suppression means for suppressing the output signal of the clamping means during the non-reading period;
Control means for generating timing pulses necessary for the power consumption reducing means, clamping means and unnecessary signal suppressing means;
An electronic endoscope apparatus comprising:
[0077]
(4) The electronic endoscope apparatus according to appendix 3, wherein the clamping means clamps outside the non-reading period by the timing pulse.
[0078]
(5) The electronic endoscope apparatus according to appendix 1, 2, or 3, wherein the power consumption reduction means is provided immediately before the input means.
[0079]
(6) The electronic endoscope apparatus according to any one of appendices 1 to 5, wherein the power consumption reduction unit cuts off a high impedance or a signal during a non-reading period during a reading period with a predetermined impedance.
[0080]
(7) An endoscope provided with a solid-state imaging device for imaging a subject in an elongated insertion portion, a drive signal to the solid-state imaging device, and signal processing for an output signal output from the solid-state imaging device In an electronic endoscope connected with a video processor via a cable,
Impedance reduction means for amplifying the output signal from the solid-state imaging device and converting the output signal to a low impedance and supplying it to the video processor via the cable;
Electric power for reducing the power consumption of the impedance reducing means in a non-reading period in which the output signal is not read with respect to a signal reading period in which the output signal from the solid-state imaging device supplied via the cable is read Means for reducing consumption;
Clamping means for clamping the output signal within the readout period;
Switch means to which an output signal of the clamp means is input;
A differential amplification means having a normal rotation input terminal to which an output signal of the clamp means is supplied; and an inverting input means to which an output signal of the switch means is supplied;
The switch means selects a clamp potential of the clamp means in synchronization with a readout period of the power consumption reduction means, and selects an output signal of the clamp means in synchronization with a non-read period. An electronic endoscope apparatus that is characterized.
[0081]
【The invention's effect】
Since the fluctuation of the DC bias due to the current consumption reducing means can be corrected and the sag generated by the AC terminal of the transmission cable can be reduced, a good image can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of an electronic endoscope apparatus according to an embodiment of the present invention.
FIG. 2 is a circuit connection diagram showing a circuit configuration of a video processor of the electronic endoscope apparatus according to the present invention.
FIG. 3 is a waveform diagram for explaining the operation of the electronic endoscope apparatus according to the present invention.
FIG. 4 is a circuit connection diagram showing a circuit configuration of a preamplifier used in a video processor of an electronic endoscope apparatus according to the present invention.
FIG. 5 is a circuit connection diagram showing a circuit configuration of a video processor of an electronic endoscope apparatus according to another embodiment of the present invention.
FIG. 6 is a block diagram showing an overall configuration of a conventional electronic endoscope apparatus.
7A and 7B show a CCD used in a conventional electronic endoscope apparatus, FIG. 7A is a circuit connection diagram, and FIG. 7B is a waveform diagram for explaining operations;
FIG. 8 is a circuit connection diagram showing a circuit configuration of power consumption reducing means used in a conventional electronic endoscope apparatus.
[Explanation of symbols]
1. Electronic endoscope device
2 ... Electronic endoscope
3. Light source device
4 ... Video processor
5 ... Monitor
6 ... Insertion section
10 ... CCD
16 ... CCD driver
17 ... Cable
18 ... Transmission cable
20 ... Preamplifier
21 ... Control circuit
23 ... CDS circuit
24 ... A / D converter
25. Digital image processing unit
26 ... D / A converter
50 ... Clamp circuit
R1, R2 ... resistance
S ... Analog switch

Claims (4)

A first resistor having a predetermined resistance value; a switch connected in series with the first resistor; the first resistor connected in series; and the first resistor provided in parallel with the switch. A second resistor having a resistance value greater than a resistance value of the solid-state imaging unit, and turning off the switch during a non-reading period in which the imaging signal from the solid-state imaging unit is not read , thereby consuming the output unit of the solid-state imaging unit Means for reducing power consumption to reduce power;
Clamping the imaging signal from the power consumption reduction unit for a predetermined clamping period , and charging means for charging the capacitor with the potential of the imaging signal obtained by clamping ,
An operational amplification means for inputting the potential charged to the capacitor by the charging means and the clamp potential during the predetermined clamping period so that the potential charged to the capacitor and the clamp potential become equal;
In the readout period for reading out the imaging signal, the clamp potential output from the operational amplification means is selected, and in the non-readout period, the selection means for selecting the imaging signal obtained by the clamping;
Control means for generating timing pulses necessary for the power consumption reduction means , the selection means and the charging means;
An electronic endoscope apparatus comprising: The electronic endoscope apparatus according to claim 1, wherein the charging unit is clamped outside the non-reading period by the timing pulse. The charging unit further includes a second capacitor for charging the output potential of the operational amplification unit, and clamps the imaging signal for a predetermined clamping period based on the potential charged in the second capacitor. The electronic endoscope apparatus according to claim 1 .   The necessary timing pulse includes a timing pulse of a signal designating the clamping period for the charging unit, and a timing pulse of a signal designating the reading period or the non-reading period for the power consumption reduction unit and the selection unit. The electronic endoscope apparatus according to claim 1, comprising:

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