JP4323849B2 - Solid-state imaging device and camera - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device including an imaging unit including a plurality of pixels and a plurality of scanning circuits configured by a dynamic logic circuit and outputting a signal for selecting a row or a column of the imaging unit.
[0002]
[Prior art]
In recent years, attention has been paid to a solid-state imaging device using an amplification type MOS sensor as one of the solid-state imaging devices. This solid-state imaging device amplifies a signal detected by a photodiode for each cell representing a pixel by a transistor, and has a feature of high sensitivity.
[0003]
In such a solid-state imaging device, a dynamic shift register is used as a circuit that horizontally or vertically scans an imaging unit having pixels arranged in two dimensions, thereby simplifying the circuit, increasing the density, and reducing power consumption. I am trying.
[0004]
A conventional solid-state imaging device such as Patent Literature 1 includes an imaging unit 10 and a plurality of scanning circuits 1 and 2 as shown in FIG. The scanning circuits 1 and 2 are shift registers that output output signals for reading pixel signals to the imaging unit 10 at independent timings. These outputs are configured to be electrically connected.
[0005]
The electronic shutter function of the solid-state image pickup device is to adjust the charge accumulation time of the image pickup unit 10 by driving and to control the exposure time electronically instead of the physical aperture function. Specifically, the electronic shutter function is realized by discharging (resetting) signal charges accumulated in each pixel at a predetermined timing different from pixel signal readout. For example, the scanning circuit 1 outputs a row selection signal for reading a normal pixel signal, and the scanning circuit 2 outputs a row selection signal for resetting with an electronic shutter function.
[0006]
Also, in the case of performing up-down or left-right reversal readout of an image, similarly to the above, a plurality of scanning circuits having different scanning directions are arranged, and their outputs are electrically connected and connected to the imaging unit 10 up and down or The structure is such that an access signal for right and left scanning is output. The scanning circuit 1 outputs a row selection signal for reading a normal pixel signal, and the scanning circuit 2 outputs a row selection signal for inverted reading for scanning in the reverse direction.
[0007]
The outputs of the plurality of scanning circuits 1 and 2 are connected to each other because, when the scanning circuits 1 and 2 are constituted by shift registers using NMOS dynamic logic circuits, an output line that outputs a high level as a selection signal. Other than the above is due to the reason that the output line is in a floating state. The logical sum of these outputs is taken by the connection.
[0008]
[Patent Document 1]
Japanese Patent Laid-Open No. 2003-46879
[0009]
[Problems to be solved by the invention]
However, the solid-state imaging device having a plurality of shift registers composed of the NMOS dynamic logic circuit has the following problems.
[0010]
A problem to be solved by the present invention will be described with reference to FIGS.
FIG. 11A is a circuit showing the detailed configuration of the structural unit of the scanning circuit 1 (referred to as the unit register 11) and the structural unit of the scanning circuit 2 (referred to as the unit register 12) shown in the broken line frame of FIG. FIG. V1 and V2 in FIG. 10 are two-phase clock signals supplied to the scanning circuit 1. The odd-numbered unit registers are operated by the clock signal V1, and the even-numbered unit registers are operated by the clock signal V2. Since the unit register 11 in FIG. 11A is the first stage unit register, the clock signal V1 is supplied. The input signal In is a signal from the previous stage, and the output signal Next is a signal to the subsequent stage. However, the input signal In to the unit register 11 in the first stage is a start pulse. The output signal Out is a row selection signal output to the imaging unit 10.
[0011]
The same applies to the input signal EIn, the output signal EExt, and the output signal EOut in the unit register 22. The output signals EOut and Out are common output wiring.
[0012]
FIG. 11B is a time chart showing the operation timing of FIG. When a pulse of the clock signal V1 for normal reading is applied to the boot transistor Tr1 (timing (1) in the figure), the gate voltage of the transistor Tr1 is boosted through the boot capacitor Cap1 (hereinafter referred to as boot). Thus, the voltage becomes higher than the high level of the input signal In ((2)). When a high voltage is applied to the gate of Tr1, the high level of the pulse of the clock signal V1 is output to the common output line Out ((3)).
[0013]
However, the following malfunction may occur. The output signal Out modulates the boot capacitance Ecap1 of the unit register 21 for electronic shutter, and the boot transistor ETr1 is turned on ((4) above). When ETr1 is turned on, a low level signal of the clock signal EV1 is output to the common output line Out, and the potential of the common output line Out is lowered ((5)). When the potential of the common output wiring Out decreases, the output signal Next to the next stage register cannot obtain a sufficient voltage, and the worst shift register stops. As described above, the transistor ETr1 is turned on by the sneaking of the output signal Out, and the high level of the clock signal V1 and the low level of the clock signal EV1 collide with each other, so that the output signal Out is lowered to an intermediate potential between them. is there.
[0014]
In particular, the operating voltage margin of the NMOS dynamic logic circuit has decreased with the recent decrease in power supply voltage in camera-equipped mobile phones and digital cameras. In the solid-state imaging device operating at a low voltage, the voltage drop of the output signals Out and Next due to the wraparound of the output signal Out becomes more remarkable.
[0015]
In view of the above problems, an object of the present invention is to provide a solid-state imaging device, a method of a solid-state imaging device, and a camera that include a plurality of shift registers using a dynamic circuit and that do not cause a decrease in output signal even at low voltage operation.
[0016]
[Means for Solving the Problems]
  In order to solve the above problems, a solid-state imaging device of the present invention includes an imaging unit including a plurality of pixels, and a plurality of scanning circuits configured by a dynamic logic circuit and outputting a signal for selecting a row or a column of the imaging unit. A solid-state imaging device including a selection circuit that selects an output signal of any one of the plurality of scanning circuits and outputs the selected signal to the imaging unit.The selection circuit includes a plurality of bootstrap circuits connected to the output signals of the plurality of scanning circuits, and outputs signals obtained by connecting the outputs of the plurality of bootstrap circuits to the imaging unit.
[0017]
According to this configuration, since the outputs of the plurality of scanning circuits are selected by the selection circuit without being connected, the wraparound of the output signal from one scanning circuit to the other scanning circuit is eliminated, and the voltage drop of the output signal is reduced. It has the effect of preventing.
[0019]
According to this configuration, the selection circuit can be easily configured by the plurality of bootstrap circuits connected to the output signals of the plurality of scanning circuits.
[0020]
Here, the bootstrap circuit may be configured to be supplied with a power supply voltage for booting.
[0021]
According to this configuration, since it is not necessary to supply a control pulse to the bootstrap circuit, the circuit configuration of the selection circuit can be simplified.
[0022]
Here, in the bootstrap circuit, the output signal line from the scanning circuit is connected to the gate, the power supply voltage for boot is supplied to one of the drain and the source, and the other of the drain and the source is connected to the imaging unit. A boot transistor to which an output line is connected, a gate of the transistor, and a capacitor connected between the other of the drain and the source may be provided.
[0023]
The bootstrap circuit may be supplied with a selection pulse for selecting a scanning circuit for booting.
[0024]
According to this configuration, the bootstrap circuit outputs the logical product of the output signal from the scanning circuit and the selection pulse, so that the output signal of the scanning circuit to which the selection pulse is applied can be selected, and the imaging unit can be selected by the selection pulse. The width and timing of the output signal to can be adjusted.
[0025]
Here, in the bootstrap circuit, the output signal line from the scanning circuit is connected to the gate, the selection pulse is supplied to one of the drain and the source, and the output line to the imaging unit is the other of the drain and the source Are connected to each other, a boot transistor connected to each other, a gate of the boot transistor, and a capacitor connected between the drain and the source. The capacitive element may be configured by a gate capacitance of an enhancement type transistor in which a drain and a source are short-circuited.
[0026]
According to this configuration, the enhancement type transistor is provided as a capacitive element on the opposite side to the output side of the bootstrap circuit, thereby eliminating the wraparound of the output signal from one scanning circuit to the other scanning circuit and the scanning circuit. When the output signal from is low level, the boot operation can be surely prohibited. In addition, only the bootstrap circuit to which the selection pulse is input operates, and selection control by the pulse and output signal timing control by the timing of the pulse can be performed.
[0027]
Here, the output signal line connected to the gate of the boot transistor may have a switch transistor inserted in series.
[0028]
According to this configuration, when the switch transistor is off, the signal held in the gate capacitance of the boot transistor is maintained even after the output signal line becomes low level. Can be set to In addition, after the output signal line becomes low level, the signal held in the gate capacitance of the boot transistor can be reset at any timing by turning on and off the switch transistor.
[0029]
The solid-state imaging device driving method and the camera including the solid-state imaging device according to the present invention also have the same means, operations, and effects as described above.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 is a diagram illustrating a schematic configuration of a main part of the solid-state imaging device according to Embodiment 1 of the present invention. This solid-state imaging device includes scanning circuits 1 and 2, a selection circuit 3, and an imaging unit 10. The scanning circuits 1 and 2 and the imaging unit 10 are the same as those in FIG. The selection circuit 3 is composed of a plurality of unit selection circuits (the unit selection circuit 31 is shown in a broken line in the figure). Each unit selection circuit receives output signals Out and EOut from the unit registers of the scanning circuits 1 and 2 and outputs a logical sum of them without lowering the voltage.
[0031]
FIG. 2A is a circuit diagram showing a configuration of the unit selection circuit 31. As shown in the figure, the unit selection circuit is composed of two bootstrap circuits for taking the logical sum of the output signal Out from the unit register 11 of the scanning circuit 1 and the output signal EOut from the unit register 21 of the scanning circuit 2. . The bootstrap circuit corresponding to the output signal Out includes a transistor Tr3 and a boot capacitor C. On the other hand, the bootstrap circuit corresponding to the output signal EOut includes a transistor Tr3E and a boot capacitor CE. Both the transistors Tr3 and Tr3E are connected to the power supply voltage VDD. Further, the output signals Out and EOut are not connected and connected to the gates of the transistors Tr3 and Tr3E, respectively. This prevents the shift register that outputs the selection signal (high level) to the imaging unit 10 from modulating the shift register that does not output the selection signal (high level).
[0032]
FIG. 2B is a time chart showing the operation timing of the unit selection circuit 31. In the figure, the gate signal In of the transistor Tr3, the output signal EOut from the unit register 21 and the output from the selection circuit 31 to the imaging unit 10 when only Out is the high level among the output signals Out and Eout. The signal Transout is shown.
[0033]
When the output signal Out of the unit register 11 becomes high level ((1) in the figure), the transistor Tr3 is turned on, and the power supply voltage VDD is connected to the transistor Tr3, so that the transistor Tr3 is connected via the boot capacitor Cap1. The gate voltage is boosted (hereinafter referred to as boot), and the gate voltage In is higher than the high level ((3)). The power supply voltage VDD is output to the output signal Transout via the transistor Tr1 ((4)).
[0034]
At this time, even if the high level of the output signal Transout goes around to the other boot capacitor CE and, as a result, the transistor Tr3E is turned on, the transistor Tr3E is also connected to the power supply voltage VDD, so the high level of the output signal Transout is , Maintained without voltage drop.
[0035]
As described above, according to the unit selection circuit in the present embodiment, in the two bootstrap circuits that take the logical sum of the two output signals and output to the imaging unit 10 as the selection signal Transout, Is connected to the power supply voltage VDD. As a result, even if the selection signal Transout goes into the other boot capacitor and the other boot transistor is turned on, the voltage drop of the selection signal Transout does not occur.
[0036]
(Embodiment 2)
FIG. 3 is a diagram illustrating a schematic configuration of a main part of the solid-state imaging device according to the present embodiment. This solid-state imaging device is different from the solid-state imaging device shown in FIG. 1 in that a selection circuit 4 is provided instead of the selection circuit 3. Hereinafter, the description of the same points is omitted, and different points are mainly described.
[0037]
The selection circuit 4 is composed of a plurality of unit selection circuits (the inside of a broken line in the figure is a unit unit circuit 41). The unit selection circuit 41 is different from the unit selection circuit 31 shown in FIG. 2 in that the boot transistor is connected to the TRANS signal and the ETRANS signal instead of being connected to the power supply voltage VDD. Here, the TRANS signal and the ETRANS signal are pulse signals that control selection of the output signal Out and the output signal EOut in the unit selection circuit 41.
[0038]
Before describing the detailed configuration of the unit selection circuit 41 (FIG. 6), first, comparative configuration examples considered in the process leading to the configuration of the unit selection circuit 41 are shown in FIGS. 4 (a), 4 (b), and 5 (a). ) (B).
[0039]
The unit selection circuit in FIG. 4A includes a bootstrap circuit for taking the logical product of the selection pulse TRANS during normal reading and the output signal Out from the scanning circuit for normal reading, and the selection pulse during electronic shutter operation. A bootstrap circuit for taking the logical product of ETRANS and the output signal EOut from the scanning circuit for electronic shutter operation is provided, and the output of each bootstrap circuit is electrically connected.
[0040]
The output signal Out and the output signal EOut of the two scanning circuits can be selected by independent bootstrap circuits and selection pulses TRANS, ETRANS.
[0041]
FIG. 4B is a time chart showing the operation timing of the bootstrap circuit of FIG. For example, when the high level of the output signal Out is applied from the scanning circuit 1 for normal reading, the gate capacitance of the boot transistor Tr3 is held at timing (1). When the selection pulse TRANS is applied at the timing of (2), the gate voltage of the transistor Tr1 is booted ((3)), and the selection signal TRANSOUT is output as shown in (4).
[0042]
In this way, if the output signal Out is at a high level at the timing when the selection pulse TRANS is applied, it is output as the selection signal TRANSOUT. The same applies when the selection pulses TRANS and ETRANS are reversed.
[0043]
Thereby, it appears as if the output of one scanning circuit does not affect the other scanning circuit.
[0044]
The problem at the time of the low voltage operation in the comparative configuration example of FIG. 4A will be described with reference to FIGS.
[0045]
5 (a) and 5 (b), the selection signal TRANSOUT output at timing (4) wraps around the bootstrap capacitor CE for the scanning circuit 2, and as shown in (5), The gate voltage of the boot transistor Tr3E is increased. When the transistor Tr3E is turned on, an ETRANS “L” signal is output to TRANSOUT, and the voltage of TRANSOUT decreases ((6)). (At this time, since a high voltage is applied to the gate of Tr3 and a low voltage is applied to the gate of Tr3E, the on-resistance of Tr3 is low and the on-resistance of Tr3E is high.) Even if the voltage drops slightly, the image quality is not affected. However, if the power supply voltage is lowered, the voltage margin of TRANSOUT disappears, and if the voltage drops even a little, the image quality deteriorates.
[0046]
FIG. 6A is a circuit diagram showing a detailed configuration of the unit selection circuit 41 that solves the problem at the time of low voltage operation. Compared with FIG. 4A, the configuration of FIG. 4A includes enhancement type transistors Tr4 and Tr4E as boot capacitors instead of the boot capacitors C and CE, and the connection position thereof is the output of the boot transistor. The difference is that it is not on the side (Transout) but on the selection signal line Trans, ETrans side. In this enhancement type transistor Tr4, the source and drain are connected and connected to the Trans signal line, and the gate is connected to the output signal Out and the gate of the transistor Tr3. The enhancement type transistor Tr4 does not conduct when the gate voltage is equal to or lower than the threshold value, and does not function as a boot capacitor, and has a characteristic of conducting when the gate voltage exceeds the threshold value and functioning as a boot capacitor. The same applies to the enhancement type transistor Tr4E.
[0047]
FIG. 6B is a time chart showing the operation timing of FIG. Although the selection signal Transout of the image pickup unit is output at timing (4), since the boot capacitors are connected to different selection pulse TRANS signal lines and ETRANS signal lines as shown in FIG. 6, the high level of the selection signal Transout is high. Since there is no path through which the level goes around the gate of the transistor Tr3E, the transistor Tr3E is not turned on (broken line (5)), and the voltage of the selection signal Transout is prevented from being lowered (broken line (4)). As described above, according to the configuration shown in FIG. 6A, the output of one bootstrap circuit does not cause the other bootstrap circuit to operate erroneously.
[0048]
The reason why the enhancement type capacitor is used as the boot capacitor will be described with reference to FIG. As shown in FIG. 7, when there is no output from the scanning circuit 1, the gate voltage of the transistor Tr3 is at a low level. At this time, even if the selection pulse TRANS is applied to the transistor Tr3, the output of TRANSOUT is prohibited.
[0049]
If a boot capacitor that always operates as a capacitor regardless of the voltage is provided instead of the enhancement type transistor Tr4, when the TRANS signal is applied at the timing of (2), (3) '(broken line) ), The boot transistor Tr3 is turned on, and TRANOUT is erroneously output as indicated by (4) '(dashed line).
[0050]
On the other hand, when the enhancement type transistor Tr4 is provided as a boot capacitor as shown in FIG. 7, if the gate voltage is low level, the transistor Tr4 is not turned on even if the TRANS signal is applied at timing (2). No operation is performed (3). As a result, it is not output to TRANOUT (4).
[0051]
The bootstrap circuit including the boot transistor 3E and the enhancement type transistor Tr4E is the same as described above.
[0052]
As described above, the selection circuit according to the second embodiment includes the enhancement type transistor as the boot capacitor on the opposite side to the output of the bootstrap circuit (Transout signal), thereby eliminating the wraparound of the Transout signal and the output signal Out. When is at a low level, the boot operation can be surely prohibited. In addition, only the bootstrap circuit to which the pulses of the selection signals Trans and ETTrans are input operates, and selection control by the pulses and output timing control of the output signal Transout can be performed by the timing of the pulses.
[0053]
(Modification)
FIG. 8A is a diagram showing a modification of the unit selection circuit 41 shown in FIG. The unit selection circuit of FIG. 6A differs from the unit selection circuit 41 in that switch transistors Tr5 and Tr5E are newly added. The switch transistor Tr5 is connected in series between the output signal line Out and the gate of the transistor Tr3 from the scanning circuit 1, and a clock signal Clk is input to the gate of the switch transistor Tr5 to maintain a signal held in the gate capacitance of the transistor Tr3. And function as a switch for controlling reset. The same applies to the switch transistor Tr5E.
[0054]
FIG. 8B is a time chart showing the operation timing of the unit selection circuit of FIG. At the timing of {circle around (1)}, the switch transistor Tr5 is turned on / off by the pulse of the clock signal Clk. At this time, the high level of the output signal Out of the scanning circuit is input and held in the boot transistor Tr3 while the switch transistor Tr5 is on. Further, after the switch transistor Tr5 is turned off, the high level signal held in the boot transistor Tr3 is maintained even if the output signal Out becomes low level. Further, after the boot operation is performed at the timings {circle around (2)}, {circle around (3)}, {circle around (4)}, the switch transistor Tr5 is turned on / off again by the pulse of the clock signal Clk at the timing {circle around (5)}. At this time, since the output signal Out is at a low level, the signal held in the boot transistor is reset.
[0055]
As described above, according to the unit selection circuit of FIG. 8A, by providing the switch transistors Tr5 and Tr5E, the signal held in the gate capacitances of the boot transistors Tr3 and 3E is output to the output signal Out. After that, the pulse input timing of the selection signals Trans and ETrans can be set flexibly. In addition, the signal held in the gate capacitances of the boot transistors Tr3 and 3E can be reset at an arbitrary timing after the output signal Out becomes low level.
[0056]
Note that the gate voltage threshold Vt3 for turning on the boot transistor Tr3 and the gate voltage threshold Vt5 for turning on the switch transistor Tr5 and Vt5 are high and Vt5 is low particularly in the case of low voltage operation. Is desirable. That is, the boot transistor Tr3 has a high threshold voltage characteristic that is kept off until a high level is obtained from the output signal Out. The switch transistor Tr5 has a high level of the output signal Out that passes through the switch transistor Tr5. It is desirable to have a low threshold voltage characteristic in order to make it easy to turn on.
[0057]
FIG. 9A is a diagram showing a modification of the unit selection circuit 31 shown in FIG. The unit selection circuit shown in the figure is different from the unit selection circuit 31 in that switch transistors Tr5 and Tr5E are newly added. The switch transistor Tr5 functions as a switch for controlling the maintenance and reset of the signal held in the gate capacitance of the boot transistor, as in FIGS.
[0058]
As described above, according to the unit selection circuit of FIG. 9A, since the switch transistors Tr5 and Tr5E are provided, the interval between the two pulses of the clock signal Clk and the output signal Transout are maintained at the high level. The width of the output signal Transout can be flexibly set by two pulse intervals.
[0059]
In each of the above embodiments, two scanning circuits have been described. However, three or more scanning circuits may be used. In that case, a bootstrap circuit may be provided for each output signal from the plurality of scanning circuits, and the output of each bootstrap circuit may be connected to be used as a selection output signal to the imaging unit 10.
[0060]
In each of the above embodiments, the scanning circuits 1 and 2 have shown configuration examples in the case where a row selection signal for selecting a row of the imaging unit 10 is output. The same applies to the configuration example when the column selection signal to be selected is output. For example, when the scanning circuit 1 outputs a column selection signal for normal scanning and the scanning circuit 2 outputs a column selection signal for scanning in the reverse direction, a normal image and a horizontally reversed image can be selected.
[0061]
【The invention's effect】
According to the solid-state imaging device of the present invention, since the wraparound of the output signal from one scanning circuit to the other scanning circuit is eliminated, it is possible to prevent the output signal from being lowered.
[0062]
Here, if the power supply voltage is supplied to the bootstrap circuit for booting, it is not necessary to supply a control pulse to the bootstrap circuit, so that the circuit configuration of the selection circuit is simplified. Can do.
[0063]
If the bootstrap circuit is supplied with a selection pulse for selecting a scanning circuit for booting, the bootstrap circuit outputs a logical product of the output signal from the scanning circuit and the selection pulse. Therefore, the output signal of the scanning circuit to which the selection pulse is applied can be selected, and the width and timing of the output signal to the imaging unit can be adjusted by the selection pulse.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a schematic configuration of a solid-state imaging device according to a first embodiment.
FIG. 2A is a circuit diagram showing a configuration of a unit selection circuit.
(B) It is a time chart which shows the operation timing of a unit selection circuit.
3 is a diagram illustrating a schematic configuration of a main part of a solid-state imaging device according to Embodiment 2. FIG.
FIG. 4A is a diagram showing a comparative configuration example considered in the process leading to the configuration of a unit selection circuit.
(B) It is a time chart which shows the operation timing.
FIG. 5A is a diagram showing a comparative configuration example considered in the process leading to the configuration of the unit selection circuit.
(B) It is a time chart which shows the operation timing.
FIG. 6A is a circuit diagram showing a configuration of a unit selection circuit.
(B) It is a time chart which shows the operation timing of a unit selection circuit.
FIG. 7A is an operation explanatory diagram of a unit selection circuit.
(B) It is a time chart which shows the operation timing.
FIG. 8A is a diagram showing a modification of the unit selection circuit.
(B) It is a time chart which shows the operation timing.
FIG. 9A is a diagram showing another modification of the unit selection circuit.
(B) It is a time chart which shows the operation timing.
FIG. 10 is a diagram illustrating a schematic configuration of a conventional solid-state imaging device.
FIG. 11A is a circuit diagram showing a configuration in which outputs of unit registers of a plurality of scanning circuits are connected.
(B) It is a time chart which shows the operation timing.
[Explanation of symbols]
1 Scanning circuit
2 Scanning circuit
3 Selection circuit
4 Selection circuit
31 Unit selection circuit
41 Unit selection circuit
Tr3 boot transistor
Tr4 enhancement type transistor
Tr5 switch transistor

Claims (9)

A solid-state imaging device having an imaging unit including a plurality of pixels and a plurality of scanning circuits configured by a dynamic logic circuit and outputting a signal for selecting a row or a column of the imaging unit,
A selection circuit that selects an output signal of any one of the plurality of scanning circuits and outputs the selected signal to the imaging unit ;
The selection circuit is also be output from a plurality of bootstrap circuits connected to the respective output signals of the plurality of scan circuits, a signal obtained by connecting the outputs of a plurality of bootstrap circuits on the imaging unit A solid-state imaging device. The bootstrap circuit, solid-state imaging device according to claim 1, wherein the power supply voltage is supplied to the boot. The bootstrap circuit is
An output signal line from the scanning circuit is connected to the gate, the boot power supply voltage is supplied to one of the drain and the source, and an output line to the imaging unit is connected to the other of the drain and the source. When,
The solid-state imaging device according to claim 2 , further comprising: a gate of the transistor, and a capacitor connected between the other of the drain and the source. The bootstrap circuit, solid-state imaging device according to claim 1, wherein the selection pulse for selecting a scanning circuit for booting is supplied. The bootstrap circuit is
An output signal line from the scanning circuit is connected to the gate, the selection pulse is supplied to one of the drain and the source, and a boot transistor to which the output line to the imaging unit is connected to the other of the drain and the source;
The solid-state imaging device according to claim 4 , further comprising: a gate of the boot transistor; and a capacitor connected between the drain and the source. The solid-state imaging device according to claim 5 , wherein the capacitive element is configured by a gate capacitance of an enhancement type transistor in which a drain and a source are short-circuited. The solid-state imaging device further includes:
The solid-state imaging device according to claim 3, wherein the output signal line connected to the gate of the boot transistor has a switch transistor inserted in series. 8. The solid-state imaging device according to claim 7 , wherein a threshold value of a gate voltage for turning on the switch transistor is smaller than a threshold value of a gate voltage for turning on the boot transistor. Camera comprising the solid-state imaging device according to any one of claims 1 to 8.

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