JP4322477B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a plurality of gate insulating films of different film materials or film thicknesses and a manufacturing method thereof, and more particularly to a semiconductor device in which gate insulating films are separately formed and a manufacturing method thereof.
[0002]
[Prior art]
As one of electrically erasable and erasable nonvolatile semiconductor memory devices (EEPROMs), a MONOS type EEPROM that accumulates charges in a silicon nitride film is known. MONOS represents Metal-Oxide-Nitride-Oxide-Semiconductor, and typically represents a metal-silicon oxide film-silicon nitride film-silicon oxide film-semiconductor. In the MONOS type EEPROM, the gate insulating film of the memory cell is an ONO storage film, whereas the transistor constituting the peripheral circuit has a MOS structure having a silicon oxide film as a gate insulating film. Therefore, it is necessary to make both separately in the manufacture of the MONOS type EEPROM.
[0003]
In the method of separately forming transistors having different gate insulating films, it is important to satisfy the following three points: reliability of the gate insulating film, high performance of the memory cell, and securing of a sufficient process margin.
[0004]
There is a method described in Japanese Patent Application Laid-Open No. 8-330436 as a method for separately forming transistors having different gate insulating films. In this known example, after element isolation is formed by the LOCOS method, two types of gate oxide films and gate electrodes having different thicknesses are formed. In recent years, a trench type element isolation method has been used instead of the LOCOS method. Compared with the LOCOS method, the trench type element isolation method has a feature that a fine element isolation width and a good element isolation withstand voltage can be realized.
[0005]
A method of separately forming a MONOS memory cell and a MOS peripheral transistor using the trench type element isolation method shown in FIGS. 60A to 60E will be described. Here, the gate insulating film and the gate electrode are formed after the element isolation formation, as in the technique described in Japanese Patent Laid-Open No. 8-330436, which is a known example. In the figure, MC indicates a memory cell region and PTR indicates a peripheral transistor region.
[0006]
First, as illustrated in FIG. 60A, the element isolation region 201 is formed on the semiconductor substrate 200. Next, as shown in FIG. 60B, the sacrificial oxide film is removed by wet etching to form the gate insulating film 202 and the gate electrode 203 of the peripheral circuit transistor. Further, the peripheral circuit region is covered with a resist layer 204.
[0007]
Next, as shown in FIG. 60C, the gate electrode and the gate oxide film in the memory cell region are removed. Next, after depositing an ONO film 205 which is a gate insulating film of a memory cell over the entire surface of the semiconductor substrate 200, a memory cell gate electrode 206 is deposited. Subsequently, the memory cell region is covered with a resist layer 207, and the memory cell gate electrode 206 and the ONO film 205 in the peripheral circuit region are removed. Next, as shown in FIG. 60D, the resist layer 207 is removed. Thereby, it is possible to make a peripheral MOS transistor and a MONOS memory cell separately.
[0008]
However, this method has the following problems. The first problem relates to the nonuniformity of the ONO film. The element isolation edge is not flat and there is a step, so that it is difficult to deposit the ONO film with a uniform film thickness and film quality. This causes variations in the program characteristics and data retention characteristics of the memory cells.
[0009]
The second problem relates to the parasitic transistor as shown in FIG. 60E, which is an enlarged view of the region TP in FIG. During the wet etching before forming the gate insulating film, a part of the buried oxide film in the element isolation trench is etched at the element isolation end. A parasitic transistor is formed by the gate electrode entering there. For this reason, both memory cells and peripheral transistors cause characteristic variations.
[0010]
In this conventional example, a peripheral transistor and then a memory cell transistor are formed first, but this problem is not solved even if the order of making is changed. The above problems are caused by the separate formation of the gate insulating film after the element isolation region is formed. In the conventional example described below, the above problems are solved by forming a gate insulating film separately prior to the formation of the element isolation region.
[0011]
As a method for solving the above problem, for example, “1998 Symposium on VLSI Technology Digest of Technical Papers, pp.102-103,“ A self-Aligned STI Process Integration for Low Cost and Highly Reliable 1 Gbit Flash Memories ”, Y. Takeuchi et al. describes a self-aligned trench isolation method that forms trench isolation after formation of a gate insulating film and a gate electrode. 61A to 61D, the steps of the manufacturing method for separately forming the MONOS cell and the MOS peripheral transistor will be described.
[0012]
First, as shown in FIG. 61A, impurity implantation of wells and channels is performed to form a memory cell well 205 and a peripheral circuit well 206. Next, the ONO film 207 and the silicon oxide film 208 are separately formed. Next, a gate electrode 209 made of polysilicon and a mask silicon nitride film 210 are deposited. Next, as shown in FIG. 61B, an element isolation trench 211 is formed in the semiconductor substrate 200. A silicon oxide film 212 is deposited on the exposed surface to fill the element isolation trench 211.
[0013]
Next, as shown in FIG. 61C, the silicon oxide film 212 is removed by a CMP (Chemical Mechanical Polishing) method until the surface on the mask silicon nitride film 210 is exposed, and the surface is flattened. . Next, as shown in FIG. 61 (d), the mask silicon nitride film 210 is removed, and a tungsten silicide layer 213 is deposited. Next, a memory cell element isolation region 214, a boundary element isolation region 215, and a peripheral circuit element isolation region 216 are formed, and each gate electrode is processed. This method solves the problems of ONO film non-uniformity and element isolation oxide film etching as shown in FIG.
[0014]
[Problems to be solved by the invention]
  The present invention has a plurality of gate insulating films having different film materials or film thicknesses.Manufacturing method of semiconductor deviceThe purpose is to improve the reliability.
[0015]
[Means for Solving the Problems]
  According to the first aspect of the present invention,A method for manufacturing a semiconductor device is provided, which is provided on a semiconductor substrate having a main surface including first and second regions and a boundary portion disposed between and in contact with the first and second regions. Forming a first insulating film; and disposing a first lower electrode layer on the first region of the first insulating film and a portion in the boundary portion, while in the second region of the first insulating film. And exposing the main surface to form a second insulating film on the first lower electrode layer in the first region and the boundary and on the main surface in the second region The second insulating film has a film material or a film thickness different from that of the first insulating film, and a second lower side on the second region and the portion in the boundary portion of the second insulating film. While disposing the electrode layer, removing the portion in the first region of the second insulating film to remove the first lower electrode And forming a laminated portion in which the end portions of the second insulating film and the second lower electrode layer are laminated on the upper surface of the end portion of the first lower electrode layer in the boundary portion; Etching the main surfaces in the first and second regions in a self-aligned manner with respect to the first and second lower electrode layers to form trenches for element isolation in the first and second regions. Simultaneously with the formation, the main surface in the boundary portion is pattern-etched from above to form a trench for element isolation in the boundary portion, and the bottom portion of the trench in the boundary portion is caused by the stacked portion. A step of forming an upward convex portion, a step of filling the trench in the first and second regions and the boundary portion with an insulating layer to form an element isolation region, and the first and second lower electrode layers Forming an upper electrode layer thereon; And pattern etching the first and second lower electrode layers and the upper electrode layer to form first and second gate electrodes in the first and second regions. .
[0016]
    According to a second aspect of the present invention,A method for manufacturing a semiconductor device is provided, which is provided on a semiconductor substrate having a main surface including first and second regions and a boundary portion disposed between and in contact with the first and second regions. Forming a first insulating film; and disposing a first lower electrode layer on the first region of the first insulating film and a portion in the boundary portion, while in the second region of the first insulating film. And exposing the main surface to form a second insulating film on the first lower electrode layer in the first region and the boundary and on the main surface in the second region The second insulating film has a film material or a film thickness different from that of the first insulating film, and a second lower side on the second region and the portion in the boundary portion of the second insulating film. While disposing the electrode layer, removing the portion in the first region of the second insulating film to remove the first lower electrode Exposing a gap between the end of the second lower electrode layer and the end of the first lower electrode layer within the boundary, and the first and second lower sides Etching the main surface in the first and second regions in a self-aligned manner with respect to the electrode layer to form a trench for element isolation in the first and second regions, and at the same time, the boundary Pattern-etching the main surface in a portion from above, forming a trench for element isolation in the boundary, and forming a downward convex portion due to the gap in the bottom of the trench in the boundary; A step of filling the trenches in the first and second regions and the boundary with an insulating layer to form an element isolation region; and a step of forming an upper electrode layer on the first and second lower electrode layers And the first and second lower electrode layers Fine said upper electrode layer pattern etched and characterized by comprising a step of forming a first and a second gate electrode on the first and second regions.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
In the course of the development of the present invention, the present inventors studied the problems of the semiconductor device and its manufacturing method as described with reference to FIGS. 61 (a) to (d). As a result, the present inventors have obtained knowledge as described below.
[0018]
In the semiconductor device shown in FIG. 61 (d), the trench element isolation depth of the boundary element isolation region 215 between the MONOS transistor and the MOS transistor is equal to the trench depth of the MONOS region element isolation region 214 and the MOS region element isolation region 216. Is the same as the trench depth. On the other hand, the trench width in the boundary element isolation region 215 is wider than the trench isolation widths 214 and 216 in other transistor regions.
[0019]
In the trench element isolation region, after filling the trench with an oxide film as shown in FIG. 61B, the buried oxide film is flattened by CMP as shown in FIG. However, the wide trench width at the boundary causes problems as shown in FIGS. 62 (a) and 62 (b).
[0020]
The first problem is the trench fillability. Since the boundary trench is wide, when the buried oxide film is thin, an insufficiently buried region Q is formed in the central portion of the trench at the boundary as shown in FIG. When wet etching is used in a later process, the insufficiently embedded region is largely etched, resulting in poor embeddability. To solve this problem, it is necessary to deposit the buried oxide film thickly, but not only the oxide film deposition but also the amount of polish in the subsequent CMP process is increased, which increases the process cost. I will let you.
[0021]
The second problem is CMP uniformity. As a characteristic of CMP, there is dishing in which a wide space portion is greatly sharpened. Since the trench at the boundary is wide, dishing is likely to occur. In this case, as shown in FIG. 62B, dishing affects the transistor region and deforms the gate electrode shape, thereby reducing the process margin and the yield.
[0022]
The above problems are caused by the fact that the trench at the boundary is wide in width although the depth is the same as the transistor region. If the width of the trench at the boundary is narrowed in order to solve this problem, the element isolation breakdown voltage is lowered. In this case, since the withstand voltage between the wells becomes insufficient, it is difficult to solve the problem by this method. For this reason, for a semiconductor device having two or more different types of gate insulating films, an apparatus structure and a manufacturing method that are highly reliable and can achieve both a sufficient process margin and device performance are required.
[0023]
Hereinafter, an embodiment of the present invention configured based on such knowledge will be described with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.
[0024]
(First embodiment)
FIG. 1A is a cross-sectional view showing the vicinity of the boundary portion of the semiconductor device according to the first embodiment. FIGS. 1B, 2A, and 2B are cross-sectional views showing the vicinity of the boundary portion of the semiconductor device according to the modification of the first embodiment. What is characteristic of this embodiment is that two types of transistors (for example, first and second transistor regions TR1 and TR2) having different gate insulating film types, for example, film material and film thickness, are the same semiconductor substrate. The boundary BS between the two is different from both of them in terms of the shape of the element isolation region or the electrode structure (the shape of the element isolation portion or the electrode structure in the first and second transistor regions TR1 and TR2). Is to include things. Specifically, a trench type element isolation region having a different depth depending on the portion or an electrode structure having a different thickness depending on the portion is disposed in the boundary portion BS.
[0025]
The semiconductor memory device shown in FIG. 1A has first and second transistor regions TR1 and TR2 disposed on a semiconductor substrate 1, and a boundary BS sandwiched between and in contact with the first and second transistor regions TR1 and TR2. . When the first transistor region TR1 is a high breakdown voltage transistor region, the gate insulating film 2 formed on the semiconductor substrate 1 is formed of a silicon oxide film having a thickness of about 10 nm to 40 nm. When the second transistor region TR2 is a low voltage transistor region, the gate insulating film 3 formed on the semiconductor substrate 1 is formed of a silicon oxide film having a thickness of about 1 nm to 10 nm. When the second transistor region TR2 is a memory cell region, the gate insulating film 3 is formed of a silicon oxide film having a thickness of about 1 nm to 10 nm or an ONO film having a thickness of about 10 nm to 50 nm.
[0026]
In the apparatus shown in FIG. 1A, at least two of the above-described three types of transistor regions are arranged adjacent to each other with different types of gate insulating films or different gate insulating film thicknesses. The semiconductor substrate 1 may have a well of the opposite conductivity type to the semiconductor substrate formed in the vicinity of the surface thereof. Further, another well having the same conductivity type as that of the semiconductor substrate may be formed on the opposite conductivity type well (the same applies hereinafter).
[0027]
In the first transistor region TR1, the lower electrode layer 4 is formed on the gate insulating film 2, the upper electrode layer 5 is formed thereon, and the first gate electrode 6 is formed. A pair of source / drain diffusion layers 7 implanted using the first gate electrode 6 as a mask are formed in the semiconductor substrate 1. The first gate electrode 6 and the source / drain diffusion layer 7 form the first transistor 8. A polysilicon layer or the like is used for each of the lower electrode layer 4 and the upper electrode layer 5.
[0028]
A trench type element isolation region 9 is disposed in the boundary portion BS shown in FIG. At the bottom of the trench in the element isolation region 9, a step having a convex portion 10 that is convex upward is formed, and the trench has a partially different depth. The width of the convex portion 10 in the direction connecting the first and second transistor regions TR1 and TR2 is about 100 nm to 10000 nm, preferably about 100 nm to 1000 nm. The height of the convex portion 10 from the deep portion of the bottom of the trench is about 10 nm to 300 nm, preferably about 30 nm to 100 nm. This height changes depending on the film thickness of the gate electrode material in the adjacent first and second transistor regions TR1 and TR2. The width of the portion 10 that protrudes above the bottom of the element isolation region 9 is given in consideration of lithography misalignment in the manufacturing process, and is, for example, about 100 nm to 10000 nm.
[0029]
In the second transistor region TR2 adjacent to the boundary part BS, the lower electrode layer 11 is formed on the gate insulating film 3, the upper electrode layer 12 is formed thereon, and the second gate electrode 13 is formed. A pair of source / drain diffusion layers 14 implanted with the second gate electrode 13 as a mask is formed in the semiconductor substrate 1. The second gate electrode 13 and the source / drain diffusion layer 14 form the second transistor 15. A polysilicon layer or the like is used for each of the lower electrode layer 11 and the upper electrode layer 12. Further, another element isolation region can be provided between the left and right transistors 8 and 15 and the element isolation region 9.
[0030]
In the semiconductor memory device shown in FIG. 1B, the configuration of the first and second transistor regions TR1 and TR2 is the same as that in FIG. 1A, and the configuration at the boundary BS is shown in FIG. Different from the configuration. Around the element isolation region 9, the lower electrode layer 4 is formed on the first gate insulating film 2, and the lower electrode layer 11 is formed on the second gate insulating film 3. Further, the upper electrode layer 16 is formed on the element isolation region 9 and the lower electrode layers 4 and 11 around the element isolation region 9, and a gate structure 17 is formed.
[0031]
In this configuration, the gate structure 17 is preferably electrically insulated from the gate electrodes 6 and 13 of the first and second transistor regions TR1 and TR2. Further, another element isolation region can be provided between the left and right transistors 8 and 15 and the element isolation region 9.
[0032]
1A and 1B is characterized in that there is a step at the bottom of the trench of the element isolation region 9 at the boundary BS, and in particular, there is a convex portion 10 that is convex upward. is there. Further, the depth of the trench in the element isolation region 9 is different between the portion on the first transistor region TR1 side and the portion on the second transistor region TR2 side.
[0033]
In the structure shown in FIGS. 1A and 1B, since the element isolation depth is shallow at the center of the element isolation region 9, good embeddability can be obtained and the manufacturing yield can be improved. One reason is that in the step of embedding the element isolation trench formed in the semiconductor substrate with an insulator, the embedding aspect ratio is reduced and the embedding characteristic is improved. Another reason is that in the step of embedding an insulator in the element isolation trench, the degree of formation of a depression on the upper surface of the element isolation central portion is reduced, and the upper surface of the insulator is flattened to a predetermined height and removed. This is because dishing can be prevented.
[0034]
Furthermore, since the gate structure 17 on the element isolation region 9 shown in FIG. 1B is the same as the gate structure of the first and second transistor regions TR1 and TR2, the processing is easy.
[0035]
In the semiconductor memory device shown in FIG. 2A, the configurations of the first and second transistor regions TR1 and TR2 are the same as those in FIGS. 1A and 1B, and the configuration at the boundary BS is shown in FIG. It differs from the configuration shown in a) and (b). In the boundary portion BS, the first gate insulating film 2 is formed from the first transistor region TR1 side to the center, and the second gate insulating film 3 is formed from the second transistor region TR2 side to the center. In the boundary portion BS, an electrode layer 20 made of the same material as that of the lower electrode layer 4 is formed on a part of the upper surface of the first gate insulating film 2 and a part of the upper surface of the second gate insulating film 3. A sidewall insulating film 21 made of the same material as that of the second gate insulating film 3 is formed on the side surface of the electrode layer 20 on the second transistor region TR2 side. The height of the electrode layer 20 at the boundary BS is lower than the height of the lower electrode layer 4 in the first transistor region TR1 and the lower electrode layer 11 in the second transistor region TR2.
[0036]
The element isolation region is formed between the first and second transistor regions TR1 and TR2 and the boundary portion BS when necessary for well isolation or the like.
[0037]
In this shape, the gate processing margin in the transistor region is improved by processing so that a part of the gate electrode layer in the transistor region is left in the boundary portion BS. In particular, when a fine memory cell transistor or the like is formed in the transistor region, the effect of improving the gate processing margin is remarkable. Further, since an element isolation region having a special shape as shown in FIGS. 1A and 1B is not created, processing is easy.
[0038]
Further, the semiconductor substrate is not etched in the boundary portion BS, and the electrode layer in the boundary portion BS is not removed. For this reason, since the film thickness of the electrode layer to be etched is also the same as the film thickness of the gate electrode of the transistor, there is no decrease in yield due to the processing of the boundary portion BS.
[0039]
In the semiconductor memory device shown in FIG. 2B, the configurations of the first and second transistor regions TR1 and TR2 are the same as those in FIGS. 1A and 1B, and the configuration at the boundary BS is shown in FIG. It differs from the configuration shown in a) and (b). Similar to the structure of FIG. 2A, in the boundary portion BS, the first gate insulating film 2 is formed from the first transistor region TR1 side to the center, and the second gate insulating film 3 is formed from the second transistor region TR2 side to the center. Is done. At the boundary BS, the first electrode layer 22 having the same material and the same thickness as the lower electrode layer 4 is formed on the first gate insulating film 2. In addition, a horizontal portion of the second electrode layer 23 is formed on the second gate insulating film 3 at the boundary BS, and is adjacent to the first electrode layer 22 via the insulating film 24. The second electrode layer 23 has the same material and the same film thickness as the lower electrode layer 11.
[0040]
The thickness of the insulating film 24 is the same as that of the second gate insulating film 3. In the boundary portion BS, the second electrode layer 23 has a vertical portion stacked on the horizontal portion, and a stacked portion extending from the vertical portion toward the first transistor region TR1. That is, the second electrode layer 23 is laminated on a part of the first electrode layer 22 via the insulating film 24. Further, the laminated electrode layer 25 is formed on the first and second electrode layers 22 and 23. A gate structure 18 is formed by the first electrode layer 22, the second electrode layer 23, the insulating film 24, and the stacked electrode layer 25. Due to such a structure, the height of the gate structure 18 is higher than the height of the transistors formed in the first and second transistor regions TR1 and TR2 at the boundary BS.
[0041]
The semiconductor memory device shown in FIG. 2B is characterized in that there is a portion where the gate structure has a stacked structure in the boundary portion BS. In this portion, the first gate insulating film 2 and the first electrode layer 22 having the same film thickness and composition as the lower electrode layer 4 are stacked on the semiconductor substrate 1. Further, a second electrode layer 23 having the same thickness and composition as the upper electrode layer 11 is laminated on the insulating film 24 having the same thickness and composition as the second gate insulating film. Further, both the first and second gate insulating films 2 and 3 exist under the electrically connected first and second electrode layers 22 and 23.
[0042]
In the structure shown in FIG. 2B, the width of the gate structure 18 is, for example, about 100 nm to 10000 nm, and preferably about 500 nm to 1000 nm. The height of the gate structure 18 is the highest part of the boundary BS, and the height of the lower electrode layer 4 and the height of the first gate insulating film 2 are added to the height of the second transistor 15 in the second transistor region TR2. Value.
[0043]
The element isolation region is formed between the first and second transistor regions TR1 and TR2 and the boundary portion BS when necessary for well isolation or the like.
[0044]
By adopting such a structure, a plurality of transistors can be formed on the same semiconductor substrate with a small number of steps.
[0045]
Further, the semiconductor substrate is not etched at the boundary BS, and the stacked gate at the boundary BS is not processed. For this reason, since the film thickness of the electrode layer to be etched is the same as the film thickness of the gate electrode of the transistor, there is no decrease in yield due to the processing of the boundary portion BS. In particular, in the case of the structure shown in FIG. 2B, since the gate electrode having the laminated structure of the boundary portion BS does not need to be etched, the yield is improved.
[0046]
3A and 3B are cross-sectional views showing the first and second transistor regions TR1 and TR2 in the present embodiment along the extending direction of each gate electrode.
[0047]
As shown in FIG. 3A, a plurality of element isolation regions 26 are formed in the semiconductor substrate 1 in the first transistor region TR1. The lower electrode layer 4 is formed between the element isolation regions 26. An upper electrode layer 5 is formed on the lower electrode layer 4. On the upper electrode layer 5, an interlayer insulating film 27 not shown in FIGS. 1A and 1B and FIGS. 2A and 2B is formed.
[0048]
As shown in FIG. 3B, a plurality of element isolation regions 26 are formed in the semiconductor substrate 1 in the second transistor region TR2. The lower electrode layer 11 is formed between the element isolation regions 26. An upper electrode layer 12 is formed on the lower electrode layer 11. On the upper electrode layer 12, an interlayer insulating film 27 not shown in FIGS. 1A and 1B and FIGS. 2A and 2B is formed.
[0049]
As shown in FIGS. 3A and 3B, according to the present embodiment, the element isolation region is formed in a self-aligned manner with respect to the gate electrode. Therefore, the gate electrode does not fall on the side surface of the gate insulating film as described in the prior art at the element isolation end. Thereby, it is possible to prevent the formation of a parasitic transistor at the end of the element isolation region, and to improve the performance of the transistor.
[0050]
In addition, according to the present embodiment, a process of forming a gate insulating film prior to the formation of the element isolation trench and forming the element isolation trench in a self-aligned manner with respect to the gate electrode and the gate insulating film (hereinafter referred to as self-aligned STI). Called process). For this reason, since there is no process for depositing or removing a dummy insulating film or dummy gate for forming an element isolation region, the number of processes can be reduced. Further, in the manufacturing process in this embodiment, since there is no step of directly applying a photoresist on the gate insulating film, the reliability of the gate insulating film can be improved.
[0051]
Next, an example of a method for manufacturing a semiconductor device according to the present embodiment will be described. First, a method for manufacturing the structure shown in FIG. 1A will be described with reference to FIGS.
[0052]
As shown in FIG. 4A, a sacrificial oxide film (not shown) is formed on the upper surface of the semiconductor substrate 1. Next, well impurities and channel impurities are implanted as necessary, and then the sacrificial oxide film is removed. Subsequently, a first gate insulating film 2 such as a silicon oxide film or a silicon nitride film and a lower electrode layer 4 such as polycrystalline silicon are formed on the semiconductor substrate 1.
[0053]
Next, as shown in FIG. 4B, the first transistor region TR1 and from here to the center of the boundary BS are covered with a photoresist layer 30, and the gate electrode layer and the gate insulating film in other regions are removed. . The removal method may be either isotropic etching such as wet etching or anisotropic etching such as RIE.
[0054]
Next, as shown in FIG. 4C, after the photoresist layer 30 is removed, a second gate insulating film 3 such as a silicon oxide film or a silicon nitride film and a polycrystalline silicon layer are formed on the entire surface of the semiconductor substrate 1. The side electrode layer 11 is formed. At this time, the first transistor region TR1 has a stacked structure in which the second gate insulating film 3 and the lower electrode layer 11 are formed on the lower electrode layer 4. Here, the lower electrode layer 4 in the first transistor region TR1 and the lower electrode layer 11 in the second transistor region TR2 may use different materials and film thicknesses. However, if these are the same material and the same film thickness, it is easy to simultaneously etch the gate electrode in a later step.
[0055]
Next, as shown in FIG. 5A, the second transistor region TR2 and from here to the center of the boundary BS are covered with a photoresist layer 31, and the gate electrode layer and the gate insulating film in other regions are removed. . The removal method may be either isotropic etching such as wet etching or anisotropic etching such as RIE. At this time, it is applied to the end portion of the lower electrode layer 4 where a part of the photoresist layer 31 is left. In consideration of misalignment, there are cases where the positions of the end portions of the photoresist layers 30 and 31 overlap with each other, and there are cases where they do not overlap. That is, the gate electrode remains in the laminated structure at the boundary BS where the first and second transistor regions TR1 and TR2 are separately formed.
[0056]
Next, as shown in FIG. 5B, after removing the photoresist layer 31, a first mask layer 32 and a second mask layer 33 are deposited. For example, a silicon nitride film is used for the first mask layer 32, and a silicon oxide film is used for the second mask layer 33, for example. Next, as shown in FIG. 5C, a photoresist layer 34 for forming an element isolation region is deposited on the second mask layer 33 to form an element isolation pattern. The photoresist layer 34 is disposed above the portion where the element isolation region is not formed.
[0057]
Next, as shown in FIG. 6A, the first mask layer 32 and the second mask layer 33 are removed by anisotropic etching, and a portion of the lower electrode layer corresponding to the element isolation region of the boundary BS is formed. 4 and 11 are exposed. Next, as shown in FIG. 6B, the lower electrode layers 4 and 11 exposed from the second mask layer 33 are removed by anisotropic etching.
[0058]
At this time, in the portion corresponding to the element isolation region of the separately formed boundary portion BS, since the two lower electrode layers are laminated before the etching, only the lower electrode layer 11 is etched. . The lower electrode layer 4 remains as the electrode layer 20 on the semiconductor substrate 1. Further, the second gate insulating film 3 remains as the sidewall insulating film 21 in the boundary portion BS. Further, the remaining film 35 remains so that the film thickness decreases from the sidewall insulating film 21 toward the second transistor region TR2 side as the lower electrode layer 11 moves away from the boundary BS.
[0059]
Next, as shown in FIG. 6C, the semiconductor substrate 1 is etched to form an element isolation region. The depth of the trench 36 in the semiconductor substrate 1 formed as the element isolation region is, for example, about 50 nm to 300 nm, and preferably about 150 nm to 250 nm. Due to the step formed by the electrode layer 20, the insulating film 21, and the remaining film 21 shown in FIG. 6B, the convex portion 10 is formed at the bottom of the trench 36 at the boundary portion BS that is separately formed. The step amount of the convex portion 10 depends on the film thickness of the electrode layer 20 remaining in FIG. 6B and the etching conditions, but is, for example, about 10 nm to 300 nm, and preferably about 30 nm to 100 nm.
[0060]
Further, the depth of the bottom of the trench 36 is different between the portion on the first transistor region TR1 side and the portion on the second transistor region TR2 side. This reflects the difference in film thickness between the first gate insulating film 2 and the second gate insulating film 3, and the thinner the gate insulating film, the deeper the groove. Here, the depth of the bottom of the trench 36 on the first transistor region TR1 side is formed to be shallower by about 5 nm to 50 nm, preferably about 10 nm to 30 nm than the depth of the bottom of the trench 36 on the second transistor region TR2 side. This is because the first gate insulating film 2 is thicker than the second gate insulating film 3 by about 5 nm to 50 nm, desirably about 10 nm to 30 nm. At this time, the semiconductor substrate 1 in the first and second transistor regions TR1 and TR2 is etched in a self-aligned manner with respect to the first and second lower electrode layers 4 and 11, and the first and second transistor regions TR1 are etched. , Trenches for the element isolation region 26 (see FIGS. 3A and 3B) are simultaneously formed in TR2.
[0061]
Next, as shown in FIG. 7A, an insulator 37 such as a silicon oxide film is buried in the trench 36 in the boundary BS and the trenches in the first and second transistor regions TR1 and TR2, and the first 2 Deposit on mask layer 33. Since the element isolation depth is shallow at the boundary BS, the embedding property is good. Next, as shown in FIG. 7B, the insulator 37 is etched back using the first mask layer 32 as a stopper by a method such as CMP. After the etch back, the upper portion of the insulator 37 becomes substantially flat.
[0062]
Next, as shown in FIG. 7C, after removing the first mask layer 32, upper electrode layers 5 and 12 are deposited on the entire exposed surface on the semiconductor substrate 1. The upper electrode layers 5 and 12 are made of polycrystalline silicon, a laminated film of polycrystalline silicon and metal or a compound of silicon and metal, or a single layer film of metal or a compound of silicon and metal. Next, as shown in FIG. 8, a photoresist layer 38 for processing the gate electrode layer is deposited to form a pattern. At this time, the photoresist layer 38 is not left at the boundary BS, and therefore, the gate electrode layer at the boundary BS is removed in a later process.
[0063]
Next, as shown in FIG. 1A, the gate electrode layer is anisotropically etched using the photoresist layer 38 as a mask, so that the first gate electrode 6, the second gate electrode 13, and the element isolation region 9 are formed. Form. Thereafter, the processing damage is recovered by post-oxidation or the like. Next, using the first gate electrode 6 and the second gate electrode 13 as a mask, diffusion layer impurities are implanted into the semiconductor substrate 1 to form source / drain diffusion layers 7 and 14. Note that a mask layer such as a silicon nitride film or a silicon oxide film may be deposited on the gate electrode layer, and the gate electrode layer may be processed using the mask layer as a mask.
[0064]
Thereafter, although not shown, an interlayer insulating film, contact plugs, wirings, and the like are formed to complete the semiconductor device. When the element isolation region is formed at the boundary BS in this way, a step remains at the bottom of the element isolation region as shown in FIG.
[0065]
Next, a method for manufacturing the structure shown in FIG. Up to the step of FIG. 7C, the manufacturing method of the structure of FIG. 1A and the manufacturing method thereof are the same.
[0066]
Next, as shown in FIG. 9, a photoresist layer 38 for processing the gate electrode layer and a photoresist layer 39 for forming an electrode layer for element isolation are deposited to form a pattern. Here, the width of the photoresist layer 39 in the left-right direction in FIG. 9 is larger than the width in the left-right direction of the insulator 37 so that the gate electrode layer remains on the side surface of the insulator 37 after etching. Formed.
[0067]
Next, as shown in FIG. 1B, the gate electrode layer is anisotropically etched using the photoresist layers 38 and 39 as a mask, so that the first gate electrode 6, the second gate electrode 13, and the gate structure 17 are etched. And the element isolation region 9 is formed. Thereafter, the processing damage is recovered by post-oxidation or the like. Next, using the first gate electrode 6 and the second gate electrode 13 as a mask, diffusion layer impurities are implanted into the semiconductor substrate 1 to form source / drain diffusion layers 7 and 14. Note that a mask layer such as a silicon nitride film or a silicon oxide film may be deposited on the gate electrode layer, and the gate electrode layer may be processed using the mask layer as a mask.
[0068]
Thereafter, although not shown, an interlayer insulating film, contact plugs, wirings, and the like are formed to complete the semiconductor device. In this way, when the boundary portion BS is an element isolation region, a step remains at the bottom of the element isolation region as shown in FIG.
[0069]
Next, a method for manufacturing the structure shown in FIG. Up to the process of FIG. 5B, the manufacturing method of the structure of FIG.
[0070]
Next, as shown in FIG. 10A, a photoresist layer 40 for forming an element isolation region is coated on the second mask layer 33. In this way, the photoresist is left at the boundary portion BS that is separately formed, and the element isolation region is not formed. After the second mask layer 33 is anisotropically etched, the photoresist layer 40 is removed to expose the second mask layer 33 as shown in FIG. At this time, although not shown, there is a portion where the second mask layer 33 is etched in the first and second transistor regions TR1 and TR2.
[0071]
Next, through the same steps as in FIGS. 6B to 7B, the element isolation region 26 (see FIGS. 3A and 3B) is formed in the first and second transistor regions TR1 and TR2. ). The shape of the boundary portion BS at this time is shown in FIG. Next, as shown in FIG. 11B, after the first mask layer 32 is removed, the upper electrode layers 5 and 12 are formed on the exposed lower electrode layers 4 and 11. Since the boundary portion BS is thus covered with the resist, the gate electrode layer remains in the stacked structure.
[0072]
Next, as shown in FIG. 12A, a photoresist layer 41 for processing the gate electrode layer is deposited to form a pattern. Next, as shown in FIG. 12B, the gate electrode layer is anisotropically etched using the photoresist layer 41 as a mask to form the first gate electrode 6 and the second gate electrode 13. Thereafter, the processing damage is recovered by post-oxidation or the like. Next, using the first gate electrode 6 and the second gate electrode 13 as a mask, diffusion layer impurities are implanted into the semiconductor substrate 1 to form the source / drain diffusion layers 7 and 14 and the diffusion layer 42 at the boundary BS. . Note that a mask layer such as a silicon nitride film or a silicon oxide film may be deposited on the gate electrode layer, and the gate electrode layer may be processed using the mask layer as a mask.
[0073]
Thereafter, although not shown, an interlayer insulating film, contact plugs, wirings, and the like are formed to complete the semiconductor device. When there is no element isolation region at the boundary BS and the gate electrode layer is removed as described above, the shape is as shown in FIG.
[0074]
However, the boundary BS has a shape shown in FIG. 2A when etching residue occurs because the gate electrode layer has a laminated structure. That is, using the first gate electrode 6, the second gate electrode 13, the electrode layer 20 and the sidewall insulating film 21 as a mask, diffusion layer impurities are implanted into the semiconductor substrate 1 to form the source / drain diffusion layers 7 and 14. . Even in this case, there is no problem such as a short circuit of the gate electrode. Further, the etching time can be shortened compared with the case where the gate electrode of the boundary portion BS is completely removed. In addition, the total processing margin is rather improved because the etching conditions need only be optimized in accordance with the transistor region.
[0075]
Next, a manufacturing method of the structure shown in FIG. Up to the step of FIG. 11B, the manufacturing method of the structure of FIG. 2A is the same as the manufacturing method.
[0076]
Next, as shown in FIG. 13, a photoresist layer 41 for processing the gate electrode layer and a photoresist layer 43 for forming the gate structure 18 at the boundary BS are deposited to form a pattern. Next, as shown in FIG. 2B, the gate electrode layer is anisotropically etched using the photoresist layers 41 and 43 as a mask, so that the first gate electrode 6, the second gate electrode 13, and the gate structure are formed. 18 is formed. Thereafter, the processing damage is recovered by post-oxidation or the like. Next, using the first gate electrode 6, the second gate electrode 13 and the gate structure 18 as a mask, diffusion layer impurities are implanted into the semiconductor substrate 1 to form source / drain diffusion layers 7 and 14. Note that a mask layer such as a silicon nitride film or a silicon oxide film may be deposited on the gate electrode layer, and the gate electrode layer may be processed using the mask layer as a mask.
[0077]
Thereafter, although not shown, an interlayer insulating film, contact plugs, wirings, and the like are formed to complete the semiconductor device. As described above, in the shape shown in FIG. 2B, a gate structure in which an electrode layer that has not been processed by etching is stacked on the semiconductor substrate 1 in the boundary portion BS is formed.
[0078]
In general, it is difficult to process the gate electrode because the boundary portion BS is made in a special shape. In this method, since it is not necessary to etch the gate electrode at the boundary BS, the processing is facilitated and the yield is improved. In particular, as shown in FIG. 2 (b), when the gate electrode has a laminated structure in the boundary portion BS, it is particularly difficult to process, so that the effect of not having to process this portion is great. .
[0079]
As described above, in the present embodiment, in a semiconductor device having two or more types of transistors having different gate insulating film thicknesses or film types, the gate insulating film is separately formed prior to the formation of the element isolation trench, By devising the structure, the number of steps can be reduced and the performance of the semiconductor device can be improved.
[0080]
Further, in the present embodiment, the process of separating the trench element or the shape and forming of the gate electrode is devised at the boundary BS where the respective transistor regions in the semiconductor device having two or more different types of gate insulating films are in contact. Thus, the reliability is high, and a sufficient process margin and device performance can be achieved at the same time.
[0081]
In particular, this embodiment is useful in a nonvolatile semiconductor device in which the element isolation region is formed in a self-aligned manner with respect to the gate electrode.
[0082]
In the present embodiment, the gate insulating film is separately formed before the trench element isolation is formed, and the photoresist is not directly applied to the gate insulating film during the separate formation.
[0083]
According to this embodiment, it is possible to provide a semiconductor device in which the element isolation oxide film is not etched at the element isolation end and the reliability of the gate insulating film is high. Further, when an ONO film is used as the gate insulating film of the memory cell, it is possible to prevent the ONO film thickness from becoming nonuniform at the element isolation end.
[0084]
In the structure described in FIGS. 1A and 1B, the bottom of the trench element isolation at the boundary BS is convex upward. As shown in FIG. 7A, when the trench is buried, the upper surface reflects the shape of the bottom of the trench, and the upper surface of the buried oxide film is convex upward in the center of the boundary BS. The wide element isolation region is easily dished during the CMP process. However, the fact that the embedding shape is convex upward cancels out this, so that CMP processing can be performed flatly as shown in FIG. 7B. As described above, since there is no trench embedding defect or CMP dishing in the conventional element isolation region shown in FIG. 62, the process margin is increased and the yield is improved.
[0085]
In FIGS. 1A and 1B, the case where the trench depths are different on the left and right is taken as an example. Obtainable. Also, there is an effect that the leakage current flowing through the bottom of the STI is reduced. This is because the side of the bottom portion of the STI becomes longer due to the level difference of the convex portion, making it difficult to form a leak path.
[0086]
In the configuration shown in FIG. 2A, the gate electrode before processing is stacked thicker than the gate electrode in the transistor region at the boundary portion BS, as shown in FIG. Here, when the gate electrode of the boundary BS is to be completely removed, the amount to be etched is larger in the boundary BS than in the transistor region. In such a state, if the gate electrode at the boundary BS is to be completely removed, the etching amount is too large in the transistor region, and the semiconductor substrate itself is etched. It is difficult to secure a processing margin for preventing this over-etching. However, in the present embodiment shown in FIG. 2A, since the gate electrode of the boundary BS is also etched by the same amount as the gate electrode of the transistor region, the etching amount can be determined only by the transistor region. A sufficient processing margin can be secured.
[0087]
In the embodiment shown in FIG. 1B and FIG. 2B, as shown in FIG. 9 and FIG. 10A, the boundary portion BS is covered with a photoresist during gate processing, so that the boundary portion is covered. The BS gate electrode is not etched. In particular, in the boundary portion BS shown in FIGS. 2B and 10B, since the structure of the gate electrode is different from that of the transistor region, it is difficult to perform etching at the same time as the transistor region. In the present embodiment shown in FIGS. 1B and 2B, the etching amount can be determined only by the transistor region, so that a sufficient processing margin can be secured.
[0088]
In the method of leaving a part of the gate electrode of the boundary BS as shown in FIG. 2A, it is not necessary to cover the boundary BS with a resist when the gate electrode is etched. For this reason, it is not necessary to take an alignment margin or the like, and the area for the gate electrode of the boundary portion BS can be reduced. On the other hand, in the method of leaving all the gate electrodes at the boundary BS as shown in FIG. 2B, the pattern of the gate electrodes at the boundary BS is large. For this reason, there is no possibility that the gate electrode is peeled off to become dust, and the yield can be increased.
[0089]
(Second Embodiment)
FIG. 14A is a cross-sectional view showing the vicinity of the boundary portion of the semiconductor device according to the second embodiment. FIGS. 14B, 15A, and 15B are cross-sectional views showing the vicinity of the boundary portion of the semiconductor device according to the modification of the second embodiment. What is characteristic of this embodiment is that two types of transistors (for example, first and second transistor regions TR1 and TR2) having different gate insulating film types, for example, film material and film thickness, are the same semiconductor substrate. The boundary BS between the two is different from both of them in terms of the shape of the element isolation region or the electrode structure (the shape of the element isolation portion or the electrode structure in the first and second transistor regions TR1 and TR2). Is to include things. Specifically, in the boundary portion BS, a trench type element isolation region having a different depth depending on the portion is disposed.
[0090]
The semiconductor memory device shown in FIG. 14A has first and second transistor regions TR1 and TR2 disposed on the semiconductor substrate 1, and a boundary BS sandwiched between and in contact with the first and second transistor regions TR1 and TR2. . When the first transistor region TR1 is a high breakdown voltage transistor region, the gate insulating film 2 formed on the semiconductor substrate 1 is formed of a silicon oxide film having a thickness of about 10 nm to 40 nm. When the second transistor region TR2 is a low voltage transistor region, the gate insulating film 3 formed on the semiconductor substrate 1 is formed of a silicon oxide film having a thickness of about 1 nm to 10 nm. When the second transistor region TR2 is a memory cell region, the gate insulating film 3 is formed of a silicon oxide film having a thickness of about 1 nm to 10 nm or an ONO film having a thickness of about 10 nm to 50 nm.
[0091]
In the device shown in FIG. 14A, at least two of the above-described three types of transistor regions are arranged adjacent to each other with different types of gate insulating films or different gate insulating film thicknesses. The semiconductor substrate 1 may have a well of the opposite conductivity type to the semiconductor substrate formed in the vicinity of the surface thereof. Further, another well having the same conductivity type as that of the semiconductor substrate may be formed on the opposite conductivity type well (the same applies hereinafter).
[0092]
In the first transistor region TR1, the lower electrode layer 4 is formed on the gate insulating film 2, the upper electrode layer 5 is formed thereon, and the first gate electrode 6 is formed. A pair of source / drain diffusion layers 7 implanted using the first gate electrode 6 as a mask are formed in the semiconductor substrate 1. The first gate electrode 6 and the source / drain diffusion layer 7 form the first transistor 8. A polysilicon layer or the like is used for each of the lower electrode layer 4 and the upper electrode layer 5.
[0093]
A trench type element isolation region 50 is disposed at the boundary BS shown in FIG. A step having a convex portion 51 that protrudes downward is formed at the bottom of the trench in the element isolation region 50, and the trench is partially different in depth. The width of the convex portion 51 in the direction connecting the first and second transistor regions TR1 and TR2 is about 100 nm to 10000 nm, preferably about 100 nm to 1000 nm. The height (depth) of the convex portion 51 from the shallow portion of the bottom of the trench is about 10 nm to 300 nm, preferably about 30 nm to 100 nm. This height changes depending on the film thickness of the gate electrode material in the adjacent first and second transistor regions TR1 and TR2. The width of the portion 51 that protrudes below the bottom of the element isolation region 9 is given in consideration of lithography misalignment in the manufacturing process, and is, for example, about 100 nm to 10000 nm.
[0094]
In the second transistor region TR2 adjacent to the boundary part BS, the lower electrode layer 11 is formed on the gate insulating film 3, the upper electrode layer 12 is formed thereon, and the second gate electrode 13 is formed. A pair of source / drain diffusion layers 14 implanted with the second gate electrode 13 as a mask is formed in the semiconductor substrate 1. The second gate electrode 13 and the source / drain diffusion layer 14 form the second transistor 15. A polysilicon layer or the like is used for each of the lower electrode layer 11 and the upper electrode layer 12.
[0095]
In the case of the structure shown in FIG. 14A, the element isolation region 50 has a greater depth at the center of the boundary portion BS than the portion of the boundary portion BS close to the left and right transistor regions. For this reason, the element isolation breakdown voltage is improved. The depth of the bottom of the element isolation region is deeper as the gate insulating film in the adjacent transistor region is thicker, and the depth is deeper as the gate insulating film is thinner. In addition, there is a step at the bottom of the trench of the element isolation region 50, and the depth of the bottom of the element isolation region is about 5 nm to 50 nm between the first transistor region TR1 side portion and the second transistor region TR2 side portion. Preferably, the difference is about 10 nm to 30 nm. This is because the first gate insulating film 2 is thicker than the second gate insulating film 3 by about 5 nm to 50 nm, desirably about 10 nm to 30 nm. Further, another element isolation region can be provided between the left and right transistors 8 and 15 and the element isolation region 50.
[0096]
In the semiconductor memory device shown in FIG. 14B, the configuration of the first and second transistor regions TR1 and TR2 is the same as that in FIG. 14A, and the configuration at the boundary BS is shown in FIG. Different from the configuration. Around the element isolation region 50, the lower electrode layer 4 is formed on the first gate insulating film 2, and the lower electrode layer 11 is formed on the second gate insulating film 3. Further, the upper electrode layer 16 is formed on the element isolation region 50 and the lower electrode layers 4 and 11 around the element isolation region 50, and the gate structure 17 is formed.
[0097]
In this configuration, the gate structure 17 is preferably electrically insulated from the gate electrodes 6 and 13 of the first and second transistor regions TR1 and TR2. Further, another element isolation region can be provided between the left and right transistors 8 and 15 and the element isolation region 50.
[0098]
14A and 14B is characterized in that there is a step at the bottom of the trench of the element isolation region 50 in the boundary portion BS, and in particular, there is a convex portion 51 that is convex downward. is there. Further, the depth of the trench in the element isolation region 50 is different between the portion on the first transistor region TR1 side and the portion on the second transistor region TR2 side. The depth of the bottom of the element isolation region is deeper as the gate insulating film in the adjacent transistor region is thicker, and the depth is deeper as the gate insulating film is thinner.
[0099]
Since the element isolation depth is deep at the center of the element isolation region 50, a good element isolation withstand voltage can be obtained even if the width of the element isolation region is reduced to achieve high integration. That is, the trench width can be narrowed and the element can be miniaturized as compared with the case where the trench depth is constant in the conventional transistor region and the boundary BS.
[0100]
Furthermore, since the gate structure 17 on the element isolation region 50 shown in FIG. 14B is the same as the gate structure of the first and second transistor regions TR1 and TR2, processing is easy.
[0101]
In the semiconductor memory device shown in FIG. 15A, the configurations of the first and second transistor regions TR1 and TR2 are the same as those in FIGS. 14A and 14B, and the configuration at the boundary BS is shown in FIG. It differs from the configuration shown in a) and (b). In the boundary BS, a recess 52 dug in the semiconductor substrate 1 is disposed.
[0102]
The element isolation region is formed between the first and second transistor regions TR1 and TR2 and the boundary portion BS when necessary for well isolation or the like.
[0103]
In this shape, since the element isolation region having a special shape as shown in FIGS. 14A and 14B is not created in the boundary portion BS, the processing is easy.
[0104]
In the semiconductor memory device shown in FIG. 15B, the configuration of the first and second transistor regions TR1 and TR2 is the same as that in FIGS. 14A and 14B, and the configuration at the boundary BS is shown in FIG. It differs from the configuration shown in a) and (b). Similar to the structure of FIG. 15A, no element isolation region is formed in the boundary portion BS. An electrode layer 53 is formed directly on the semiconductor substrate 1 at the boundary BS. The electrode layer 53 has the same composition as the upper electrode layers 5 and 12 and the height thereof is the same as that of the upper electrode layers 5 and 12.
[0105]
Further, first and second conductive side walls 54 and 55 are formed on the side surfaces of the electrode layer 53 on the first and second transistor regions TR1 and TR2 side. The first conductive sidewall 54 has the same composition as that of the lower electrode layer 4 and is disposed between the protrusion of the electrode layer 53 and the first gate insulating film 2. The second conductive side wall 55 has the same composition as the lower electrode layer 11 and is disposed between the protrusion of the electrode layer 53 and the second gate insulating film 3. Because of this structure, the height of the gate structure at the boundary BS is equal to the height of the transistors formed in the first and second transistor regions TR1 and TR2.
[0106]
The element isolation region is formed between the first and second transistor regions TR1 and TR2 and the boundary portion BS when necessary for well isolation or the like.
[0107]
The semiconductor memory device shown in FIG. 15B is characterized in that there is a portion where the electrode layer 53 is in direct contact with the semiconductor substrate in the boundary portion BS. In the boundary BS, both the first and second gate insulating films 2 and 3 exist on both sides of the electrode layer 53. With these structures, a plurality of transistors can be formed on the same semiconductor substrate with a small number of steps.
[0108]
In the structure shown in FIG. 15B, the semiconductor substrate is not etched at the boundary BS, and the electrode layer at the boundary BS is not removed. For this reason, since the thickness of the conductor to be etched is the same as the thickness of the gate electrode of the transistor, there is no reduction in yield due to the processing of the boundary portion BS.
[0109]
In the manufacturing process in this embodiment, since there is no step of directly applying a photoresist on the gate insulating film, the reliability of the gate insulating film can be improved. In particular, in the case of the structure shown in FIG. 15B, since the gate electrode is left in the boundary portion BS, the gate electrode having a special structure in the boundary portion BS does not need to be etched, so that the yield is improved.
[0110]
The present embodiment also has the structure shown in FIGS. 3A and 3B as in the first embodiment. Since the gate electrode does not fall on the side surface of the gate insulating film at the element isolation end, a parasitic transistor can be prevented from being formed at the end of the element isolation region, and the performance of the transistor can be improved. In addition, since a self-aligned STI process is employed and there is no process for depositing or removing a dummy insulating film or dummy gate for forming an element isolation region, the number of processes can be reduced.
[0111]
Next, an example of a method for manufacturing a semiconductor device according to the present embodiment will be described. First, a method for manufacturing the structure shown in FIG. 14A will be described with reference to FIGS.
[0112]
As shown in FIG. 16A, a sacrificial oxide film (not shown) is formed on the upper surface of the semiconductor substrate 1. Next, well impurities and channel impurities are implanted as necessary, and then the sacrificial oxide film is removed. Subsequently, a first gate insulating film 2 such as a silicon oxide film or a silicon nitride film and a lower electrode layer 4 such as polycrystalline silicon are formed on the semiconductor substrate 1.
[0113]
Next, as shown in FIG. 16B, the first transistor region TR1 and the portion from here to the middle of the boundary BS are covered with a photoresist layer 56, and the gate electrode layer and the gate insulating film in other regions are removed. . The removal method may be either isotropic etching such as wet etching or anisotropic etching such as RIE.
[0114]
Next, as shown in FIG. 16C, a second gate insulating film 3 such as a silicon oxide film or a silicon nitride film and a lower electrode layer 11 such as polycrystalline silicon are formed on the entire surface of the semiconductor substrate 1. At this time, the first transistor region TR1 has a stacked structure in which the second gate insulating film 3 and the lower electrode layer 11 are formed on the lower electrode layer 4. Here, the lower electrode layer 4 in the first transistor region TR1 and the lower electrode layer 11 in the second transistor region TR2 may use different materials and film thicknesses. However, if these are the same material and the same film thickness, it is easy to simultaneously etch the gate electrode in a later step.
[0115]
Next, as shown in FIG. 17A, the second transistor region TR2 and the portion from here to the middle of the boundary BS are covered with a photoresist layer 57, and the gate electrode layer and the gate insulating film in other regions are removed. . The removal method may be either isotropic etching such as wet etching or anisotropic etching such as RIE. At this time, the end portion of the photoresist layer 57 is separated from the end portion of the lower electrode layer 4 that remains. That is, the lower electrode layers 4 and 11 are both removed at the center of the boundary portion BS where the first and second transistor regions TR1 and TR2 are separately formed so that the surface of the semiconductor substrate 1 is exposed.
[0116]
Next, as shown in FIG. 17B, after removing the photoresist layer 57, a first mask layer 58 and a second mask layer 59 are deposited. For example, a silicon nitride film is used for the first mask layer 56, and a silicon oxide film is used for the second mask layer 59, for example. Next, as shown in FIG. 17C, a photoresist resist layer 60 for forming an element isolation region is deposited on the second mask layer 59 to form an element isolation pattern. The photoresist layer 60 is disposed above the portion where the element isolation region is not formed.
[0117]
Next, as shown in FIG. 18A, the photoresist layer 60 is used to remove the second mask layer 59 and the first mask layer 58 by anisotropic etching so as to be opened in the element isolation pattern. . At this time, since the gate electrode does not exist before the etching at the center of the boundary portion BS, the semiconductor substrate 1 is exposed on the surface after the etching. Next, as shown in FIG. 18B, the lower electrode layers 4 and 11 that are not covered by the first mask layer 58 and the second mask layer 59 are removed by anisotropic etching. At this time, in the center of the boundary BS, the semiconductor substrate 1 is etched, and a recess 44 is formed.
[0118]
Next, as shown in FIG. 18C, the semiconductor substrate 1 is etched to form an element isolation region. The depth of the trench 61 in the semiconductor substrate 1 formed as the element isolation region is, for example, about 50 nm to 300 nm, and preferably about 150 nm to 250 nm. The separately created boundary BS has a downwardly convex shape at the bottom of the trench 61 due to the step shown in FIG. Although the level difference of the convex portion depends on the film thickness of the lower electrode layers 4 and 11 remaining in FIG. 18A and the etching conditions, it is generally about 10 nm to 300 nm, and preferably about 30 nm to 100 nm.
[0119]
Further, the depth of the bottom of the trench 61 is different between the portion on the first transistor region TR1 side and the portion on the second transistor region TR2 side. Here, the depth of the bottom of the trench 61 on the first transistor region TR1 side is formed to be shallower by about 5 nm to 50 nm, preferably about 10 nm to 30 nm than the depth of the bottom of the trench 61 on the second transistor region TR2 side. This is because the first gate insulating film 2 is thicker than the second gate insulating film 3. At this time, the semiconductor substrate 1 in the first and second transistor regions TR1 and TR2 is etched in a self-aligned manner with respect to the first and second lower electrode layers 4 and 11, and the first and second transistor regions TR1 are etched. , Trenches for the element isolation region 26 (see FIGS. 3A and 3B) are simultaneously formed in TR2.
[0120]
Next, as shown in FIG. 19A, the trench 61 in the boundary BS and the trenches in the first and second transistor regions TR1 and TR2 are embedded with an insulator 62 such as a silicon oxide film, and the like. In this way, the insulator 62 is etched back using the first mask layer 58 as a stopper. Next, as shown in FIG. 19B, after removing the first mask layer 58, upper electrode layers 5 and 12 are deposited on the entire surface of the semiconductor substrate 1. The upper electrode layers 5 and 12 are made of polycrystalline silicon, a laminated film of polycrystalline silicon and metal or a compound of silicon and metal, or a single layer film of metal or silicon and a compound of metal. Next, as shown in FIG. 19C, a photoresist layer 63 for processing the gate electrode is deposited to form a gate electrode pattern.
[0121]
Next, as shown in FIG. 14A, the gate electrode is anisotropically etched using the photoresist layer 63 as a mask to form the first gate electrode 6 and the second gate electrode 13. Thereafter, the processing damage is recovered by post-oxidation or the like. Next, diffusion layer impurities are implanted to form source / drain diffusion layers 7 and 14. At this time, the resist layer is not left at the boundary BS, and the gate electrode at the boundary BS is removed. Of course, a mask layer such as a silicon nitride film or a silicon oxide film may be deposited on the gate electrode, and the gate electrode may be processed using the mask layer as a mask.
[0122]
Further, although not shown, an interlayer insulating film, contact plugs, wirings and the like are formed to complete the semiconductor device. Thus, when the element isolation region is formed in the boundary part BS, a step remains as the downward convex part 51 at the bottom of the element isolation trench. In addition, since the element isolation trench is deep in the boundary portion BS, the embedded shape may be projected downward to reflect it. In that case, as shown in FIG. 20, a recess 64 is formed on the upper surface.
[0123]
Next, a method for manufacturing the structure shown in FIG. The process up to the step shown in FIG. 19B is the same as the manufacturing method of the structure shown in FIG. In the above manufacturing process, the method of opening the photoresist layer for gate electrode processing at the boundary BS is shown, but here, the method of leaving the photoresist layer at the boundary BS is used. That is, as shown in FIG. 21, a pattern is used that leaves the photoresist layer 65 at the boundary portion BS. At this time, the opening of the photoresist layer 65 is provided outside the width of the trench 61.
[0124]
Next, as shown in FIG. 14B, the gate electrode is anisotropically etched using the photoresist layer 65 as a mask to form the first gate electrode 6 and the second gate electrode 13. At this time, the lower electrode layer 4 is left on the first gate insulating film 2 and the lower electrode layer 11 is left on the second gate insulating film 3 around the element isolation region 50. Further, the gate structure 17 is formed by leaving the upper electrode layer 16 on the element isolation region 50 and the lower electrode layers 4 and 11 around it. Thereafter, the processing damage is recovered by post-oxidation or the like. Next, diffusion layer impurities are implanted into the semiconductor substrate 1 to form the source / drain diffusion layer 7 in the first transistor region TR1 and the source / drain diffusion layer 14 in the second transistor region TR2. Note that a mask layer such as a silicon nitride film or a silicon oxide film may be deposited on the gate electrode, and the gate electrode may be processed using the mask layer as a mask.
[0125]
In addition, since the element isolation trench is deep in the boundary portion BS, the embedded shape may be projected downward to reflect it. In that case, as shown in FIG. 22, a recess 64 is formed on the upper surface, and the upper electrode layer 16 is formed by filling the recess 64.
[0126]
Next, a method for manufacturing the structure shown in FIG. In the manufacturing method of this structure, the steps up to FIG. 17B are the same as the manufacturing method of the structure shown in FIG.
[0127]
Next, as shown in FIG. 23A, a photoresist layer 67 for forming an element isolation region is covered on the second mask layer 59. After anisotropic etching of the second mask layer 59, as shown in FIG. 23B, the photoresist layer 67 is removed to expose the upper surface of the second mask layer 59. At this time, although not shown, there is a portion where the second mask layer 59 is etched in the first and second transistor regions TR1 and TR2.
[0128]
Next, through the same steps as in FIGS. 18A to 19A, the element isolation region 26 (see FIGS. 3A and 3B) is formed in the first and second transistor regions TR1 and TR2. ). The shape of the boundary portion BS at this time is shown in FIG. At this time, the second mask layer 59 remains on the depression 68 existing on the upper surface of the first mask layer 58.
[0129]
Next, as shown in FIG. 24B, the second mask layer 59 and the first mask layer 58 are removed, and the upper surfaces of the lower electrode layers 4 and 11 and the upper surface of the semiconductor substrate 1 are exposed. The upper electrode layers 5 and 12 are formed on the upper surfaces of these. Next, as shown in FIG. 25A, a gate electrode forming photoresist layer 69 is formed on the upper electrode layers 5 and 12.
[0130]
Next, as shown in FIG. 25B, the first gate electrode 6 and the second gate electrode 13 are formed by etching using the photoresist layer 69 as a mask. Thereafter, the processing damage is recovered by post-oxidation or the like. Next, diffusion layer impurities are implanted into the semiconductor substrate 1 to form the source / drain diffusion layer 7 in the first transistor region TR1 and the source / drain diffusion layer 14 in the second transistor region TR2. In this step, since the boundary BS is not covered with a mask, a diffusion layer similar to the source / drain diffusion layers of the first and second transistor regions TR1 and TR2 is also formed in the boundary BS. Note that the source / drain diffusion layer may not be formed by covering the boundary BS with a photoresist layer.
[0131]
Thus, when the boundary portion BS is not an element isolation region and the gate electrode is removed, the shape is as shown in FIG. However, the boundary BS is difficult to ensure the etching selectivity because the gate electrode is in direct contact with the semiconductor substrate. When the semiconductor substrate is etched, the boundary BS takes the shape of FIG. Even in this case, since the gate electrode does not remain, there is no problem such as a short circuit of the gate electrode.
[0132]
Next, a method for manufacturing the structure shown in FIG. The steps up to FIG. 24B are the same as the manufacturing method of the structure shown in FIG.
[0133]
Next, as shown in FIG. 26, a photoresist layer 70 for forming the gate electrode of the first and second transistor regions TR1 and TR2 and the gate structure of the boundary BS is formed on the upper electrode layers 5 and 12. Form. Around the boundary BS, a photoresist layer 70 is formed so as to spread outside the recess 68. Next, as shown in FIG. 15B, the gate electrode layer is etched using the photoresist layer 70 as a mask, and the first gate electrode 6, the second gate electrode 13, the electrode layer 53, the first conductive sidewall 54, and the like. A second conductive side wall 55 is formed. In the structure shown in FIG. 15B, an electrode layer that is in direct contact with the semiconductor substrate at the boundary BS remains.
[0134]
It is difficult to process the gate electrode because the specially formed boundary BS has a special shape. However, in this method, since it is not necessary to process the gate electrode of the boundary BS, the processing becomes easier and the yield is improved as compared with other methods. When the gate electrode is in direct contact with the semiconductor substrate at the boundary BS, it is particularly difficult to process, so that it is very effective if this portion is not processed.
[0135]
62 (a) and 62 (b), which are conventional problems, are caused by the fact that the trench width is wide at the boundary BS, as shown in FIGS. Therefore, by making the bottom of the trench project downward as in the present embodiment and making the trench width narrower than in the prior art, it is possible to prevent filling defects and dishing without impairing the element isolation breakdown voltage. Note that the aspect ratio (aspect ratio) of the trench at the boundary BS at this time increases, but if the aspect ratio of the trench in the memory cell region is made smaller than that, the burying characteristics are reduced due to the increased aspect ratio. Can be prevented.
[0136]
As shown in FIG. 15A, in the method of digging a semiconductor substrate without leaving any gate electrode at the boundary BS, no dust is generated because the gate electrode does not remain at the boundary BS. Further, since the boundary portion BS is not covered with the resist, the area of the boundary portion BS can be reduced.
[0137]
In the manufacturing method shown in FIG. 25A, the gate electrode before processing is not thicker than the transistor region. Therefore, the etching amount can be adjusted to the required amount in the transistor region. Further, since the semiconductor substrate is etched only at the boundary portion BS, damage due to etching does not cause a problem.
[0138]
Further, at the boundary BS shown in FIG. 15B, the electrode layers 53, 54, and 55 (conductive portions of the gate structure) are left and the electrode layers are electrically connected to the semiconductor substrate (well). In the method, the gate electrode can be processed only in the transistor region. In particular, by electrically connecting the electrode layer (conductive portion of the gate structure) to the well, the resistance of the well is lowered, and the step-up / step-down of the well is increased, so that the device performance is improved. Further, since a potential can be applied to the well or the semiconductor substrate through the electrode layer, it is not necessary to provide a well contact or a substrate contact separately.
[0139]
(Third embodiment)
27A and 27B are cross-sectional views of the semiconductor device in this embodiment. A characteristic feature of this embodiment is that three types of transistors (for example, first to third transistor regions TR1, TR2, and TR3) having different gate insulating film types or film thicknesses exist on the same semiconductor substrate. In the boundary BS between two adjacent transistor regions, the shape of the element isolation region or the electrode structure is different from those of the two adjacent transistor regions.
[0140]
In the structure shown in FIG. 27A, the first and second transistor regions TR1 and TR2 are the same as the structure shown in FIG. Further, between the second and third transistor regions TR2 and TR3, there is disposed an element isolation region 72 having a convex portion 71 on the bottom. A third gate insulating film 73 is formed on the semiconductor substrate 1 in the third transistor region TR3. The composition or film thickness of the third gate insulating film 73 is different from that of the first gate insulating film 2 and the second gate insulating film 3. A third gate electrode 76 in which a lower electrode layer 74 and an upper electrode layer 75 are stacked is formed on the third gate insulating film 73.
[0141]
Using the third gate electrode 76 as a mask, a source / drain diffusion layer 77 is formed in the semiconductor substrate 1, and a third transistor 78 is formed.
[0142]
The example shown in FIG. 27A is characterized in that there is a step at the bottom of the trench of the element isolation regions 9 and 27 in the boundary portion BS, and in particular, there are convex portions 10 and 71 that are convex upward. . Further, the depth of the element isolation region 9 is different between the portion on the first transistor region TR1 side and the portion on the second transistor region TR2 side. The depth of the element isolation region 72 is also different between the portion on the second transistor region TR2 side and the portion on the third transistor region TR3 side. Here, since the gate insulating film 3 in the second transistor region TR2 is thinner than the gate insulating film 73 in the third transistor region TR3, the bottom of the element isolation region 72 is the thickness of the third transistor region TR3. The element isolation region is formed with a shallow depth at the bottom.
[0143]
In the example shown in FIG. 27B, the structure of the boundary BS between the first and second transistor regions TR1 and TR2 is the same as the structure of the boundary BS between the second and third transistor regions TR2 and TR3. It is characterized by being different. There is no protrusion at the bottom of the element isolation region 80 at the boundary BS between the second and third transistor regions TR2 and TR3, and there is only a step difference in depth depending on the contact region. Since the third gate insulating film 81 is formed thicker than the second gate insulating film 3, the depth is formed deeper on the second transistor region TR 2 side of the element isolation region 80.
[0144]
In the third transistor region TR3, a third gate insulating film 81 is formed on the semiconductor substrate 1, and a third gate electrode 84 composed of a lower electrode layer 82 and an upper electrode layer 83 is formed on the third gate insulating film 81. It is formed. A source / drain diffusion layer 85 formed in the semiconductor substrate 1 is provided using the third gate electrode 84 as a mask, and a third transistor 86 is provided.
[0145]
By adopting these structures, it becomes a self-aligned STI process that does not require the deposition and removal process of the dummy insulating film and dummy gate for forming the STI, and a plurality of transistors can be formed on the same semiconductor substrate with a small number of processes. It becomes. Further, in the manufacturing process in the structure of FIG. 27A, since there is no step of directly applying a photoresist on the gate insulating film, the reliability of the gate insulating film can be improved.
[0146]
In the manufacturing process in the structure of FIG. 27B, since the process of removing the gate electrode that has been prepared is reduced, the manufacturing process can be simplified and the cost can be reduced.
[0147]
FIG. 28A is a cross-sectional view illustrating the structure of the gate electrode of the first transistor region TR1. FIG. 28B is a cross-sectional view illustrating the structure of the gate electrode of the second transistor region TR2. FIG. 28C is a cross-sectional view illustrating the structure of the gate electrode of the third transistor region TR3. As shown in FIGS. 28A to 28C, the gate electrode of the transistor in this embodiment is formed in a self-aligned manner with respect to the element isolation region. For this reason, the gate electrode does not fall on the side surface of the gate insulating film at the element isolation end. Therefore, it is possible to prevent the formation of a parasitic transistor at the element isolation end and improve the performance of the transistor.
[0148]
27 (a) and 27 (b) are formed by a method in which the gate electrodes overlap each other at the boundary BS to form an element isolation trench and remove the gate electrode. The However, as described in the first and second embodiments, the presence / absence of overlap at the boundary BS, the presence / absence of element isolation trenches, and the presence / absence of gate electrode removal can be arbitrarily combined. . Further, the structure of the boundary of each creation may be unified into the same structure, or may be a separate structure.
[0149]
An example of a method for manufacturing the semiconductor device having the structure shown in FIG. 27A in this embodiment will be described below. 29A to 30A are the same as the steps shown in FIGS. 4A to 5A.
[0150]
Next, as shown in FIG. 30B, etching is performed using the photoresist layer 91 that exposes the third transistor region TR3 and its boundary portion BS. Next, as shown in FIG. 30C, after the photoresist layer 91 is removed, a third gate insulating film 73 is deposited on the entire surface, and a lower electrode layer 74 is formed thereon. Next, as shown in FIG. 31A, a photoresist layer 92 is provided in the third transistor region TR3 and its boundary BS, and etching is performed. As a result, the lower electrode layer 4 is exposed in the first transistor region TR1, and the lower electrode layer 11 is exposed from the boundary portion BS to the second transistor region TR2.
[0151]
Next, as shown in FIG. 31B, the photoresist layer 92 is removed, and a first mask layer 93 and a second mask layer 94 are sequentially formed on the exposed surface. The first mask layer 93 is, for example, a silicon nitride film, and the second mask layer 94 is, for example, a silicon oxide film. Thereafter, the element isolation region and the gate electrode are processed by the same method as the steps from FIG. 5C to FIG. 8 shown as the manufacturing method of the first embodiment. Further, although not shown, an interlayer insulating film, contact plugs, wirings and the like are formed to complete the semiconductor device.
[0152]
In the method of this embodiment, since there is no step in which the photoresist directly contacts the gate insulating film, high reliability of the gate insulating film can be ensured. Further, the structure of the boundary portion BS that is separately created is not limited to the structure shown in FIG. 27A, and other structures shown in the first embodiment and the second embodiment may be used. Different types of structures may be combined. Furthermore, by using the method of this embodiment mode, four or more types of gate insulating films and gate electrodes can be formed separately.
[0153]
Next, an example of a manufacturing method of the structure shown in FIG.
[0154]
First, a sacrificial oxide film is formed on the surface of the semiconductor substrate. After implanting well impurities and channel impurities as necessary, the sacrificial oxide film is removed. Next, as shown in FIG. 32A, a first gate insulating film 2 such as a silicon oxide film or a silicon nitride film and a lower electrode layer 4 such as polycrystalline silicon are formed on the semiconductor substrate 1.
[0155]
Next, as shown in FIG. 32B, the portion to be the first transistor region TR1 is covered with a photoresist layer 95, and the gate electrode and the gate insulating film in other regions are removed. The removal method may be either isotropic etching such as wet etching or anisotropic etching such as RIE.
[0156]
Next, as shown in FIG. 32C, an oxide film 96 such as a silicon oxide film or a silicon nitride film is formed on the entire surface of the semiconductor substrate 1. Next, as shown in FIG. 32D, the third transistor region TR3 is covered with a photoresist layer 97, and the oxide film 96 in other regions is removed.
[0157]
Next, as shown in FIG. 33A, the second gate insulating film 3 and the lower electrode layers 11 and 82 are formed on the exposed surface. The second gate insulating film 3 is formed on the oxide film 96, and the film thickness is increased to form the third gate insulating film 81 in the third transistor region TR3. Different materials and film thicknesses may be used for the lower electrode layer 11 and the lower electrode layer 82. However, if these are the same material and the same film thickness, it is easy to simultaneously etch the gate electrode in a later step.
[0158]
Next, as shown in FIG. 33 (b), the portions to be the second and third transistor regions TR2 and TR3 are covered with a photoresist layer 98, and the lower electrode layers 11 and 82 and the second gate are formed in other regions. The insulating film 3 is removed. The removal method may be either isotropic etching such as wet etching or anisotropic etching such as RIE. At this time, a part of the photoresist covers the boundary portion BS on the first transistor region TR1 side. Therefore, the gate electrode remains in the laminated structure at the boundary portion BS where the first and second transistor regions TR1 and TR2 are separately formed.
[0159]
Next, as shown in FIG. 33C, a first mask layer 99 and a second mask layer 100 are deposited. The first mask layer 99 is, for example, a silicon nitride film, and the second mask layer 100 is, for example, a silicon oxide film. Thereafter, an element isolation trench and an element isolation region are formed by the same processes as those shown in FIGS. 6A to 7C.
[0160]
Next, the structure shown in FIGS. 34A and 34B is formed by a process similar to the process of FIGS. Next, using the photoresist layer 101 as a gate electrode formation mask, the gate electrode is processed in the same manner as described with reference to FIG. Since the lower electrode layers 11 and 82 are used in common at the boundary BS between the second and third transistor regions TR2 and TR3, there is no difference in the film thickness at the boundary BS. For this reason, a difference in thickness between the second gate insulating film and the third gate insulating film is generated at the bottom of the element isolation region 80. That is, the depth of the element isolation region 80 at the boundary BS on the side adjacent to the thick third transistor is shallower than the depth of the element isolation region 80 on the side adjacent to the second transistor. Further, although not shown, an interlayer insulating film, contact plugs, wirings and the like are formed to complete the semiconductor device.
[0161]
In contrast to the method of manufacturing the semiconductor device shown in FIG. 27A, in the method of manufacturing the semiconductor device shown in FIG. 27B, the lower electrode layer 11 and the third transistor region of the second transistor region TR2 are used. The lower electrode layer 82 of TR3 is deposited in common. For this reason, a removal process is abbreviate | omitted and a process can be simplified.
[0162]
The structure of the separate boundary portion BS is not limited to the structure shown in FIGS. 27A and 27B, and other structures shown in the first embodiment and the second embodiment may be used. A plurality of structures may be combined. Furthermore, by using this embodiment mode, four or more types of gate insulating films and gate electrodes can be formed separately. Further, since the photoresist is directly applied only on the gate insulating film of the high breakdown voltage transistor, the number of separate steps can be reduced without impairing the reliability of the memory cell.
[0163]
(Fourth embodiment)
The semiconductor device in this embodiment is applied to any of a NAND-type EEPROM, a NOR-type EEPROM, an AND-type EEPROM, or a Virtual Ground Array-type EEPROM having a MONOS-type cell structure which is one of nonvolatile storage devices. Cross-sectional views in the vicinity of the boundary portion BS according to the present embodiment are shown in FIGS.
[0164]
FIG. 38 shows an equivalent circuit diagram of a NAND memory cell block in which a plurality of memory cells are arranged in series between selection transistors. That is, the non-volatile memory cells M0 to M15 are connected in series, one end of the memory cell M0 is connected to the data transfer line BL via the selection transistor S1, and one end of the memory cell M15 is commonly connected via the selection transistor S2. Connected to source line SL.
[0165]
Control electrodes of the respective memory cells M0 to M15 are connected to data transfer lines WL0 to WL15. Further, in order to select one memory cell block from a plurality of memory cell blocks along the data transfer line and connect it to the data transfer line, the control electrode of the selection transistor S1 is connected to the block selection line SSL. Further, the control electrode of the selection transistor S2 is connected to the block selection line GSL, and a NAND memory cell block A is formed in a region indicated by a dotted line.
[0166]
Here, a state in which 16 memory cells are connected in the memory cell block A is shown. However, the number of memory cells connected to the data transfer line and the data selection line only needs to be plural.ⁿThe number (n is a positive integer) is desirable for address decoding. Further, it is not always necessary to use the same structure as the memory cell transistor as the selection transistor, and normal MOS transistors can be used as the selection transistors S1 and S2 as shown in FIG.
[0167]
The MONOS type nonvolatile memory includes a MONOS type transistor constituting a memory cell, a MOS transistor having a relatively thin gate oxide film constituting a peripheral low voltage circuit (hereinafter referred to as an LV transistor), and a comparison constituting a peripheral high voltage circuit. It includes at least three types of transistors, namely MOS transistors (hereinafter referred to as HV transistors) having a thick gate oxide film. The MONOS memory cell and the LV transistor are separately formed by the method according to the first to third embodiments, and the boundary portion BS has, for example, the shape shown in FIG. However, as described in the first to third embodiments, the presence / absence of the overlap at the boundary BS, the presence / absence of the element isolation trench, and the presence / absence of the gate electrode removal can be arbitrarily combined.
[0168]
In the semiconductor device whose cross section is shown in FIG.¹⁴cm^{-3 ~}10¹⁹cm^-3Memory cell region MC, low-voltage (LV) transistor region LV, high-voltage (HV) transistor region HV, and boundary portion BS between them on P-type semiconductor substrate 102 containing boron at an impurity concentration of Is placed. An N-type well 102n and a P-type well 102p are formed in the substrate 102. When the P-type well 102p is formed in the N-type well 102n, a voltage can be applied to the P-type well 102p independently of the P-type semiconductor substrate 102. Thereby, the booster circuit load at the time of erasing can be reduced and the power consumption can be suppressed.
[0169]
In memory cell region MC, charge storage layer 104 is formed via tunnel gate insulating film 103. The tunnel gate insulating film 103 is made of, for example, a silicon oxide film or oxynitride film having a thickness of 1 to 10 nm. The charge storage layer 104 is made of, for example, SiN or SiON having a thickness of 3 nm to 50 nm. On this, for example, a block insulating film 105 made of a silicon oxide film having a thickness of 2 nm to 10 nm is formed.
[0170]
On the block insulating film 105, a control gate 106 is formed with a thickness of 10 nm to 500 nm, and a memory cell gate 107 and a selection gate 108 are configured. The control gate 106 is, for example, a stack structure of polysilicon or WSi (tungsten silicide) and polysilicon, a stack structure of NiSi, MoSi, TiSi, CoSi and polysilicon, a stack structure of metal and polysilicon, or a silicon structure. It consists of a single layer structure of a metal compound or metal. Further, a mask insulating film made of a silicon oxide film or a silicon nitride film having a thickness of about 10 nm to 300 nm is disposed on the control gate 106.
[0171]
In the LV transistor region LV, an LV gate insulating film 113 is formed on the substrate 102, and an LV gate 109 is formed thereon. In the HV transistor region HV, an HV gate insulating film 110 is formed on the substrate 102, and an HV gate 111 is formed thereon.
[0172]
Side wall insulating films 119 made of, for example, a silicon nitride film or a silicon oxide film having a thickness of 5 nm to 200 nm are formed on both sides of the gate electrode in each of the regions MC, LV, and HV. A source / drain diffusion layer 112 that is an N-type diffusion layer is formed on the surface of the substrate 102. These source / drain diffusion layers 112 and the memory cell gate 107 form a MONOS type nonvolatile EEPROM cell. The gate length of the charge storage layer is, for example, 0.5 μm or less and 0.01 μm or more.
[0173]
These source / drain diffusion layers 112 are made of, for example, phosphorus, arsenic, or antimony with a surface concentration of 10¹⁷cm^-3To 10^{twenty one}cm^-3For example, it is formed with a depth of 10 nm to 500 nm. Further, these source / drain diffusion layers 112 are connected in series between the memory cells to realize NAND connection. The source / drain diffusion layer 112 on one end side of the selection gate 108 is connected to the data transfer line 116 via the contact plug 115.
[0174]
The selection gate 108 is formed in the same layer as the control gate 106 of the memory cell gate 107. The contact plug 115 is filled with, for example, N-type or P-type doped polysilicon or tungsten, tungsten silicide, Al, TiN, Ti, or the like to form a conductor region. The data transfer line 116 is made of tungsten, tungsten silicide, titanium, titanium nitride, or aluminum.
[0175]
The selection gate 108 is opposed to the substrate 102 through a gate insulating film 117 having the same structure as that of the charge storage layer 104 of the memory cell gate 107 to form a selection transistor. The gate length of the selection gate 108 is longer than the gate length of the memory cell gate, for example, 1 μm or less and 0.02 μm or more. Thereby, a large on / off ratio at the time of block selection and non-selection can be secured, and erroneous writing and erroneous reading can be prevented.
[0176]
Each of these elements is, for example, SiO₂And an interlayer film 118 made of SiN. Further, on the interlayer film 118, for example, SiO₂An insulating film protective layer (not shown) made of Si, SiN, or polyimide, or an upper wiring (not shown) made of W, Al, or Cu, for example, is formed.
[0177]
A first element isolation region 120 having a structure as shown in FIG. 1A is disposed between the memory cell region MC and the LV transistor region. A second element isolation region 121 having a structure as shown in FIG. 27B is disposed between the LV transistor and the HV transistor region HV.
[0178]
A contact plug 122 is connected to the source / drain diffusion layer 112 of the LV transistor region LV. The contact plug 122 is connected to the wiring 123. A contact plug 124 is connected to the source / drain diffusion layer 112 in the HV transistor region HV. The contact plug 124 is connected to the wiring 125.
[0179]
In this embodiment, since the MONOS type EEPROM cell is used, the writing voltage and the erasing voltage can be lowered as compared with the floating gate type EEPROM cell described later. For this reason, in the peripheral circuit transistor, the withstand voltage can be maintained even if the element isolation interval is narrowed and the gate insulating film thickness is reduced.
[0180]
Therefore, the area of the circuit to which the high voltage is applied can be reduced, and the chip area can be further reduced. Furthermore, the thickness of the charge storage layer 104 can be reduced to 20 nm or less as compared with the floating gate type memory cell. For this reason, the aspect ratio at the time of gate formation can be reduced, the processing shape of the gate electrode can be improved, the embedding characteristics between the gates of the interlayer film 118 can be improved, and the breakdown voltage can be improved.
[0181]
Further, the process for forming the floating gate electrode and the slit creation process are unnecessary, and the process steps can be further shortened. In addition, since the charge storage layer 104 is an insulator and charges are trapped in each charge trap, it is difficult for the charges to escape and strong resistance can be provided. Furthermore, even if the sidewall insulating film of the charge storage layer 104 is thinned, good retention characteristics can be maintained without any charges trapped in the charge storage layer 104 being lost.
[0182]
The selection transistor shown in FIG. 35 has the same MONOS structure as the memory cell transistor. In this case, the manufacturing cost can be reduced because the process for making the selection transistor and the memory cell transistor can be omitted. In addition, since it is not necessary to make a margin for making a difference, the distance between the selection transistor and the memory cell can be reduced, and the element area can be reduced.
[0183]
In the structure shown in FIG. 35, there is no gate insulating film on the substrate 102 where the gate is not formed.
[0184]
FIG. 36 shows a modification of the structure shown in FIG. Here, the first element isolation region 120 in FIG. 35 is not provided, and instead, the gate structure 130 is formed at the boundary BS between the memory cell region MC and the LV transistor region LV. In the gate structure 130, on the substrate 102, the gate insulating film 117 of the selection gate 108 is provided on the memory cell region MC side, and the LV gate insulating film 113 is provided on the side far from the memory cell region MC. A gate electrode material is disposed between the gate insulating film 117 and the LV gate insulating film 113 so as to be in direct contact with the substrate 102. An insulating film 119 is disposed on the side wall of the gate structure. The gate structure 130 is formed by the same method as the electrode layer 53 in the boundary portion BS shown in FIG. 15B by changing the composition of the insulating film and the conductor.
[0185]
FIG. 37 shows another modification of the structure shown in FIG. Here, in the structure shown in FIG. 35, when the gate electrode on the memory cell region MC side is processed, the gate insulating film is left without being processed at the same time. That is, the tunnel gate insulating film 103 and the charge storage layer 104 are formed on the surface of the semiconductor substrate in the memory cell region MC and the boundary portion BS adjacent thereto.
[0186]
As the structure of the boundary BS between the memory cell region MC and the LV transistor region LV in FIG. 37, the structures shown in FIGS. Moreover, these structures can be applied to the boundary BS between the memory cell region MC and the HV transistor region HV by exchanging the LV gate insulator and the HV gate insulator. That is, FIG. 40A to FIG. 40H are applicable to the boundary portion BS of the NAND MONOS semiconductor memory device.
[0187]
Note that if each substrate has a structure in which the substrate 102 is exposed without providing a gate insulating film at each boundary BS, the present invention can be applied to the boundary BS of the semiconductor device shown in FIGS. Moreover, it is good also as a structure which does not form the diffusion layer 112 in each boundary part BS. Furthermore, the structure of the boundary of each creation may be unified into the same structure, or may be different structures depending on places.
[0188]
In the boundary portion BS shown in FIG. 40A, an element isolation region 132 similar to the structure shown in FIG. The tunnel gate insulating film 103 and the charge storage layer 104 are formed on the element isolation region 132 on the memory cell region MC side. Source / drain diffusion layers 112 are formed in the substrate 102 on both sides of the element isolation region 132. A step having a convex portion that is convex upward is formed at the bottom of the trench in the element isolation region 132. By adopting such a boundary BS structure, STI embedding can be improved, dishing can be prevented, and the area can be reduced.
[0189]
In the boundary portion BS shown in FIG. 40B, the same gate structure as the selection gate 108 is formed so as to cover the element isolation region 132 in the structure shown in FIG. By adopting such a boundary BS structure, STI embedding can be improved, dishing can be prevented, and gate processing can be facilitated.
[0190]
In the boundary portion BS shown in FIG. 40C, an element isolation region 133 similar to the structure shown in FIG. 14A is replaced with the element isolation region 132 in FIG. By adopting such a structure of the boundary portion BS, the breakdown voltage of the STI can be improved and the area can be reduced.
[0191]
In the boundary portion BS shown in FIG. 40 (d), the element isolation region 132 is replaced with the element isolation region 133 shown in FIG. 40 (c) in the structure shown in FIG. 40 (b). By adopting such a structure of the boundary portion BS, the breakdown voltage of STI can be improved and gate processing can be facilitated.
[0192]
In the boundary portion BS shown in FIG. 40 (e), a structure similar to the structure shown in FIG. 2 (a) is formed. On the substrate 102 in the center of the boundary BS, a gate structure 134 is formed which is formed from the constituent material of the gate structure of the memory cell region MC and the LV transistor region LV. In the gate structure 134, an ONO film 131 is formed on the memory cell region MC side on the substrate 102, and an LV gate insulating film 113 is formed on the LV transistor region LV side. On the ONO film 131 and the insulating film 113, the electrode layer 20, the sidewall insulating film 119, and the like are formed. A tunnel gate insulating film 103 and a charge storage layer 104 are formed on the substrate 102 on the memory cell region MC side from the gate structure 134. Source / drain diffusion layers 112 are formed in the substrate 102 on both sides of the gate structure 134. By adopting such a structure of the boundary portion BS, gate processing can be facilitated and defects due to STI can be avoided.
[0193]
The boundary portion BS shown in FIG. 40 (f) has the same structure of the boundary portion BS as the structure shown in FIG. 2 (b). On the substrate 102 in the center of the boundary BS, a gate structure 135 is formed which is made of a material constituting the gate structure of the memory cell region MC and the LV transistor region LV. In the gate structure 135, an ONO film 131 is disposed on the substrate 102 on the memory cell region MC side, and an LV gate insulating film 113 is disposed on the LV transistor region LV side. A stacked gate structure similar to the control gate 108 is provided on the ONO film 131, and a lower layer structure of the LV gate 109 is provided on the LV gate insulating film 113. An insulating film 119 is formed on the side surface of the gate structure 135. By adopting such a structure of the boundary portion BS, dust can be reduced and defects due to STI can be avoided.
[0194]
The boundary portion BS shown in FIG. 40 (g) has the structure of the boundary portion BS similar to the structure shown in FIG. 15 (a). A recess 136 is formed in the surface of the substrate 102 at the center of the boundary BS. A tunnel gate insulating film 103 and a charge storage layer 104 are formed on the substrate 102 on the memory cell region MC side from the recess 136. By adopting such a structure of the boundary portion BS, dust can be reduced and defects due to STI can be avoided.
[0195]
In the boundary BS shown in FIG. 40 (h), a structure similar to the gate structure 130 shown in FIG. 15 (b) is shown. Here, a recess is formed on the surface of the semiconductor substrate 102 at the center of the boundary, but it may be flat as in FIG. In this gate structure, the electrode layer is in direct contact with the surface of the substrate 102 without using an insulating film. By adopting such a boundary BS structure, gate processing is easy, dust can be reduced, defects due to STI can be avoided, and the aspect ratio can be matched.
[0196]
FIG. 41A shows a cross section in the direction perpendicular to the data transfer line on the gate of the memory cell. FIG. 41B shows a cross section in the direction perpendicular to the data transfer line on the gates of the peripheral transistors.
[0197]
As shown in FIGS. 41A and 41B, the element isolation region 300 covers the side surfaces of the substrate 102 and the gate insulating film. Therefore, the etching before forming the tunnel gate insulating film 103 does not expose the end portion of the element isolation region, and the gate electrode 106 is below the surface of the substrate 102. Can prevent. This is because this structure is formed by the self-aligned STI method. In this manner, electric field concentration at the boundary between the element isolation region 300 and the tunnel gate insulating film 103 and a parasitic transistor with a lowered threshold value are unlikely to occur. Further, since a sidewalk phenomenon, which is a phenomenon of lowering the write threshold due to bird's beak, is less likely to occur, a more reliable transistor can be formed.
[0198]
FIG. 42 shows an equivalent circuit diagram of a NOR type MONOS type memory cell. Sources and drains of the respective memory cells M01, M02, M11, M12, M21, and M22 are connected between the data transfer lines BL1 and BL2 and the source line SL. Data selection lines WL0, WL1, and WL2 are connected to the respective gates. The above-described structure of the present embodiment can be appropriately modified and applied to such a NOR type MONOS type memory cell.
[0199]
FIG. 43 shows an equivalent circuit diagram of an AND type MONOS type memory cell block in which a plurality of memory cells are arranged in series between selection transistors. Nonvolatile memory cells M0 to M15 are connected in parallel. One end of each of the memory cells M0 to M15 is connected to the data transfer line BL via the selection transistor S1. The other ends of the memory cells M0 to M15 are connected to the common source line SL via the selection transistor S2.
[0200]
Control electrodes of the respective memory cells M0 to M15 are connected to data transfer lines WL0 to WL15. Further, in order to select one memory cell block from a plurality of memory cell blocks along the data transfer line and connect it to the data transfer line, the control electrode of the selection transistor S1 is connected to the block selection line SSL. Further, the control electrode of the selection transistor S2 is connected to the block selection line GSL, and forms an AND memory cell block B in a region indicated by a dotted line.
[0201]
Here, a state in which 16 memory cells are connected in the memory cell block B is shown. However, the number of memory cells connected to the data transfer line and the data selection line only needs to be plural.ⁿ The number (n is a positive integer) is desirable for address decoding. Further, it is not always necessary to use the same structure as the memory cell transistor as the selection transistor. For example, as shown in FIG. 44, normal MOS transistors can be used as the selection transistors S1 and S2.
[0202]
Also in such an AND type MONOS type memory cell, the above-described structure of the present embodiment can be appropriately changed and applied.
[0203]
Next, an example of a method for manufacturing the nonvolatile semiconductor memory device of the present embodiment shown in FIG. 35 will be described with reference to FIGS. 45 (a) to 48 (c). First, a sacrificial oxide film (not shown) is formed on the surface of the semiconductor substrate 102. After implanting well impurities and channel impurities as necessary, the sacrificial oxide film is removed.
[0204]
Next, as shown in FIG. 45A, a tunnel gate insulating film 103 made of, for example, a silicon oxide film or an oxynitride film having a thickness of 1 to 10 nm is formed on the semiconductor substrate 102. Next, the charge storage layer 104 made of, for example, SiN or SiON is formed and formed with a thickness of 3 nm to 50 nm. Next, for example, a block insulating film 105 made of a silicon oxide film having a thickness of 2 nm to 10 nm is formed. On top of this, for example, a polysilicon layer 137 is deposited with a thickness of 10 nm to 500 nm.
[0205]
Next, as shown in FIG. 45B, a portion that becomes the memory cell region MC is covered with a photoresist layer 138, and the polysilicon layer 137, the block insulating film 105, the charge storage layer 104, and the tunnel in other regions are covered. The gate insulating film 103 is removed. The removal method may be either isotropic etching such as wet etching or anisotropic etching such as RIE. Next, as shown in FIG. 45C, the gate insulating film 110 of the HV transistor made of a silicon oxide film or an oxynitride film having a thickness of, for example, 5 to 50 nm is formed on the entire surface of the semiconductor substrate 102. To do.
[0206]
Next, as shown in FIG. 46A, the HV transistor region HV is covered with a photoresist layer 139, and the gate insulating film 110 of the HV transistor is removed from other regions. Next, as shown in FIG. 46B, the photoresist layer 139 is removed, and an LV made of, for example, a silicon oxide film or an oxynitride film having a thickness of 1 nm to 10 nm is formed on the entire surface of the semiconductor substrate 102. A system gate insulating film 113 is formed, and an HV system gate insulating film 110 is formed to a predetermined thickness. For example, a polysilicon layer 140 is deposited with a thickness of, for example, 10 nm to 500 nm through the HV-based gate insulating film 110.
[0207]
At this time, the memory cell region MC has a laminated structure in which the LV transistor gate insulating film 113 and the polysilicon layer 140 are formed on the polysilicon layer 137 of the memory cell. Here, the gate electrode of the memory cell and the gate electrode of the LV transistor may use different materials and film thicknesses. However, if the same material and the same film thickness are used, it is easy to simultaneously etch the gate electrode.
[0208]
Next, as shown in FIG. 46C, the region (peripheral circuit region) of the LV transistor and the HV transistor is covered with a photoresist layer 141, and the polysilicon layer 140 and the LV gate insulating film in other regions are covered. Remove. The removal method may be either isotropic etching such as wet etching or anisotropic etching such as RIE. At this time, a part of the photoresist layer 141 is applied to the memory cell region MC. Therefore, the gate electrode remains in the stacked structure at the boundary BS where the memory cell region MC and the peripheral circuit region are separately formed.
[0209]
Next, the photoresist layer 141 is removed, and a first mask layer 142 and a second mask layer 143 are deposited as shown in FIG. The first mask layer 142 is, for example, a silicon nitride film, and the second mask layer 143 is, for example, a silicon oxide film. Next, as shown in FIG. 47B, a photoresist layer 144 for forming an element isolation region is deposited to form an element isolation pattern. Here, a method for forming an element isolation region without leaving a resist at the boundary portion BS that is separately formed will be described.
[0210]
Next, as shown in FIG. 47C, after removing the photoresist layer 144, the second mask layer 143, and the first mask layer 142 by anisotropic etching, the polysilicon layer 140 is anisotropically etched. Remove with. Subsequently, the semiconductor substrate 102 is etched to form element isolation trenches 145 and 146 in order to form an element isolation region. The depth of the element isolation trenches 145 and 146 is, for example, about 50 nm to 300 nm.
[0211]
At the boundary BS where the memory cell region MC and the LV transistor region LV are separately formed, the step generated in FIG. 46B remains in FIG. 47B, so that it has a convex shape at the bottom of the element isolation region. . The step of the convex portion depends on the step in FIG. 46B and the etching conditions, but is, for example, about 10 nm to 300 nm, preferably about 30 nm to 100 nm. The depth of the element isolation trench also varies depending on the contact area, which reflects the ONO film thickness of the memory cell region MC, the film thickness difference between the gate insulating film of the LV transistor region LV, and the HV transistor region HV, The thinner the gate insulating film, the deeper the element isolation depth. In the boundary portion BS where the LV transistor region LV and the HV transistor region HV are separately formed, the step generated in FIG. 46B remains in FIG. 47B, so that the depth of the bottom of the element isolation trench 146 is different. .
[0212]
Next, as shown in FIG. 48A, the element isolation trenches 145 and 146 are filled with an insulating film such as a silicon oxide film, and the buried material is etched back using the first mask layer 142 as a stopper by a method such as CMP. . Since the element isolation region in the boundary portion BS has a shallow element isolation depth, the embedding property is good, and the upper part of the element isolation insulating film is almost flat after the etch back. After removing the first mask layer 142, a gate electrode layer 140 is deposited on the entire exposed surface. The gate electrode layer 140 is made of polycrystalline silicon, a laminated film of polycrystalline silicon and metal or a compound of silicon and metal, or a single layer film of metal or a compound of silicon and metal. Further, a mask insulating film 104 made of a silicon oxide film or silicon nitride film having a thickness of about 10 nm to 300 nm is deposited.
[0213]
Next, as shown in FIG. 48B, a photoresist layer 148 for processing the gate electrode is deposited to form a pattern. Next, as shown in FIG. 48C, the gate electrode is anisotropically etched using the photoresist layer 148 as a mask. Thereafter, the processing damage is recovered by post-oxidation or the like. Next, if necessary, a gate sidewall insulating film 119 is formed and a diffusion layer impurity is implanted to form a source / drain diffusion layer 112.
[0214]
At this time, the boundary portion BS does not leave a resist, and the gate electrode of the boundary portion BS is removed. Of course, a mask layer such as a silicon nitride film or a silicon oxide film may be deposited on the gate electrode, and the gate electrode may be processed using the mask layer as a mask. Further, although not shown, an interlayer insulating film, contact plugs, wirings and the like are formed to complete the semiconductor device as shown in FIG.
[0215]
Note that a twin well configuration may be employed in which a first well having a conductivity type opposite to that of the semiconductor substrate is provided on the semiconductor substrate, and a second well having the same conductivity type as that of the semiconductor substrate is provided thereon.
[0216]
In this embodiment, the same effects as those of the first to third embodiments can be obtained. As the transistors forming the peripheral circuit, two types of transistors having a MOS structure and different gate oxide thicknesses are exemplified. However, this embodiment can be applied to the transistors constituting the peripheral circuit even when there are three or more gate oxide film thicknesses.
[0217]
(Fifth embodiment)
The semiconductor device in this embodiment is applied to any of a NAND type EEPROM, a NOR type EEPROM, an AND type EEPROM, or a Virtual Ground Array type EEPROM having a floating gate type cell structure which is one of nonvolatile memory devices. In a floating gate type nonvolatile memory, a memory cell transistor constituting a memory cell, a relatively thin gate oxide MOS transistor (hereinafter referred to as LV transistor) constituting a peripheral low voltage circuit, and a relatively thick gate constituting a peripheral high voltage circuit At least three types of transistors, oxide MOS transistors (hereinafter referred to as HV transistors), are required.
[0218]
Also in the present embodiment, the equivalent circuit of the NAND memory cell shown in FIG. 38 or 39, the equivalent circuit of the NOR memory cell shown in FIG. 42, and the equivalent circuit of the AND memory cell shown in FIG. 43 or FIG. The configuration can be applied as it is.
[0219]
FIG. 49 to FIG. 51 are cross-sectional views of the vicinity of the separately created boundary portion BS according to the present embodiment.
[0220]
Here, the floating gate type memory cell and the LV transistor are separately formed by the method according to the first to third embodiments, and the boundary portion BS has a shape shown in FIG. 49, for example. However, as described in the first to third embodiments, the presence / absence of the overlap at the boundary BS, the presence / absence of the element isolation trench, and the presence / absence of the gate electrode removal can be arbitrarily combined.
[0221]
In the semiconductor device whose cross section is shown in FIG.¹⁴cm^{-3 ~}10¹⁹cm^-3Memory cell region MC, low-voltage (LV) transistor region LV, high-voltage (HV) transistor region HV, and boundary portion BS between them on P-type semiconductor substrate 150 containing boron at an impurity concentration of Is placed. An N-type well 150n and a P-type well 150p are formed in the substrate 150. When the P-type well 150p is formed in the N-type well 150n, a voltage can be applied to the P-type well 150p independently of the P-type semiconductor substrate 150. Thereby, the booster circuit load at the time of erasing can be reduced and the power consumption can be suppressed.
[0222]
In memory cell region MC, charge storage layer 152 is formed through tunnel gate insulating film 151. The tunnel gate insulating film 151 is made of, for example, a silicon oxide film or an oxynitride film having a thickness of 3 nm to 15 nm. The charge storage layer 152 is made of, for example, phosphorus or arsenic having a thickness of 10 nm to 500 nm.¹⁸cm^-3To 10^{twenty one}cm^-3It consists of added polysilicon.
[0223]
An element isolation insulating film 301 (see FIG. 53A) made of, for example, a silicon oxide film is formed in a self-aligned manner with respect to the charge storage layer 152. For example, the tunnel gate insulating film 151 and the charge storage layer 152 are deposited on the entire surface of the semiconductor substrate 150 and then patterned to reach the semiconductor substrate 150 until the semiconductor substrate 150 reaches a depth of, for example, 0.50 nm to 300 nm. It can be formed by etching up to this point and embedding an insulating film. As described above, since the tunnel gate insulating film 151 and the charge storage layer 152 can be formed on the entire surface without a step, it is possible to perform film formation with improved uniformity and uniform characteristics.
[0224]
On this, a control gate electrode 154 is formed via an interpoly insulating film 153. The interpoly insulating film 153 is made of, for example, a silicon oxide film or an oxynitride film having a thickness of 5 nm to 30 nm, or a silicon oxide film / silicon nitride film / silicon oxide film. The gate electrode 154 is made of, for example, phosphorus, arsenic, or boron having a thickness of 10 nm to 500 nm.¹⁷cm^-3To 10^{twenty one}cm^-3Is doped with polysilicon, or a stacked structure of WSi (tungsten silicide) and polysilicon, or a stacked structure of NiSi, MoSi, TiSi, CoSi and polysilicon. A memory cell gate 161 and a select gate 162 are formed in a stacked structure including a tunnel gate insulating film 151, a charge storage layer 152, an interpoly insulating film 153, and a gate electrode 154. Further, a mask insulating film made of a silicon oxide film or a silicon nitride film having a thickness of about 10 nm to 300 nm is disposed on the control gate electrode 154.
[0225]
In the LV transistor region LV, an LV gate insulating film 155 is formed on the substrate 150, and an LV gate electrode 156 is formed thereon. In the HV transistor region HV, an HV gate insulating film 157 is formed on the substrate 150, and an HV gate electrode 158 is formed thereon. The selection transistor, the LV transistor, and the HV transistor are provided with a terminal for directly applying a potential to the gate electrode in contact with the gate insulating film.
[0226]
As shown in FIG. 49, sidewall insulating films 159 made of, for example, a silicon nitride film or a silicon oxide film having a thickness of 5 nm to 200 nm are formed on both sides of these gate electrodes. In addition, an N-type source / drain diffusion layer 160 is formed on the surface of the substrate 150. These source / drain type diffusion layers 160 are made of, for example, phosphorus, arsenic, or antimony with a surface concentration of 10¹⁷cm^-3To 10^{twenty one}cm^-3It is formed between 10 nm and 500 nm in depth. Further, these source / drain diffusion layers 160 are shared by adjacent memory cell transistors, and NAND connection is realized. The source / drain diffusion layer 160, the memory cell gate 161, and the select gate 162 form a floating gate type EEPROM cell that uses the amount of charge stored in the charge storage layer 152 as an information amount. The gate length is, for example, 0.5 μm or less and 0.01 μm or more.
[0227]
The source / drain diffusion layer 160 on one end side of the selection gate 162 is connected to the data transfer line 167 via the contact plug 163. The data transfer line 167 is made of tungsten, tungsten silicide, titanium, titanium nitride, or aluminum. The contact plug 163 is filled with, for example, N-type or P-type doped polysilicon or tungsten, tungsten silicide, Al, TiN, Ti, or the like to form a conductor region.
[0228]
The selection gate 162 forms a selection transistor. The gate length of the selection gate 162 is longer than the gate length of the memory cell gate 161, for example, 1 μm or less and 0.02 μm or more. Thereby, a large on / off ratio at the time of block selection and non-selection can be secured, and erroneous writing and erroneous reading can be prevented.
[0229]
Each of these elements is, for example, SiO₂And an interlayer film 165 made of SiN. Furthermore, on the interlayer film 165, for example, SiO₂An insulating film protective layer (not shown) made of Si, SiN, or polyimide, or an upper wiring (not shown) made of W, Al, or Cu, for example, is formed.
[0230]
A first element isolation region 166 having a structure as shown in FIG. 1A is disposed between the memory cell region MC and the LV transistor region LV. A second element isolation region 167 having a structure as shown in FIG. 27B is disposed between the LV transistor and the HV transistor region HV.
[0231]
A contact plug 168 is connected to the source / drain diffusion layer 160 in the LV transistor region LV. Contact plug 168 is connected to wiring 169. A contact plug 170 is connected to the source / drain diffusion layer 160 in the HV transistor region HV. The contact plug 170 is connected to the wiring 171.
[0232]
The selection transistor shown in FIG. 49 has the same stacked gate structure as the memory cell transistor. In this case, the manufacturing cost can be reduced because the process for making the selection transistor and the memory cell transistor can be omitted. In addition, since there is no need to make a margin for separate production, the distance between the select transistor and the memory cell can be reduced, and the element area can be reduced.
[0233]
In the structure shown in FIG. 49, there is no gate insulating film on the substrate 150 where the gate is not formed.
[0234]
FIG. 50 shows a modification of the structure shown in FIG. Here, the structure of the control gate in the memory cell region MC, the LV gate in the LV transistor region LV, and the HV gate in the HV transistor region HV are different from the structure shown in FIG. is there.
[0235]
In the control gate 172, the gate electrode 154 in the memory cell gate 161 is stacked on the semiconductor substrate 150 via the tunnel gate insulating film 151. A sidewall insulating film 159 is formed around the periphery. In the LV gate 173, the gate electrode 154 in the memory cell gate 161 is stacked on the semiconductor substrate 150 via the LV gate insulating film 155. A sidewall insulating film 159 is formed around the periphery. In the HV gate 174, the gate electrode 154 in the memory cell gate 161 is stacked on the semiconductor substrate 150 via the HV gate insulating film 157. A sidewall insulating film 159 is formed around the periphery. That is, in FIG. 49, the transistors and selection transistors that form the peripheral circuit also have a stacked gate similar to that of the memory cell, but may be a single-layer gate as shown in FIG.
[0236]
FIG. 51 shows another modification of the structure shown in FIG. Here, the structure shown in FIG. 50 is the same as the structure shown in FIG. 50 except that the gate insulating film in each transistor region covers the exposed surface of the semiconductor substrate 150 in each region. That is, in FIGS. 49 and 50, the gate insulating film does not exist in the region where the gate electrode is etched, but the gate insulating film may be left on the entire surface of the semiconductor substrate 150 as shown in FIG.
[0237]
As the structure of the boundary BS between the memory cell region MC and the LV transistor region LV in FIG. 49, the structure shown in FIGS. 52A to 52H can be adopted. Here, these structures can be applied to the boundary BS between the memory cell region MC and the HV transistor region HV by exchanging the LV gate insulating film and the HV gate insulating film.
[0238]
The structure of the boundary of each creation may be unified into the same structure, or may be different structures depending on places. Moreover, it is good also as a structure which does not form the diffusion layer 160 in each boundary part BS.
[0239]
In the boundary portion BS shown in FIG. 52A, an element isolation region 166 similar to the structure shown in FIG. Source / drain diffusion layers 160 are formed in the substrate 150 on both sides of the element isolation region 166. At the bottom of the trench of the element isolation region 166, a step having a convex portion that is convex upward is formed. By adopting such a boundary BS structure, STI embedding can be improved, dishing can be prevented, and the area can be reduced.
[0240]
At the boundary BS shown in FIG. 52B, a gate structure is formed to cover the element isolation region 166 in the structure shown in FIG. This gate structure has the same structure as the selection gate 162 on the tunnel gate insulating film 151 and the LV gate insulating film 155 at the boundary BS, and is selected without the charge storage layer 152 on the element isolation region 166. It has the same structure as the gate 162. By adopting such a boundary BS structure, STI embedding can be improved, dishing can be prevented, and gate processing can be facilitated.
[0241]
In the boundary portion BS shown in FIG. 52C, an element isolation region 175 similar to the structure shown in FIG. 14A is replaced with the element isolation region 166 in FIG. By adopting such a structure of the boundary portion BS, the breakdown voltage of the STI can be improved and the area can be reduced.
[0242]
In the boundary portion BS shown in FIG. 52 (d), the element isolation region 166 is replaced with the element isolation region 175 shown in FIG. 52 (c) in the structure shown in FIG. 52 (b). By adopting such a structure of the boundary portion BS, the breakdown voltage of STI can be improved and gate processing can be facilitated.
[0243]
In the boundary portion BS shown in FIG. 52 (e), a structure similar to the structure shown in FIG. 2 (a) is formed. On the substrate 150 in the center of the boundary BS, a gate structure 176 is formed which is formed from the constituent material of the gate structure of the memory cell region MC and the LV transistor region LV. In the gate structure 176, a tunnel insulating film 151 is formed on the memory cell region MC side on the substrate 150, and an LV gate insulating film 155 is formed on the LV transistor region LV side. On the tunnel insulating film 151 and the insulating film 155, the electrode layer 20, the sidewall insulating film 159, and the like are formed. Source / drain diffusion layers 160 are formed in the substrate 150 on both sides of the gate structure 176. By adopting such a structure of the boundary portion BS, gate processing can be facilitated and defects due to STI can be avoided.
[0244]
The boundary portion BS shown in FIG. 52 (f) has the same structure of the boundary portion BS as the structure shown in FIG. 2 (b). A gate structure 177 is formed on the substrate 150 in the center of the boundary portion BS. The gate structure 177 is formed of a material constituting the gate structure of the memory cell region MC and the LV transistor region LV. In the gate structure 177, a tunnel insulating film 151 is disposed on the substrate 150 on the memory cell region MC side, and an LV gate insulating film 155 is disposed on the LV transistor region LV side. A laminated gate structure similar to the control gate 162 is provided on the tunnel insulating film 151, and a lower layer structure of the LV gate electrode 156 is provided on the LV gate insulating film 155. An insulating film 159 is formed on the side surface of the gate structure 177. By adopting such a structure of the boundary portion BS, dust can be reduced and defects due to STI can be avoided.
[0245]
The boundary portion BS shown in FIG. 52 (g) has the same structure of the boundary portion BS as the structure shown in FIG. 15 (a), and a recess 178 is disposed on the substrate 150. By adopting such a structure of the boundary portion BS, dust can be reduced and defects due to STI can be avoided.
[0246]
In the boundary portion BS shown in FIG. 52 (h), a structure similar to that of the selection gate 162 shown in FIG. 15 (b) is shown. Here, a recess is formed on the surface of the semiconductor substrate 150 at the center of the boundary, but it may be flat as in FIG. In this gate structure, the electrode layer is in direct contact with the surface of the substrate 150 without using an insulating film. By adopting such a structure of the boundary portion BS, the gate processing is easy, dust is reduced, defects due to STI are avoided, and the boundary portion BS has the same aspect ratio.
[0247]
FIG. 53A shows a cross section in the direction perpendicular to the data transfer line on the gate of the memory cell. FIG. 53B shows a cross section in a direction perpendicular to the data transfer line on the gates of the peripheral transistors.
[0248]
As shown in FIGS. 53A and 53B, the element isolation region 301 covers the side surfaces of the substrate 150 and the gate insulating film. Therefore, the etching before forming the tunnel gate insulating film 151 does not expose the end of the element isolation region, and the gate electrode 154 is located below the surface of the substrate 150 in both the memory cell and the peripheral transistor. Can prevent. In this manner, electric field concentration at the boundary between the element isolation region 301 and the tunnel gate insulating film 151 and a parasitic transistor with a lowered threshold value are unlikely to occur. Further, since a sidewalk phenomenon, which is a phenomenon of lowering the write threshold due to bird's beak, is less likely to occur, a more reliable transistor can be formed.
[0249]
Next, an example of a method for manufacturing the nonvolatile semiconductor memory device of the present embodiment shown in FIG. 49 will be described with reference to FIGS. 54 (a) to 57 (c). First, a sacrificial oxide film (not shown) is formed on the surface of the semiconductor substrate 150. After implanting well impurities and channel impurities as necessary, the sacrificial oxide film is removed.
[0250]
Next, as shown in FIG. 54A, a tunnel gate insulating film 151 made of, for example, a silicon oxide film or an oxynitride film having a thickness of 3 nm to 15 nm is formed on the semiconductor substrate 150. . Next, for example, polysilicon is deposited to a thickness of 10 nm to 500 nm to form the charge storage layer 152.
[0251]
Next, as shown in FIG. 54B, the portion to be the memory cell region MC is covered with a photoresist layer 180, and the gate electrode and the gate insulating film in other regions are removed. The removal method may be either isotropic etching such as wet etching or anisotropic etching such as RIE. Next, as shown in FIG. 54C, a gate insulating film 157 of an HV transistor made of, for example, a silicon oxide film or an oxynitride film having a thickness of 5 nm to 50 nm is formed on the entire surface of the semiconductor substrate 150. To do.
[0252]
Next, as shown in FIG. 55A, the HV transistor region HV is covered with a photoresist layer 181 and the gate insulating film in the HV transistor region HV is removed from other regions. Next, as shown in FIG. 55B, over the entire surface of the semiconductor substrate 150, for example, the gate of an LV transistor made of a silicon oxide film or oxynitride film having a thickness of, for example, between 1 nm and 10 nm. An insulating film 155 is formed. Furthermore, for example, polysilicon is deposited to a thickness of 10 nm to 500 nm.
[0253]
At this time, the memory cell region MC has a stacked structure in which the gate insulating film 155 and the first gate electrode 182 of the LV transistor are formed on the gate electrode of the memory cell. In addition, the thickness of the gate insulating film 157 of the HV transistor formed in advance is also increased. Here, the gate electrode of the memory cell and the gate electrode of the LV transistor may use different materials and film thicknesses. However, if the same material and the same film thickness are used, it is easy to simultaneously etch the gate electrode.
[0254]
Next, as shown in FIG. 55C, the region (peripheral circuit region) of the LV transistor and the HV transistor is covered with a photoresist layer 183, and the gate electrode and the gate insulating film in other regions are removed. The removal method may be either isotropic etching such as wet etching or anisotropic etching such as RIE. At this time, a part of the photoresist layer 183 covers the memory cell region MC. Therefore, the gate electrode remains in the stacked structure at the boundary BS where the memory cell region MC and the peripheral circuit region are separately formed.
[0255]
Next, as shown in FIG. 56A, the photoresist layer 183 is removed, and a first mask layer 184 and a second mask layer 185 are deposited. The first mask layer 184 is, for example, a silicon nitride film, and the second mask layer 185 is, for example, a silicon oxide film. Next, as shown in FIG. 56B, a photoresist mask 186 for forming an element isolation region is deposited to form an element isolation pattern. Here, a method for forming an element isolation region without leaving a resist at the boundary portion BS that is separately formed will be described.
[0256]
Next, after removing the photomask 186 and the second mask layer 185 by anisotropic etching, the first gate electrodes 152 and 182 are removed by anisotropic etching. Subsequently, the semiconductor substrate 150 is etched to form first and second element isolation trenches in order to form an element isolation region. The depth of the element isolation trench is, for example, about 50 nm to 300 nm.
[0257]
The boundary portion BS is formed in a convex shape at the bottom of the element isolation region due to the step shown in FIG. The step of the convex portion depends on the step in FIG. 56B and the etching conditions, but is, for example, about 10 nm to 300 nm, preferably about 30 nm to 100 nm. Also, the depth of the bottom of the element isolation region differs depending on the contact region, which reflects the difference in film thickness between the tunnel insulating film thickness of the memory cell and the gate insulating film of the LV transistor and the gate insulating film of the HV transistor. The thinner the insulating film, the deeper the element isolation region.
[0258]
Further, the isolation region trench is filled with an insulating film such as a silicon oxide film, and the filling material is etched back by using a method such as CMP with the first mask layer 184 as a stopper. Since the element isolation boundary portion BS has a shallow element isolation depth, the embedding property is good, and the upper part of the element isolation insulating film becomes almost flat after the etch back. The first mask layer 184 is removed, and the first gate electrode 182 in the LV transistor region LV and the HV transistor region HV has the same thickness as the charge storage layer 152. Thereafter, the insulating film embedded in the element isolation trench is etched back. The shape at this time is shown in FIG.
[0259]
Next, as shown in FIG. 57A, for example, an interpoly insulation made of a silicon oxide film or oxynitride film having a thickness of 5 nm to 30 nm, or a silicon oxide film / silicon nitride film / silicon oxide film. A film 153 is formed. Next, as shown in FIG. 57B, a gate electrode 154 is deposited on the entire surface of the semiconductor substrate 150. The gate electrode 154 is made of polycrystalline silicon, a laminated film of polycrystalline silicon and metal or a compound of silicon and metal, or a single layer film of metal or a compound of silicon and metal. Next, a mask insulating film made of a silicon oxide film or silicon nitride film having a thickness of about 10 nm to 300 nm is deposited. Next, a photoresist layer 187 for processing the gate electrode is deposited to form a pattern. Next, the gate electrode is anisotropically etched using the photoresist layer 187 as a mask. Next, the processing damage is recovered by post-oxidation or the like.
[0260]
Next, as shown in FIG. 57 (c), a gate sidewall insulating film 159 is formed as necessary, and diffusion layer impurities are implanted to form a source / drain diffusion layer 160. Next, as shown in FIG. At this time, the boundary portion BS does not leave a resist, and the gate electrode of the boundary portion BS is removed. Further, although not shown, an interlayer insulating film, contact plugs, wirings, and the like are formed to complete the semiconductor device as shown in FIG.
[0261]
Also in the manufacturing method of the present embodiment, the effects of the manufacturing methods in the first to third embodiments and the fourth embodiment can be obtained in the same manner except for the effects unique to MONOS.
[0262]
(Sixth embodiment)
The present embodiment is applied to an AND-type EEPROM having a MONOS-type memory cell structure, as shown in FIG. FIG. 58 can be said to be another modification of the structure shown in FIG. Here, a boundary portion BS is disposed between the memory cell region MC and the select transistor region STR for the memory cell. In the boundary portion BS, a recess 136 is formed on the surface of the substrate 102 in the same manner as the structure shown in FIGS. 40 (g) and 15 (a). A tunnel gate insulating film 103 and a charge storage layer 104 are formed on the substrate 102 on the memory cell region MC side from the recess 136. Desirably, if the gate insulating film of the selection transistor 128 is shared with the LV-based gate insulating film 113, the process can be simplified. An equivalent circuit of the memory cell block is as shown in FIG. The structure of the boundary portion BS may be any of FIGS. 40A to 40H, and a preferable form can be used from the viewpoints of the number of steps and ease of processing.
[0263]
Next, FIG. 59A shows a cross section in the direction perpendicular to the data transfer line on the gate of the memory cell. FIG. 59B shows a cross section in the direction perpendicular to the data transfer line on the gate of the selection transistor.
[0264]
As shown in FIGS. 59A and 59B, the side surface of the substrate 102 is covered with the element isolation region 302. Therefore, the etching before forming the ONO film 131 does not expose the end of the element isolation region, and the gate electrodes 106 and 108 are located below the surface of the substrate 102. Can prevent. For this reason, gate concentration at the boundary between the substrate 102 and the ONO film 131 and a parasitic transistor whose threshold value has decreased are unlikely to occur. Further, since a sidewalk phenomenon, which is a phenomenon of lowering the write threshold due to bird's beak, is less likely to occur, a more reliable transistor can be formed.
[0265]
By making the selection transistor a MOS transistor, fluctuations in the threshold due to voltage stress for operation are eliminated. For this reason, a highly reliable nonvolatile memory can be realized. Also in this embodiment, the same effects as those in the first to third embodiments and the fourth embodiment can be obtained.
[0266]
In each of the above embodiments, the memory cell transistors are formed prior to the peripheral circuit transistors. However, the order of making is not limited to this, and the peripheral circuit transistors may be formed first. In the fourth to sixth embodiments, the memory cell region MC and the LV transistor region LV, and the HV transistor region HV and the LV transistor region LV are adjacent to each other through a boundary. However, the mode of adjacent regions is not limited to this, and for example, the memory cell region MC and the HV transistor region HV may be adjacent to each other via a boundary portion.
[0267]
【The invention's effect】
  According to the present invention, a plurality of gate insulating films having different film materials or film thicknesses are provided.Manufacturing method of semiconductor deviceCan improve the reliability.
[Brief description of the drawings]
FIGS. 1A and 1B are cross-sectional views showing the vicinity of a boundary portion of a semiconductor device according to a first embodiment of the present invention and a modification thereof, respectively.
FIGS. 2A and 2B are cross-sectional views showing the vicinity of a boundary portion of a semiconductor device according to another modification of the first embodiment, respectively.
FIGS. 3A and 3B are cross-sectional views showing the gate electrodes of the first and second transistor regions in the first embodiment along the extending direction, respectively. FIGS.
4A to 4C are cross-sectional views showing a method for manufacturing the structure shown in FIG.
5A to 5C are cross-sectional views showing a method for manufacturing the structure shown in FIG. 1A, following FIG. 4C.
6A to 6C are cross-sectional views showing a method for manufacturing the structure shown in FIG. 1A, following FIG. 5C.
7A to 7C are cross-sectional views showing a method for manufacturing the structure shown in FIG. 1A, following FIG. 6C.
FIG. 8 is a cross-sectional view showing a method for manufacturing the structure shown in FIG. 1A, following FIG. 7C;
9 is a cross-sectional view showing a method for manufacturing the structure shown in FIG.
FIGS. 10A and 10B are cross-sectional views showing a method for manufacturing the structure shown in FIG.
11A and 11B are cross-sectional views showing a method for manufacturing the structure shown in FIG. 2A, following FIG. 10B.
12A and 12B are cross-sectional views showing a method for manufacturing the structure shown in FIG. 2A, following FIG. 11B.
13 is a cross-sectional view showing a manufacturing method of the structure shown in FIG.
14A and 14B are cross-sectional views showing the vicinity of a boundary portion of a semiconductor device according to a second embodiment of the present invention and a modification thereof, respectively.
FIGS. 15A and 15B are cross-sectional views each showing a vicinity of a boundary portion of a semiconductor device according to another modification of the second embodiment. FIGS.
FIGS. 16A to 16C are cross-sectional views showing a method for manufacturing the structure shown in FIG.
17A to 17C are cross-sectional views showing a method for manufacturing the structure shown in FIG. 14A, following FIG. 16C.
18A to 18C are cross-sectional views showing a method for manufacturing the structure shown in FIG. 14A, following FIG. 17C.
19A to 19C are cross-sectional views showing a method for manufacturing the structure shown in FIG. 14A, following FIG. 18C.
20 is a cross-sectional view showing a method for manufacturing the structure shown in FIG. 14A, following FIG. 19C;
21 is a cross-sectional view showing a method for manufacturing the structure shown in FIG.
22 is a cross-sectional view showing a method for manufacturing the structure shown in FIG. 14B, following FIG. 21;
23 (a) and 23 (b) are cross-sectional views showing a method for manufacturing the structure shown in FIG. 15 (a).
24A and 24B are cross-sectional views showing a method for manufacturing the structure shown in FIG. 15A, following FIG. 23B.
25A and 25B are cross-sectional views showing a method for manufacturing the structure shown in FIG. 15A, following FIG. 24B.
26 is a cross-sectional view showing a method of manufacturing the structure shown in FIG.
FIGS. 27A and 27B are cross-sectional views showing the vicinity of a boundary portion of a semiconductor device according to a third embodiment of the present invention and a modification thereof, respectively. FIGS.
28A to 28C are cross-sectional views showing the gate electrodes of the first, second, and third transistor regions in the third embodiment, respectively, along the extending direction.
29A to 29C are cross-sectional views showing a method of manufacturing the structure shown in FIG.
30A to 30C are cross-sectional views showing a method for manufacturing the structure shown in FIG. 27A, following FIG. 29C.
FIGS. 31A and 31B are cross-sectional views showing a method for manufacturing the structure shown in FIG. 27A, following FIG.
32A to 32D are cross-sectional views showing a method for manufacturing the structure shown in FIG. 27B.
33 (a) to 33 (c) are cross-sectional views showing a method for manufacturing the structure shown in FIG. 27 (b), following FIG. 32 (d).
34A and 34B are cross-sectional views showing a method for manufacturing the structure shown in FIG. 27B, following FIG. 33C.
FIG. 35 is a sectional view showing the vicinity of a boundary portion of a semiconductor device according to a fourth embodiment of the invention.
FIG. 36 is a cross-sectional view showing the vicinity of a boundary portion of a semiconductor device according to a modification of the fourth embodiment.
FIG. 37 is a cross-sectional view showing the vicinity of a boundary portion of a semiconductor device according to another modification of the fourth embodiment;
FIG. 38 is an equivalent circuit diagram showing a NAND MONOS memory cell of the semiconductor device according to the fourth embodiment.
FIG. 39 is another equivalent circuit diagram showing a NAND MONOS type memory cell of the semiconductor device according to the fourth embodiment.
FIGS. 40A to 40H are cross-sectional views showing structures that can be used as boundaries between the memory cell region and the LV transistor region in the device shown in FIG. 37, respectively.
FIGS. 41A and 41B are cross-sectional views showing a memory cell region and a peripheral transistor region of a NAND MONOS semiconductor device according to the fourth embodiment, respectively.
FIG. 42 is an equivalent circuit diagram showing a NOR type MONOS type memory cell of a semiconductor device according to a fourth embodiment.
FIG. 43 is an equivalent circuit diagram showing an AND MONOS type memory cell of the semiconductor device according to the fourth embodiment.
FIG. 44 is another equivalent circuit diagram showing an AND-type MONOS type memory cell of the semiconductor device according to the fourth embodiment.
45 (a) to 45 (c) are cross-sectional views showing a method for manufacturing the structure shown in FIG.
46 (a) to 46 (c) are cross-sectional views showing a method for manufacturing the structure shown in FIG. 35, following FIG. 45 (c).
47 (a) to 47 (c) are cross-sectional views showing a method for manufacturing the structure shown in FIG. 35, following FIG. 46 (c).
48 (a) to 48 (c) are cross-sectional views showing a method of manufacturing the structure shown in FIG. 35, following FIG. 47 (c).
FIG. 49 is a sectional view showing the vicinity of a boundary portion of a semiconductor device according to a fifth embodiment of the invention.
FIG. 50 is a cross-sectional view showing the vicinity of a boundary portion of a semiconductor device according to a modification of the fifth embodiment.
FIG. 51 is a cross-sectional view showing the vicinity of a boundary portion of a semiconductor device according to another modification of the fifth embodiment;
52A to 52H are cross-sectional views showing structures that can be used as boundaries between the memory cell region and the LV transistor region in the device shown in FIG. 51, respectively.
FIGS. 53A and 53B are cross-sectional views showing a memory cell region and a peripheral transistor region of a NAND type floating gate type semiconductor device according to a fifth embodiment, respectively.
54 (a) to 54 (c) are cross-sectional views showing a method of manufacturing the structure shown in FIG.
55 (a) to 55 (c) are cross-sectional views showing a method for manufacturing the structure shown in FIG. 49, following FIG. 54 (c).
56 (a) to 56 (c) are cross-sectional views showing a method for manufacturing the structure shown in FIG. 49, following FIG. 55 (c).
57 (a) to 57 (c) are cross-sectional views showing a method for manufacturing the structure shown in FIG. 49, following FIG. 56 (c).
FIG. 58 is a sectional view showing the vicinity of a boundary portion of a semiconductor device according to a sixth embodiment of the invention.
FIGS. 59A and 59B are cross-sectional views showing a memory cell region and a peripheral transistor region of an AND type MONOS type semiconductor device according to the sixth embodiment, respectively.
60A to 60D are cross-sectional views showing a conventional trench type element isolation method, and FIG. 60E is an enlarged cross-sectional view showing a region TP in FIG.
61 (a) to 61 (d) are cross-sectional views showing a conventional self-aligned trench isolation method.
FIGS. 62A and 62B are cross-sectional views for explaining problems of the method shown in FIGS. 61A to 61D, respectively.
[Explanation of symbols]
TR1, TR2, TR3 ... transistor region
BS ... Boundary part
MC: Memory cell area
PTR ... Peripheral transistor area
LV ... Low voltage transistor region
HV ... High-voltage transistor region
1, 102 ... Semiconductor substrate
2, 3, 73 ... gate insulating film
4, 11, 74, 82 ... lower electrode layer
5, 12, 16, 75, 83 ... upper electrode layer
6, 13, 76, 84 ... gate electrode
7, 14, 77, 85, 112, 160 ... source / drain diffusion layers
8, 15, 78, 86 ... transistor
9, 26, 50, 72, 80, 120, 121, 132, 133, 145, 146, 166, 167, 175, 300, 301, 302 ... element isolation region
10, 71 ... convex part
17, 18, 134, 176 ... gate structure
20, 22, 23, 25, 53 ... electrode layer
21, 119, 159 ... sidewall insulating film
30, 31, 34, 38, 39, 40, 41, 43, 56, 57, 60, 63, 65, 67, 69, 70, 91, 92, 95, 97, 98, 101, 138, 139, 141, 144, 148, 180, 181, 183, 186, 187 ... Photoresist layer
32, 33, 58, 59, 93, 94, 99, 100, 142, 143, 184, 185 ... mask layer
36, 61, 145, 146 ... trench
44, 52, 64, 136, 178 ... concave portion
37, 62 ... Insulator
42 ... diffusion layer
51 ... downward convex part
54, 55 ... conductive side walls
103, 151 ... Tunnel gate insulating film
104, 152 ... charge storage layer
106, 154... Control gate electrode
107, 161 ... Memory cell gate
108, 162 ... selection gate
109, 156, 173 ... LV gate
111, 158, 174 ... HV system gate

Claims (2)

Forming a first insulating film on a semiconductor substrate having a main surface including first and second regions and a boundary portion disposed between and in contact with the first and second regions;
The first lower electrode layer is disposed on the first region of the first insulating film and the portion in the boundary portion, and the main surface is removed by removing the portion of the first insulating film in the second region. A step of exposing
Forming a second insulating film on the first lower electrode layer in the first region and the boundary and on the main surface in the second region; and the second insulating film is formed by the first insulating film. Having a film material or film thickness different from the film;
A second lower electrode layer is disposed on the second region of the second insulating film and a portion in the boundary portion, while a portion of the second insulating film in the first region is removed and the first region is removed. A lower electrode layer is exposed, and a laminated portion is formed in which the end portions of the second insulating film and the second lower electrode layer are laminated on the upper surface of the end portion of the first lower electrode layer within the boundary portion. And a process of
Etching the main surfaces in the first and second regions in a self-aligned manner with respect to the first and second lower electrode layers to form trenches for element isolation in the first and second regions. Simultaneously with the formation, the main surface in the boundary portion is pattern-etched from above to form a trench for element isolation in the boundary portion, and the bottom portion of the trench in the boundary portion is caused by the stacked portion. Forming an upward convex portion;
Filling the trenches in the first and second regions and the boundary with an insulating layer to form an element isolation region;
Forming an upper electrode layer on the first and second lower electrode layers;
Pattern-etching the first and second lower electrode layers and the upper electrode layer to form first and second gate electrodes in the first and second regions;
A method for manufacturing a semiconductor device, comprising: Forming a first insulating film on a semiconductor substrate having a main surface including first and second regions and a boundary portion disposed between and in contact with the first and second regions;
The first lower electrode layer is disposed on the first region of the first insulating film and the portion in the boundary portion, and the main surface is removed by removing the portion of the first insulating film in the second region. A step of exposing
Forming a second insulating film on the first lower electrode layer in the first region and the boundary and on the main surface in the second region; and the second insulating film is formed by the first insulating film. Having a film material or film thickness different from the film;
A second lower electrode layer is disposed on the second region of the second insulating film and a portion in the boundary portion, while a portion of the second insulating film in the first region is removed and the first region is removed. Exposing the lower electrode layer;
Forming a gap between the end of the second lower electrode layer and the end of the first lower electrode layer within the boundary;
Etching the main surfaces in the first and second regions in a self-aligned manner with respect to the first and second lower electrode layers to form trenches for element isolation in the first and second regions. Simultaneously with the formation, the main surface in the boundary portion is subjected to pattern etching from the upper side to form a trench for element isolation in the boundary portion, and the bottom portion of the trench in the boundary portion faces downward due to the gap. Forming a convex portion of
Filling the trenches in the first and second regions and the boundary with an insulating layer to form an element isolation region;
Forming an upper electrode layer on the first and second lower electrode layers;
Pattern-etching the first and second lower electrode layers and the upper electrode layer to form first and second gate electrodes in the first and second regions;
A method for manufacturing a semiconductor device, comprising:

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