JP4319810B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

【００１２】
前記第一導電型の半導体素材としては、Ｎ⁺型又はＰ⁺型半導体基板上に積層したN^-型半導体層や、Ｎ型単結晶基板が好適に用いられるが、Ｐ型を用いても良い。前記第一導電型領域側の第二電極はこれらの半導体基板の裏面に付設すれば足りる。
【００１５】
【発明の実施の形態】
以下に本発明の一実施の形態につき図面を参照して説明する。以下は本発明の一実施形態であって本発明を限定するものではない。
まず、図１を参照して本ＪＢＳの構造につき説明する。図１は本発明の一実施形態のＪＢＳを示す断面図（下部）と平面図（上部）である。なお、本実施形態においては、Ｐ型活性領域４が前記第二導電型活性領域に対応し、N^-型領域３が前記第一導電型領域に対応する。
【００１６】
図１に示すように本ＪＢＳは、Ｎ⁺型の半導体基板１と、半導体基板１上にN^-型でエピタキシャル成長により形成された半導体層２とを備える。
半導体層２の表層中央部には表面視円形状の多数のＰ型活性領域４が不純物導入によりに等間隔に形成され、これらを包囲するようにＰ型のガードリング５が形成される。半導体層２の表層最外周部にはＮ⁺型又はＰ⁺型のチャネルストップ領域６がガードリング５と間隔を隔てて不純物導入により形成される。半導体層２の残存部がN^-型領域３となる。
【００１７】
さらに本ＪＢＳは、半導体層２表面上に敷設されるバリアメタル７と、半導体酸化膜８と、ＰＳＧ（リン・珪酸・ガラス）保護膜２３bとを備える。
バリアメタル７は、ガードリング５の内周縁及びガードリング５に囲まれた全領域を覆っている。したがって、ガードリング５に囲まれた領域で半導体層２表面上に露出するＰ型活性領域４の露出面及びN^-型領域３の露出面はバリアメタル７によって覆われている。Ｐ型活性領域４とN^-型領域３によりＰＮ接合が形成され、N^-型領域３とバリアメタル７によってショットキー接合が形成される。
バリアメタル７の第一導電型領域であるN^-型領域３に対するショットキー障壁高さ（φBN）は、φBN≧０．６８ｅＶである。このような条件を満たす半導体と金属との組み合せの例を、各組み合せにおけるφBN値を括弧内に示して列挙する。例えば、Si（n型）に対してはAg（φBN＝0.78eV）, Al（φBN＝0.72eV）, Au（φBN＝0.80eV）, Mo（φBN＝0.68eV）, Pd（φBN＝0.81eV）, Pt（φBN＝0.90eV）である。GaAs（n型）に対してはAg（φBN＝0.88eV）, Al（φBN＝0.80eV）, Au（φBN＝0.90eV），Cu（φBN＝0.82eV）, Hf（φBN＝0.72eV）, Pt（φBN＝0.84eV），Ta（φBN＝0.85eV）, W（φBN＝0.80eV）である。GaAs（ｐ型）に対してはHf（φBN＝0.68eV）である。
半導体酸化膜８は、ガードリング５の外周縁及びチャネルストップ領域６の内周縁及びガードリング５とチャネルストップ領域６との間で露出するN^-型領域３の露出面を覆っている。
ＰＳＧ保護膜２３bは、この半導体酸化膜８に敷設されている。
【００１８】
さらに本ＪＢＳは、第一電極メタル９と、第二電極メタル１０と、等電位リング（Equi-Potential-Ring）電極メタル１１と、最終絶縁保護膜２４とを備える。本ＪＢＳでは第一電極メタル９が陽極電極、第二電極メタル１０が陰極電極となり、本ＪＢＳはこれら２電極を端子とするダイオードを成す。
半導体酸化膜８の開口部を介して第一電極メタル９がガードリング５及びバリアメタル７に接合する。
N^-型領域３側の電極である第二電極メタル１０は、半導体基板１の裏面に被着される。
等電位リング電極メタル１１は第二電極メタル１０と等電位に保持されているものであり、半導体酸化膜８の外周開口部を介してチャネルストップ領域６に接続する。
第一電極メタル９、第二電極メタル１０及び等電位リング電極メタル１１はアルミニウム等により構成することができる。
最終絶縁保護膜２４は素子周辺領域にリング状に敷設されて第一電極メタル９の縁部及び等電位リング電極メタル１１を被覆し、電気的・機械的負荷から保護する。最終絶縁保護膜２４としては、シリコン窒化物やＰＳＧ膜を用いることができる。
【００１９】
図１に示すように本ＪＢＳはプレーナ技術により製作されるもので、Ｐ型活性領域４及びガードリング５の下端縁部は丸みを帯びており曲面接合を構成する。特に本ＪＢＳは、ガードリング５の下端外周縁である外端コーナー部１２に最大電界が生じるように構成されたものである。これにより高電圧印加時にガードリング５が形成された素子周辺部分によって高エネルギーを負担し耐久する。このようにガードリング５を形成し、かつ、最大電界がガードリング５で生じるように構成することにより高耐圧のＪＢＳを得ることができる。
【００２０】
次に、図２を参照して本ＪＢＳのショットキー接合面積率Ｓn／Ｓについて説明する。本ＪＢＳは、ガードリング５に囲まれる領域の面積をＳ、第二導電型活性領域であるＰ型活性領域４の面積をＳp、第一導電型領域であるN^-型領域３の面積をＳｎとするとき（Ｓ＝Ｓp＋Ｓn）、Ｓn／Ｓ≧４０％の関係を満たす。図２は図１においてガードリング５に囲まれる領域内の半導体層２表面の部分拡大図である。
【００２１】
図２(a)に示すように、半導体層２表面には円形状にＰ型活性領域４が露出し、Ｐ型活性領域４の周辺にN^-型領域３が露出する。
任意の一のＰ型活性領域４a（最外周を除く）の周囲に隣接して６つのＰ型活性領域４bが互いに等間隔に配置されたドットパターンで形成されている。６つのＰ型活性領域４bの各中心を結ぶと正六角形を成す。一のＰ型活性領域４aの中心はこの正六角形の中心に一致する。なお、縞状のパターンで形成しても良い。
【００２２】
正六角形は６つの正三角形に分割できる。いま、図２(b)に示すように一つの正三角形を取り出して考える。ガードリング５に囲まれる領域全体は、この図２(b)に示す正三角形を単位とする繰返しパターンで形成されることとなる。したがって、図２(b)に示す正三角形におけるＳp／Ｓ、Ｓn／Ｓはガードリング５に囲まれる領域全体のＳp／Ｓ、Ｓn／Ｓとして採用できる。かかる正三角形の一辺の長さをa、隣接する２つのＰ型活性領域（円形ドット）４の間隔の長さをb（＝Ｗn）とするとき、Ｓp／Ｓ、Ｓn／Ｓはそれぞれ次の式で表される。
Ｓp／Ｓ＝π（a-b）²／｛２√３・a²｝、Ｓn／Ｓ＝１−π（a-b）²／｛２√３・a²｝
【００２３】
例えば、Ｓn／Ｓ≧４０％の関係を満たす数値としてａ＝１５μｍ、b＝３μｍを挙げることができる。この場合、上式に代入して計算すると、Ｓp／Ｓ＝約５８％、Ｓn／Ｓ＝約４２％となる。なお、この場合、Ｐ型活性領域（円形ドット）４の直径が（a−b）で１２μｍとなる。Ｐ型活性領域（円形ドット）４の深さＸjpを例えば６μｍとするとき、Ｐ型活性領域（円形ドット）４の直径を（a−b）で１２μｍとするには、Ｐ型活性領域４を形成するためのマスクの開口部の幅を約２μｍとすることにより形成できる。これは、単一のＰ型活性領域４の形成幅（本実施形態では直径）をＷpとし、Ｐ型活性領域４の深さをＸjpとするとき、Ｗp−０．８×２×Ｘjpにより求められる。
【００２４】
順方向電圧降下ＶF、逆方向リーク電流ＩR、耐圧の向上のためにはショットキー接合面積Ｓnは少ない方が良いが、４０％未満に形成する、すなわち、Ｐ型活性領域４を６０％以上とする場合には、Ｐ型活性領域４を分散して形成することが難しい。また、隣接する２つのＰ型活性領域４間に形成されるN^-型領域３の形成幅をＷnとするとき、Ｗn≧１μｍの関係を満たすことにより、形成誤差によって２つのＰ型活性領域４が連続してしまう等の不都合を生じさせることなく容易にＰ型活性領域４を分散して形成することができる。
【００２５】
次に、図３及び図４を参照して本ＪＢＳの主要な製造工程につき説明する。図３及び図４は本発明一実施形態のＪＢＳを製造する主要工程における断面図である。
【００２６】
まず、図３（１）に示すように、Ｎ⁺型の半導体基板１上にエピタキシャル成長させたN^-型の半導体層２を有するウエファを酸化させ、その表裏に半導体酸化膜２１a，２２を形成する。例えば、半導体基板１及び半導体層２にシリコンを用いる。その場合、例えば、１０００℃で９０分の湿式酸化法により半導体酸化膜２１a，２２として約０・５μｍのシリコン酸化膜を形成する。
【００２７】
次に、図３（２）に示すように、半導体層２表面の半導体酸化膜２１aを周知のリソグラフィ・エッチング技術を用いて開口し酸化膜マスクパターン２１ｂとする。さらに、酸化膜マスクパターン２１ｂをマスクとしてＰ型不純物を半導体層２に導入する。それには例えば、ボロンをイオン注入することにより行う。Ｐ型不純物導入後、熱拡散しＰ型不純物を活性化させる。これによりＰ型活性領域４及びガードリング５が形成される。このとき図２に示したパターンを得るには、Ｐ型活性領域４を形成するための開口幅Ｋ１を２μｍとし、隣接する開口部間の間隔Ｋ２を１３μｍとし、Ｐ型活性領域４の深さ（Ｘjp）が約６μｍとなるようにＰ型不純物を注入する。これによりＰ型不純物は横方向にも進行し幅１２μｍのＰ型活性領域４が３μｍの間隔Ｋ３をもって形成される。
ガードリング５を形成する開口部の幅としては、例えば３０μｍとし、これにより約４０μｍ幅のガードリング５を形成する。
【００２８】
図３（３）に示すように、Ｐ型不純物導入後の熱拡散工程において半導体酸化膜２１ｂの開口部を含めて、ウエファ表面を酸化させ新たな半導体酸化膜２１ｃを形成する。
半導体酸化膜２１ｂ及び半導体酸化膜２１ｃの周縁部を周知のフォトリソグラフィ技術を用いてエッチングして開口する。これにより開口した開口部を介してＮ⁺型不純物を導入し、Ｎ⁺型のチャネルストップ層６を形成する。それには例えば、リンをイオン注入することにより行う。その深さＸjn+は例えば、1.2〜1.3μｍとされる。Ｎ⁺型不純物導入後、熱拡散しＮ⁺型不純物を活性化させる。
【００２９】
次に、図４（４）に示すように、ＰＳＧ（リン・珪酸・ガラス）膜２３aを形成する。なお図３（３）に示される半導体酸化膜２１ｂ及び２１ｃをまとめて半導体酸化膜２１ｄとして図４（４）中に示す。
【００３０】
次に、周知のリソグラフィ・エッチング・金属成膜技術を用いて、ＰＳＧ膜２３a及び半導体酸化膜２１ｄを開口して、図４（５）に示すようにＰＳＧ膜２３ｂ及び半導体酸化膜８とする。ＰＳＧ膜２３ｂ及び半導体酸化膜８の開口部を介して上述したバリアメタル７を図４（５）に示すようにガードリング５、Ｐ型活性領域４及びその間のN^-型領域３上に形成する。図４（５）に示すようにバリアメタル７をＰＳＧ膜２３b及び半導体酸化膜８の開口部全域のみならず、ＰＳＧ膜２３b及び半導体酸化膜８の内周縁上にまで敷設しても良い。しかしＰＳＧ膜２３b及び半導体酸化膜８の開口部の周縁を除くこの開口部より一回り小さい範囲にバリアメタル７を形成しても良い。
【００３１】
さらにその後、周知のリソグラフィ・エッチング・金属成膜技術を用いて、上述した第一電極メタル９と、等電位リング電極メタル１１を形成する。図４（５）に示すように上述した第一電極メタル９によりバリアメタル７を完全に覆うようにする。
以上の工程を経て残った半導体酸化膜８は、図１に示した半導体酸化膜８に対応する。なお、半導体酸化膜８上にはＰＳＧ膜２３bが形成される。
一方、ウエファ裏面を研削する。これにより、裏面の半導体酸化膜２２は除去される。
【００３２】
その後、図４（６）に示すようにウエファ裏面に上述した第二電極メタル１０を形成する。
さらに、図４（６）に示すように最終絶縁保護膜２４を周辺領域に形成する。中央の第一電極メタル９は露出させておく。最終絶縁保護膜２４としては、シリコン窒化物やＰＳＧ膜を用いることができる。
【００３３】
以上のようにして形成された素子に対しライフタイムキラーを導入するための電子線照射を行い、さらにその後アニール処理を行う。なお、電子線は表面側から照射すれば足りるが、本願発明者らは実験により裏面側から照射しても結果に大差はないことを確認している。
ライフタイムキラーを導入するための電子線の照射量をΦEIは式１を満たす値とする。また、アニール温度は３００〜３５０℃とする。
【００３４】
また、半導体素材である半導体層２の不純物濃度（Nd）とその厚み（ｄl）と第二導電型活性領域であるＰ型活性領域４の深さ（Ｘjp）は、最大電界強度Ｅmaxがガードリング５に生じて 逆電圧印加時において、Ｅmax≦３．０×１０⁵（Ｖ／ｃｍ）以下となるように決定する。
また、２つのＰ型活性領域４,４間の領域に生じる最大電界強度をEjbsとし、Ｓp＝０とした場合のショットキー接合に生じる電界強度をEsbdとするとき、Ejbs≦０．８６×Esbdの関係を満たすようにＳp／Ｓ比を決定する。
【００３５】
【実施例】
次に、以上の実施形態に該当する構成及び比較例について行った予備実験１，２、シミュレーション及び本実験１〜４を開示する。
まず、予備実験１，２及び本実験１〜４における実験試料の共通事項につき説明する。これらの実験試料及び計算対象構造は上記実施形態の図１に示した構造に従う。上記実施形態で特定していない条件をさらに記述する。
半導体基板１と半導体層２をシリコンとし、半導体酸化膜８をシリコン酸化膜とした。半導体層２はエピタキシャル成長法により形成したエピタキシャル層である。Ｐ型不純物としてボロンを用い、Ｎ型不純物としてリンを用いた。
バリアメタル７としては、パラジウム系金属を用いた。
第一電極メタル９、第二電極メタル１０及び電位リング電極メタル１１はアルミニウムを主用成分として構成した。
半導体基板１の厚みは２８０〜２８５μｍとした。
ガードリング５の幅は、４０μｍとした。
Ｎ⁺型のチャネルストップ層６は、リンをイオン注入することにより形成し、その深さＸjn+を1.2〜1.3μｍとした。
【００３６】
〔予備実験１〕
予備実験１は、異なるＳn／Ｓ比に対するデバイス特性の測定を行ったものである。図５の表に測定対象とその測定結果を示す。測定するデバイス特性は、順方向電圧降下ＶF（at 3A），逆方向リーク電流ＩR（at 180V），逆方向電圧ＶR（at 100μA）の３項目である。
図５の表に示すように半導体層２の比抵抗ρ＝6.0Ω・ｃｍとする計１２の試料を用意した。そのうち６試料は半導体層２の厚さｄl＝21μｍとしたWafer▲１▼に構成したもので図５(a)に測定結果の表を示す。他の６試料は半導体層２の厚さｄl＝28μｍとしたWafer▲２▼に構成したもので図５(b)に測定結果の表を示す。図５(a)(b)の表にそれぞれ示すようにＳn／Ｓ比を42％，58.3％，67.2％，77.3％，85.5％，1 00％とした。Ｓn／Ｓ比1 00％の試料は比較用のＳＢＤである。その他はＪＢＳである。いずれの試料もライフタイムキラーの導入を行っていない。
また、図５(a)の表に示す測定結果を特性毎にグラフ化したものを図６(a)(b)(c)に示す。図５(b)の表に示す測定結果を特性毎にグラフ化したものを図７(a)(b)(c)に示す。
【００３７】
〔予備実験２〕
予備実験２は、半導体層２の比抵抗ρ＝8.5Ω・ｃｍ，厚さｄl＝30μｍとするWafer▲３▼について異なるＳn／Ｓ比に対するデバイス特性の測定を行ったものである。図８の表に測定対象とその測定結果を示す。測定するデバイス特性は、順方向電圧降下ＶF（at 1A），逆方向リーク電流ＩR（at 280V），逆回復時間ｔrr（at 1A），逆方向電圧ＶR（at 200μA）の４項目である。
図８の表に示すようにＳn／Ｓ比を42％，1 00％とした。Ｓn／Ｓ比1 00％の試料は比較用のＳＢＤである。Ｓn／Ｓ比42％の試料がＪＢＳである。いずれの試料もライフタイムキラーの導入を行っていない。
図８の表に示す測定結果を特性毎にグラフ化したものを図９(a)(b)(c)(d)に示す。
【００３８】
〔シミュレーション〕
本シミュレーションは、ＪＢＳモデルとＳＢＤモデルに関する電界を計算したシミュレーションである。図１０(a)及び図１１(a)にＳＢＤモデルの計算対象領域の断面図を、図１０(b)及び図１１(b)にＪＢＳモデルの計算対象領域の断面図を示した。
ＪＢＳモデルとしては、半導体層２の比抵抗ρ＝8.5Ω・ｃｍ、厚さｄl＝29μｍと設定した。P型活性領域４及びガードリング５の表面濃度はCs≒3×10¹⁷／ｃｍ³と設定し、印加逆電圧はＶR=300Vと設定した。半導体層２をシリコンとし、半導体酸化膜８をシリコン酸化膜とした。
バリアメタル７は、パラジウム系金属とした。第一電極メタル９はアルミニウムとした。
ＳＢＤモデルは、P型活性領域４が無い、すなわち、Ｓp＝０である点のみ異なり、その他の点はＪＢＳモデルと同じとした。
【００３９】
（結果）
図１０に等電位曲線を重ねて示した。図１１に等電界強度曲線を重ねて示した。図１２は図１１の部分拡大図である。さらに図１３に示す縦ライン１上の電界強度分布曲線を図１４(a)に、図１３に示す縦ライン２上の電界強度分布曲線を図１４(b)に、図１３に示す縦ライン３上の電界強度分布曲線を図１４(c)に。図１３に示す縦ライン４上の電界強度分布曲線を図１４(d)に示した。なお、図１４(a)〜(d)中に対応する各ライン１〜４上の不純物濃度分布曲線を併せて示した。
【００４０】
図１１の等電界曲線によって示されるように、ＪＢＳモデル、ＳＢＤモデルともにガードリング５の外端コーナー部（ガードリング５内）に最大電界強度が生じ、その値は約３E５（V／ｃｍ）となった。その他、ガードリング５の内端コーナー部（ガードリング５内）に極大値が生じた。さらにＪＢＳモデルにおいてはP型活性領域４の下端部（P型活性領域４内）に極大値が生じた。
ＪＢＳモデルにおいてP型活性領域４の下端部の極大値は、ガードリング５の内端コーナー部の極大値より高い値となった。P型活性領域４の下端部の極大値は、より内側（素子中央側）のP型活性領域４の方が低い値となった。また、ＳＢＤモデルにおけるガードリング５の内端コーナー部の極大値よりＪＢＳモデルにおける同値の方が低くなった。
【００４１】
さらに図１５の表に図１３に示した縦ライン１〜４上の最大電界値及びガードリング５の外端コーナー部の最大電界値をＳＢＤモデルとＪＢＳモデルのそれぞれについて示し、さらに同表にＪＢＳモデルの電界値を対応する箇所のＳＢＤモデルの電界値で割ったもの（ＪＢＳ／ＳＢＤ電界比）、及びＪＢＳモデルの電界値から対応する箇所のＳＢＤモデルの電界値を引いたもの（ΔＥ）を示した。
図１５の表のライン３におけるＪＢＳ／ＳＢＤ電界比に示すように、２つのＰ型活性領域４,４間の領域に生じる最大電界強度をEjbsとし、Ｓp＝０とした場合のショットキー接合に生じる電界強度をEsbdとするとき、Ejbs≦０．８６×Esbdの関係を満たす。かかる電界強度の低下効果は、Ｓp／Ｓの値を高める、すなわち、Ｐ型活性領域４の面積占有率を高めるほど高まる。
【００４２】
〔本実験１〕
本実験１は、電子線照射量ΦEIの変化に対するJBSデバイス特性変化の測定である。
（条件）
試料ＪＢＳ１〜４において、半導体層２の比抵抗ρ＝6.5Ω・ｃｍ，厚さｄl＝23μｍとした。Ｓn／Ｓ比は42％とした。Ｐ型活性領域４の深さＸjp＝６μｍとした。電子線照射量ΦEIは0，200，300，400KGyと変化させた。
比較用試料（ＦＲＤ）として、ρ＝5.7Ω・ｃｍ，厚さ28μｍのＰＮ接合ダイオード（Ｓn／Ｓ比＝100％）を用いた。比較用試料の接合深さＸjp＝６μｍとした。
以上の試料（ＪＢＳ１〜４，ＦＲＤ）について測定するデバイス特性は、順方向電圧降下ＶF（ＩF＝0.1A， 1.0A，5.0A，10A，20A／25℃，100℃），逆方向電圧ＶR（200μA），逆回復時間ｔrr（25℃，100℃），逆方向リーク電流ＩR（25℃，100℃）である。各試料４０ケについて測定し平均値を算出して以下の結果を得た。
【００４３】
（結果）
図１６の表(a1)に、温度２５℃・各順方向電流IFにおいて異なる電子線照射量ΦEIに対する順方向電圧降下ＶFの実測結果を示す。同条件の比較用試料ＦＲＤのＶF特性を図１６の表(a2)示す。
図１６の表(b1)に、温度１００℃・各順方向電流ＩFにおいて異なる電子線照射量ΦEIに対する順方向電圧降下ＶFの実測結果を示す。同条件の比較用試料ＦＲＤのＶF特性を図１６の表(b2)示す。
図１７に、図１６(a1)(b1)の表をグラフ化したΦEI−ＶFの関係を表すグラフを示した。図１８(a)に、図１６(a1)(a2)の表をグラフ化したＩF−ＶFの関係を表すグラフを示した。図１８(b)に、図１６(b1)(b2)の表をグラフ化したＩF−ＶFの関係を表すグラフを示した。
【００４４】
図１９(a1)(a2)の表にその他の特性（ＶR（at ＩR＝200μＡ），ｔrr（at ＩF＝5Ａ，２５℃），ｔrr（at ＩF＝5Ａ，１００℃），ＩR（at ＶR＝１８０Ｖ，２５℃），ＩR（at ＶR＝200Ｖ，１００℃）の測定結果を示した。
図１９(b)に、図１９(a1)(a2)の表に基づきグラフ化したΦEI−ＶRの関係を表すグラフを示した。
図２０(a)に、図１９(a1)(a2)の表に基づきグラフ化したΦEI−ｔrrの関係表すグラフを示した。
図２０(b)に、図１９(a1)(a2)の表に基づきグラフ化したΦEI−ＩRの関係を表すグラフを示した。
図２１(a1)(a2)に、２５℃におけるＶF−ｔrrのトレードオフ特性を示す表及びグラフを示した。
図２１(b1)(b2)に、１００℃におけるＶF−ｔrrのトレードオフ特性を示す表及びグラフを示した。
【００４５】
〔本実験２〕
本実験２は、アニール条件検証のための実験である。電子線照射量ΦEI及びアニール条件（温度と時間）を変えたときの順方向電圧降下ＶFと逆回復時間ｔrrを測定した。
（条件）
試料Ｓ−(1)〜Ｓ−(17)において、半導体層２の比抵抗ρ＝5.0Ω・ｃｍ、厚さｄl＝19，21μｍの２水準を採用した。
前酸化の有無、照射量ΦEI、アニール温度、アニール時間を、図２２(a)の表、図２２(b)の表に示したように条件を割り振る。かかる条件で順方向電圧降下ＶF（at 1A,5A,20A）と逆回復時間ｔrr（２５℃, １００℃）を測定した。各試料２０ケについて測定し平均値を算出して以下の結果を得た。
【００４６】
（結果）
図２２(a)の表に、厚さｄl＝19μｍの試料におけるＶF特性の測定結果を示した。図２２(b)の表に、厚さｄl＝21μｍの試料におけるＶF特性の測定結果を示した。
図２３(a)に、図２２(a)の表に基づきグラフ化したものを示した。図２３(b)に、図２２(b) の表に基づきグラフ化したものを示した。
図２４(a)の表に、厚さｄl＝19μｍの試料におけるｔrr特性の測定結果を示した。図２４(b)の表に、厚さｄl＝21μｍの試料におけるｔrr特性の測定結果を示した。図２５(a)に、図２４(a)の表に基づきグラフ化したものを示した。図２５(b)に、図２４(b) の表に基づきグラフ化したものを示した。
【００４７】
〔本実験３〕
本実験３おいては、異なる電子線照射量ΦEIに対する逆方向電圧ＶR、順方向電圧降下ＶF、逆回復時間ｔrr、逆方向リーク電流ＩRを測定した。また、ＩＦＳＭ サージ試験、B／P（バック・パワー）耐量試験及びＥＳＤ耐量試験も行う。
（条件）
試料ＪＢＳ１A▲１▼〜▲４▼として、半導体層２の比抵抗ρ＝5.0Ω・ｃｍ、厚さｄl＝19，21μｍの２水準を採用した。比較用試料の接合深さＸjp＝６μｍとした。
比較用試料（ＦＲＤ１Ａ）として、半導体層２の比抵抗ρ＝5.0Ω・ｃｍ、厚さｄl＝19，21μｍのＰＮ接合ダイオード（Ｓn／Ｓ比＝０％）を用いた。比較用試料の接合深さＸjp＝６μｍとした。
異なる電子線照射量ΦEI（0，200，300，400KGy）に対するＶR（25℃），ＶF（25℃，100℃），ｔrr（25℃，100℃），ＩＦＳＭ，B／P，ＥＳＤ，ＩR（25℃，100℃）の各特性を測定する。各試料２０ケについて測定し平均値を算出して以下の結果を得た。
【００４８】
（結果）
図２６(a)(b)の表に、厚さｄl＝21μｍの試料において異なる電子線照射量ΦEIに対するＶR（25℃），ＶF（25℃，100℃），ｔrr（25℃，100℃），ＩＳＦＭ，B／P（バック・パワー）耐量，ＥＳＤ耐量，ＩR（25℃，100℃）の測定結果を示した。これらの測定結果をグラフ化したものを図２７(a)(b)(c)(d)及び図２８(a)(b)(c)に示した。
図２９(a)(b)の表に、厚さｄl＝19μｍの試料において異なる電子線照射量ΦEIに対するＶR（25℃），ＶF（25℃，100℃），ｔrr（25℃，100℃），ＩＳＦＭ，B／P（バック・パワー）耐量，ＥＳＤ耐量，ＩR（25℃，100℃）の測定結果を示した。なお、これらの測定結果をグラフ化したものは掲載していない。
【００４９】
次に、ＪＢＳと比較用デバイスのスイッチ特性（ＯＮ→ＯＦＦ特性）波形を対比して開示する。
図３０(a)に、２５℃におけるＪＢＳ（ρ＝5.0Ω・ｃｍ，ｄｌ＝ 19μｍ）と比較用デバイスとしてＳＢＤ，ＦＲＤ（ρ＝5.0Ω・ｃｍ，ｄｌ＝ 19μｍ）のＯＮ→ＯＦＦ時の電流の変化を表す波形図を示した。
図３０(b)に、１００℃におけるＪＢＳ（ρ＝5.0Ω・ｃｍ，ｄｌ＝ 19μｍ）と比較用デバイスとしてＳＢＤ，ＦＲＤ（ρ＝5.0Ω・ｃｍ，ｄｌ＝ 19μｍ）ののＯＮ→ＯＦＦ時の電流の変化を表す波形図を示した。
【００５０】
〔本実験４〕
本実験４は、異なる電子線照射量ΦEIに対する逆方向電圧ＶR、順方向電圧降下ＶF、逆回復時間ｔrr、逆方向リーク電流ＩRを測定する。
（条件）
６種の試料ＪＢＳ５Ａ(1)〜(6)を用意した。また、２種の比較用試料ＦＲＤ５Ａ(1)，(2)を用意した。
本発明の試料のうち、ＪＢＳ５Ａ(1)〜(4)は、半導体層２の比抵抗ρ＝8.5Ω・ｃｍ，厚さｄl＝29μｍとするものを用い、電子線照射量ΦEI＝0，40，100，300 KGyとした。
本発明の試料ＪＢＳ５Ａ(5)は、半導体層２の比抵抗ρ＝8.3Ω・ｃｍ，厚さｄl＝27.7μｍのもので、電子線照射量ΦEI＝400 KGyとした。
本発明の試料ＪＢＳ５Ａ(6)は、半導体層２の比抵抗ρ＝10Ω・ｃｍ，厚さｄl＝33μのもので、電子線照射量ΦEI＝0 KGyとした。
比較用試料ＦＲＤ５Ａ(1)は、半導体層２の比抵抗ρ＝9.0Ω・ｃｍ，厚さｄl＝29μｍのものを、比較用試料ＦＲＤ５Ａ(2)は、半導体層２の比抵抗比抵抗ρ＝8.3Ω・ｃｍ，厚さｄl＝27.7μｍのものを用いた。
以上の試料について測定するデバイス特性は、ＶR（25℃），ＶF（25℃，100℃），ｔrr（25℃，100℃），ＩR（25℃，100℃）である。各試料２０ケについて測定し平均値を算出して以下の結果を得た。
【００５１】
（結果）
図３１(a)(b)の表に、各試料における逆方向電圧ＶR、順方向電圧降下ＶF、逆回復時間ｔrr、逆方向リーク電流ＩRの測定結果を示す。図３１(a)(b)の表に基づきグラフ化したものを、図３２(a)〜(f)に示した。
【００５２】
〔検証〕
次に以上の実験及びシミュレーションの結果を元に本発明の技術的効果を検証する。
（１）Ｓn／Ｓ比とＶF特性、ＩR特性及びＶR特性
予備実験１及び２の結果から以下のことがわかる。
Ｓn／Ｓ比の増加に従ってＶFが増加する、すなわち、ＶF特性が低下する傾向にある。
また、Ｓn／Ｓ比の増加に従ってＩRが増加する、すなわち、ＩR特性が低下する傾向にある。
また、Ｓn／Ｓ比の増加に従ってＶRが減少する、すなわち、ＶR特性が低下する傾向にある。
したがって、Ｓn／Ｓ比を下げることが、優れたＶF特性、ＩR特性及びＶR特性を得る上で好ましい。
しかし、Ｓn／Ｓ比を４０未満に下げることは、P型活性領域４を分散して形成することを困難にする。また、Ｓn／Ｓ比を下げると、図３０に示したようにスイッチ時のノイズ特性が低下する。
したがって、Ｓn／Ｓ≧４０％とすることが好ましい。
また、図６(c)及び図７(c)に示すように、Ｓn／Ｓ比が８０％前後である範囲においてＶR特性の底となるから、４０％≦Ｓn／Ｓ≦７０％とすることがより好ましく、４０％≦Ｓn／Ｓ≦７０％とすることがより低ノイズで逆回復時間の短いスイッチ特性が得られる。
【００５３】
（２）電子線照射量ΦEI
[予備実験１＆２]および[本実験１，２，３，４]の結果を踏まえて、次のような形式で表現する上記式１を定義することができた。
【００５４】
式１の全体のフォームは、放射線の打ち込み量（注入量）と被照射素材中のライフタイムとの関係を記述する公知の式
Δ（１／τ）＝（１／τs）-（１／τo）＝ＫΦ
より引用している[Ref．放射線と産業 Ｎｏ．６４（１９９４），pp.14〜18 望月康弘氏]。
上式を照射量Φに関して変形し、式１とした。
ここで、τs，τo→ｔrrs，ｔrroとしたのは、ｔrrが素子中（N^-層での正孔）のライフタイムと深く関係することからである。
また、上記式１中の[ ]内は、τ→ｔrrへの、また、実験結果を数式化する上での補正項全体である。
【００５５】
[ ]内の第１項 ln（ＩF×Cl）／ln（Cl）は、素子の面積補正と定義される補正部である。本発明ではデバイスとしては１A型、５A型の２種類を用いたために、その定格電流IFをもって代表記述することとした。これ以外にも、ある電流密度（J≒１６５A／ｃｍ²）を設計基準にしていれば、実際の素子の活性領域面積比、あるいはチップサイズ面積比等で記述してもよい。
この場合は、１A型素子に対する５A型素子のｔrr増大比を定格電流比で表したという一例にすぎない。あとはClの値や、ln型の比例関係にあるか、直線型の比例関係にあるかは、全ての実験結果をうまく記述できるものが真実をより近く表現していると考えればよい。本発明では上記のようにした。
[ ]内の第２項 （ｄl²／Nd²）は、いうまでもなく、種々のρ、ｔの組み合わせが所望のデバイス特性（特にＶR）に対して選ばれたときの補正項を定義しているものである。
【００５６】
その導出根拠は、以下のRef．にある。
[Ref. IEEE, ED, Vol.37, No.5, May 1990, pp.1364~1372 "An Analysis of Positive & Negative Resistance Characteristics In High-Current-Density Region of SBD", by Yamamoto et al.]
すなわち、上記文献中に書かれたＶFを決定する式のうち、特に高電流密度時にＳＢＤ界面からN^-層中にさかんに注入される少数キャリア（正孔電流）に起因する寄生抵抗分（Ｒs）とＩFの積、（Ｒs・ＩF）＝ＶF2部分が、ＩFとともに大きく変わるが、この部分に関係する式を整理すると、ＶF2∝（ｄl²／Nd²）の関係が導かれる。
つまり、ΦEIの増大はＶFの増大を伴う。ＶFは、（ｄl²／Nd²）に比例するとの関係からΦEI∝（ｄl²／Nd²）として補正するものである。
【００５７】
また（ｄl²／Nd²）α項をさらに補正するαは、べき乗補正係数と呼ばれる補正係数である。上記文献中のN^-層中への少数キャリアの注入度を、本発明では（ρ＝５Ω・ｃｍ／ｔ＝21μｍ）素材を基準に考えてきたが、より高耐圧のデバイスでは、この少数キャリア注入が、より起こりやすくなるのを、（ｄl²／Nd²）項のみでは表現しきれず、つまり、ΦEI∝（ｄl／Nd）²の２乗項をさらに（より大きい方向に）微調整し、実験結果データとフィッティングさせたいとの意図がある。
あるρとｔを採れば、（ｄl／Nd）及び（ｄl／Nd）²の値が決まる。そのとき前記の式１中に用いるαの値を、図３３に示した。
αの値は図３４（a）のグラフから、それぞれの（ｄl／Nd）²に相当するαの値を読み取ることで決定できるが、αについても、実験式化しておく。αは、（ｄl²／Nd²）の変化に対し、わずかに上に凸の曲線となるため、完全な１次関係とはならないが、次式２として近似できる。式２中の0.999乗の部分が（１次関係ならば1.000）からのわずかなズレ（上に凸）の度合いを示している。
【００５８】
【数３】

＜検算結果＞
本実験１，３，４のｔrrに関するデータと理論計算式から求めたΦEI_simの値と実験値ΦEIとを比較する。
図３５（a）に、本実験１での実験結果（ｔrr_m）と本実験１の各パラメータを式１に代入して計算したΦEI_simを示す。かかる計算に用いた本実験１の各パラメータは図３５（b）に示す。
ｔrrの実験値（ｔrr_m25℃）での０，２００，３００，４００[KGy]照射時の７０．７ns，５２．０ns，４８．７ns，４４．９nsに相当するΦEIの計算値は、０，２４６，３０９，３９２[KGy]となり、ほぼ近い。（Ｋ＝３８．１の精度）
【００５９】
同様にＴa＝１００℃での（ｔrr_m100℃）各０，２００，３００，４００[KGy]において、式１は０，２５８，３５０，４３８[KGy]とやや高めな値を返してくるが、精度（Ｋ＝２０．１）は、それほど悪くない。
同様に、図３６（a），（b）に、本実験３での実験結果（ｔrr_m）と本実験３の各パラメータを式１に代入して計算した計算結果ΦEI_simを示す。かかる計算に用いた本実験３の各パラメータは図３６（c）に示す。
ｔrr_m25℃の３００，４００[KGy]ともに２６nsであるので、ΦEI_sim 25℃はともに４２３[KGy]を返すが、２００[KGy]での３０nsに対するΦEI_sim 25℃は２３４[KGy]を返してくるので、ほぼＯＫとみる。
ｔrr_m100℃での２００，３００[KGy]ともに同じ値のｔrr_m100℃＝３３nsをフィッティングさせるのは困難をきわめるが、３００[KGy]で３６０[KGy]を返してくるので、ほぼＯＫとみる。
図３６（a）に比べて５Ａ型の図３６（b）は、かなり実験値ΦEIと計算値ΦEI_simとの間のマッチングがとれている。
【００６０】
同じく、本実験４での検算結果を図３７（a）に示す。計算に用いた本実験４の各パラメータを図３７（b）に示す。
この８．５Ω・ｃｍ／29μｍ厚の場合、ΦEI_sim25℃での４０，１００[KGy]に対して返してくる値３７．８[KGy]，１０５[KGy]は相当精度が良い。また、ΦEI_sim100℃での３００[KGy]，４００[KGy]に対して返してくる値ΦEI_ sim100℃は１０５[KGy]，３２２[KGy]となり、かなり精度が良い。
以上より、少ない実験因子・データから求めたわりには式１は種々の（ｄl／Nd）、定格電流、Ｔa＝２５℃／１００℃の差等があっても、ｔrroが既知（電子線照射前の組立後デバイスのｔrrを測ればわかる）であり、所望のｔrrs（例えばＦＲＤのｔrr（既知）の１．５倍程度）を決定し入力すれば、そのｔrrを得るために必要な照射量ΦEIをかなりな精度で予測することが可能になる。
【００６１】
＜数式の変換＞
式１を、ｔrroとΦEIからｔrrsを求める式３に変換することができる。
【００６２】
【数４】

〔１〕式１より、ｔrroを知り、所望のｔrrsを入力すれば、ΦEIが求まる。
〔２〕式３より、既知のｔrroとΦEIより、ｔrrsを予測することができる。上記の〔１〕はデバイス設計者にとって便利な数式であり、〔２〕はデバイスの製造者にとって極めて有益な数式表現である。これらをグラフ化する。
本実験１の各パラメータを式３に代入して求めたｔrrsの値を図３８(a)の表及び(b)のグラフに示す。かかる計算に用いた本実験１の各パラメータは図３８（ｃ）に示す。図３８(b)中の○印、×印は、ｔrrの実験値である。
【００６３】
本実験３の各パラメータを式３に代入して求めたｔrrsの値を図３９(a)の表及び(b)のグラフに示す。かかる計算に用いた本実験３の各パラメータは図３９(c)に示す。図３９(b)中の○印、×印は、ｔrrの実験値である。
【００６４】
本実験４の各パラメータを式３に代入して求めたｔrrsの値を図４０(a)の表及び(b)のグラフに示す。かかる計算に用いた本実験４の各パラメータは図４０(c)に示す。図４０(b)中の○印、×印は、ｔrrの実験値である。
【００６５】
続いて、Ｔa＝２５℃での各種本実験において用いられたデバイス（ＪＢＳ構造）の全てのΦEI−ｔrrs特性及びＴa＝１００℃でのΦEI−ｔrrs特性をグラフ化し、比較しやすいように、まとめて示す。
図４１(a)に式３により求めたΦEIとｔrrの関係を示す。図４１(b)にＴa＝２５℃でのΦEI−ｔrrs特性を示す。図４１(c)にＴa＝１００℃でのΦEI−ｔrrs特性を示す。
【００６６】
以上により、従来にはない耐圧領域において、ＪＢＳ構造が優位であること、また、本発明によるＪＢＳ構造において、ＪＢＳ構造の高速化には電子線照射が最適であり、かつ不可欠との前提にたち、
(1)[予備実験１＆２]及び[本実験１~４]を通じて、１８０Ｖ型，２８０Ｖ型ＪＢＳ素子の種々の特性を調査した。また、その特性が相互にどう影響しあうかも示した。
(2)シミュレーションにより、本構造のＳＢＤ界面の電界（Ｗn領域）が従来のＳＢＤ構造に比べて、かなり低下する（同一のＶR電圧印加時において）構造であり、かつ適切なρ、ｔを選択しているので、ガードリング部にＥcrit相当の最大電界を発生させる構造となっていることを確認した。
(3)上記(1)の種々の実験結果から得たデータを式１の表現にまとめ、チップサイズ、ρ、ｔ（ｄl，Nd）、Ｔa＝２５℃，１００℃のパラメータ変化に対してｔrroとｔrrsが既知であれば、このｔrrs実現するためにはΦEIをどの程度照射すれば得られるかを予測することができるようになった。
(4)式３においては、式１からの変換を行うことにより、ｔrroとΦEIが既知であれば、最終的にどの程度のｔrrsが得られるかを予測することができるようになった。
(5)上記式１、式３の精度は図３８から図４０中に示したように、かなり実用性の高いレベルの仕上がりになることが明らかである。
(6)本発明のＪＢＳによれば、ＶF（１００℃）特性において、定格電圧電流同等型のＦＲＤのそれを上回ることのないこと、又、ｔrr特性においても、ＦＲＤのそれの１．５倍以内であること、しかも、Soft-Recovery特性を備えた新規構造のデバイスが最適化され、具現化されたと言える。又、電子線なので、ＩR（がΦEI大の時）も悪くない。
そして、その最適化の最も困難を極める部分が、適切なρ、ｔ、Ｘjpの選択を前提としたライフタイムキラー量の決定と予想の工程にあったことは、以上の説明から、より明らかである。
【００６７】
（３）アニール条件
本実験２の結果からわかるように、アニール温度は３００℃以上３５０℃以下の範囲とすることが好ましい。アニール温度は３００℃未満とすると、電子線被照射域のライフタイムキラーの実効性を充分に引き出すことができず、３５０℃を超えると、電子線被照射域が焼き鈍しされてしまいライフタイムキラーの実効性が減殺されてしまう。
アニール時間は２０分以上６０分以下の範囲が良い。より好ましくは３０分以上６０分以下の範囲である。また、上記アニール温度範囲内で比較的低温のアニール温度（例えば、３００℃）を用いるほど、アニール時間を比較的長くとることが好ましい。
【００６８】
【発明の効果】
本発明によれば、ショットキー接合の面積率や電子線照射条件、アニール処理条件等の諸条件が適切に選定され、逆回復時間ｔrrがより短く、順方向電圧降下ＶFがより低く、逆方向リーク電流ＩRが少なく、低ノイズで逆耐圧ＶＲの高いＪＢＳを安価に具現化することができる。
【図面の簡単な説明】
【図１】本発明の一実施形態のＪＢＳを示す断面図（下部）と平面図（上部）である。
【図２】図１においてガードリング５に囲まれる領域内の半導体層２表面の部分拡大図である。
【図３】本発明一実施形態のＪＢＳを製造する主要工程における断面図である。
【図４】本発明一実施形態のＪＢＳを製造する図３に続く主要工程における断面図である。
【図５】予備実験１の測定条件と測定結果を示す表である。
【図６】図５(a)の表に示す測定結果を特性毎にグラフ化したものである。
【図７】図５(b)の表に示す測定結果を特性毎にグラフ化したものである。
【図８】予備実験２の測定条件と測定結果を示す表である。
【図９】図８の表に示す測定結果を特性毎にグラフ化したものである。
【図１０】シミュレーションにより得られた等電位曲線図である。
【図１１】シミュレーションにより得られた等電界強度曲線図である。
【図１２】図１１の部分拡大図である。
【図１３】電界強度分布を測定する縦方向のライン１〜４の位置を特定するための断面図である。
【図１４】図１３に示す縦ライン１〜４上の電界強度分布曲線をそれぞれ示した図である。
【図１５】シミュレーションにより得られた重要値等をまとめた表である。
【図１６】本実験１の測定条件とＶＦ特性の測定結果を示す表である。
【図１７】図１６(a1)(b1)の表をグラフ化したΦEI−ＶFの関係を表すグラフである。
【図１８】 (a)は図１６(a1)(a2)の表をグラフ化したＩF−ＶFの関係を表すグラフである。(b)は図１６(b1)(b2)の表をグラフ化したＩF−ＶFの関係を表すグラフである。
【図１９】 (a)(a2)は本実験１の測定条件とＶＦ特性以外の特性の測定結果を示す表である。（ｂ）は本図(a1)(a2)の表に基づきグラフ化したΦEI−ＶRの関係を表すグラフである。
【図２０】(a)は図１９(a1)(a2)の表に基づきグラフ化したΦEI−ｔrrの関係表すグラフである。(b)は図１９(a1)(a2)の表に基づきグラフ化したΦEI−ＩRの関係を表すグラフである。
【図２１】 (a1)は２５℃におけるＶF−ｔrrのトレードオフ特性を示す表であり、(a2)はそのグラフである。(b1)は１００℃におけるＶF−ｔrrのトレードオフ特性を示す表であり、(b2)はそのグラフである。
【図２２】本実験２の測定条件及び順方向電圧降下ＶF（at 1A,5A,20A）の測定結果を示す表である。
【図２３】 (a)は図２２(a)の表に基づきグラフ化したものものである。(b)は図２２(b) の表に基づきグラフ化したものである。
【図２４】本実験２の測定条件及び逆回復時間ｔrr（２５℃, １００℃）の測定結果を示す表である。
【図２５】 (a)は図２４(a)の表に基づきグラフ化したものである。(b)は図２４(b) の表に基づきグラフ化したものである。
【図２６】本実験３の測定条件及び測定結果を示す表である。
【図２７】図２６の表に掲載の測定結果をグラフ化したものである。
【図２８】図２６の表に掲載の他の測定結果をグラフ化したものである。
【図２９】本実験３の異なる試料に対する測定条件及び測定結果を示す表である。
【図３０】ＪＢＳ（ρ＝5.0Ω・ｃｍ，ｄｌ＝ 19μｍ）と比較用デバイスとしてＳＢＤ，ＦＲＤ（ρ＝5.0Ω・ｃｍ，ｄｌ＝ 19μｍ）のＯＮ→ＯＦＦ時の電流の変化を表す波形図である。(a)は２５℃における波形図であり、(b)は１００℃においる波形図である。
【図３１】本実験４の測定条件及び測定結果を示す表である。
【図３２】図３１(a)(b)の表に基づきグラフ化したものである。
【図３３】式１中に用いるαと比抵抗ρとの関係
【図３４】（ｄl／Nd）²とαとの関係を表すグラフ(a)と表(b)
【図３５】 (a)は、本実験１での実験結果（ｔrr_m）と本実験１の各パラメータを式１に入れて求めたΦEI_simとを比較して示した表である。(b)は、式１に代入した本実験１の各パラメータの値を示す表である。
【図３６】 (a)(b)は、本実験３での実験結果（ｔrr_m）と本実験３の各パラメータを式１に入れて求めたΦEI_simとを比較して示した表である。(c)は、式１に代入した本実験３の各パラメータの値を示す表である。
【図３７】 (a)は、本実験４での実験結果（ｔrr_m）と本実験１の各パラメータを式１に入れて求めたΦEI_simとを比較して示した表である。(b)は、式１に代入した本実験４の各パラメータの値を示す表である。
【図３８】本実験１の各パラメータを式３に代入して求めたｔrrsの値を示す表(a)及びグラフ(b)である。(c)は、かかる計算に用いた本実験１の各パラメータを示す表である。
【図３９】本実験３の各パラメータを式３に代入して求めたｔrrsの値を示す表(a)及びグラフ(b)である。(c)は、かかる計算に用いた本実験３の各パラメータを示す表である。
【図４０】本実験４の各パラメータを式３に代入して求めたｔrrsの値を示す表(a)及びグラフ(b)である。(c)は、かかる計算に用いた本実験４の各パラメータを示す表である。
【図４１】 (a)は、式３により求めたΦEIとｔrrの関係を示す表である。図４１(b)は、Ｔa＝２５℃でのΦEI−ｔrrs特性を示すグラフである。図４１(c)は、Ｔa＝１００℃でのΦEI−ｔrrs特性を示すグラフである。
【図４２】ＳＢＤとＦＲＤの各デバイスの定格電圧（V）とその損失（W）との関係を表した曲線である。
【図４３】ＳＢＤとＦＲＤの各デバイスを、順バイアスから逆バイアスにスイッチした際の逆回復の様子を概略示した電流変化波形である。
【符号の説明】
１…半導体基板 ２…半導体層 ３…N^-型領域 ４…Ｐ型活性領域… ５… …ガードリング ６…チャネルストップ領域 ７…バリアメタル ８…半導体酸化膜… ９…第一電極メタル １０…第二電極メタル １１…等電位リング電極メタル２３b…ＰＳＧ保護膜 ２４…最終絶縁保護膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a Junction Barrier Controlled Schottky (hereinafter referred to as JBS) having a structure in which a Schottky junction and a PN junction coexist, and more specifically, a high-speed / medium current / medium withstand voltage type JBS semiconductor device using a planar structure. The present invention relates to a method for determining an electron beam irradiation condition optimal for reducing the forward voltage drop VF and shortening the reverse recovery time trr (trade-off), and a manufacturing method thereof.
[0002]
BACKGROUND OF THE INVENTION
As a diode used in an application circuit operated at a frequency of several tens to several hundreds KHZ, a Schottky barrier diode (hereinafter referred to as SBD) or an ultra fast recovery diode (hereinafter referred to as FRD) is used. It has been widely used in the past.
As is well known, SBD is a unipolar device that uses a junction between a semiconductor and a metal (usually NBD).^-Therefore, the reverse recovery time is depleted on the semiconductor side because the potential barrier is lower and the forward voltage drop is smaller than that of a PN junction diode. This is only the time required to form the layer, and therefore has a feature such as fast switching.
On the other hand, FRD shortened the reverse recovery time by introducing minority carrier recombination centers (lifetime killer) by adding heavy metals to the PN junction or irradiating with radiation, etc. to shorten the minority carrier lifetime. It has been said that an extremely short reverse recovery time can be achieved by shortening the minority carrier lifetime.
[0003]
However, SBD is advantageous at low voltage for frequency conversion in a high frequency band, but is disadvantageous for high voltage applications because of a large loss of operation. For this reason, FRD is used instead of SBD for high voltage applications, but FRD has a property that loss is increased at low voltage. Such loss is evaluated particularly by the forward voltage drop VF, the reverse leakage current IR, and the reverse recovery time trr.
In FIG. 42, the horizontal axis represents the rated voltage (V) of the device, and the vertical axis represents the loss (W). A curve A shows a tendency of change in loss with respect to a change in rated voltage of SBD, and a curve B shows a tendency of change in loss with change in rated voltage of FRD.
As shown in FIG. 42, below a certain rated voltage, the effect of the low VF characteristics of the SBD is large and the SBD has a lower loss. However, when the rated voltage is exceeded, the SBD also loses the low VF characteristics. Combined with the effects that the reverse leakage current component is originally larger than that of the FRD and the switching speed of the relatively high breakdown voltage SBD is slow, the FRD has a lower loss.
It is known to those skilled in the art that the replacement area of a device that is dominant between SBD and FRD has a rated voltage value of about 150 to 300V. That is, it has been empirically known in the process of device development in the industry that one of SBD and FRD is switched from the superiority of the other in the range of about 150 to 300 V to the other.
One of the reasons is that a stable and high barrier height (φB) barrier metal is indispensable for obtaining a high breakdown voltage SBD, but the SBD inherently possesses an SBD exceeding the 200 V rating. Commercial production as it is is impossible with current technology.
Therefore, in applications where the SBD cannot be manufactured and whose voltage exceeds the rated voltage (200 to 600 V, 1200 V), there is a background that FRD is frequently used.
[0004]
However, in the device replacement region where SBD and FRD are dominant, the superiority of both devices may not be maintained. An example of this will be described with reference to FIG.
FIG. 43 is a current change waveform schematically showing reverse recovery when switching from forward bias to reverse bias. In FIG. 43, the vertical axis represents current, the horizontal axis represents time, waveform A is for a 180 V type SBD, and waveform B is for a 200 V type FRD.
At such a rated voltage, the reverse recovery time trr of SBD, which is originally high speed, becomes relatively long. However, it is clear that the reverse recovery waveform of SBD is quite excellent in softness and low noise.
On the other hand, FRD seems to have no problem because the reverse recovery time trr is short, but since the lifetime killer is effective, the forward voltage drop VF rises and the current during recovery There is a shoot phenomenon, and as a result, after a damped vibration is repeated several times, it settles down and the OFF is completed. In a certain application (parent device), the vibration phenomenon occurring at this time may be a source of noise, which may be undesirable.
As a conclusion of demands demanded by users of SBD and FRD, it is an essential condition that the device has a shorter reverse recovery time (trr), a lower VF, and a lower noise.
[0005]
It is well known in the art that a JBS having a structure in which a Schottky junction and a PN junction coexist can be considered as one of the promising candidates for a device to meet such market demands (needs). For example, [ISPSD'93, pp.199-204, Comparison of High Voltage Power Rectifier Structures, by M. Mehretra & BJBaliga] etc. has been published as a document of JBS structure (although the naming method varies) long.
In addition, there are persistent demands for applications such as FWD (free wheel diode) used in combination with IGBT, and there are various publications in these applications. For example, [ISPSD'01, pp. 307-314, Great Improvement in IGBT Turn-on Characteristics with Trench Oxide Schottky (TOPS) Diode, by M. Nemoto, et al]
The IGBT is generally a large area (and medium / high speed) element of several tens to several hundreds of A type, and the FRD used in combination with the IGBT is also a large area element, but the reverse recovery time trr increases the element area. In consideration of the increase with the above, any of the introduction examples described in the above-mentioned document is an application of about several tens of KHZ at the operating frequency, and therefore the reverse recovery time trr is about 200, which is about one digit higher. It is a medium to high speed device that is as long as ~ 300ns. Furthermore, in the development of FWD for them, the planer structure was the center at first, but recently, the structure of the trench structure has been announced as the ultimate structure. However, while the trench structure is advantageous for miniaturization of the device surface, it involves a complicated manufacturing method and a disadvantage in price.
[0006]
[Problems to be solved by the invention]
However, even with the above idea, an ultrafast device that still covers the above-mentioned 150 to 300V rated voltage range, that is, a power MOSFET that has a reverse recovery time trr within several tens of ns and is operated at a higher frequency than the IGBT. Devices that can meet the demands of higher-speed circuits that are used in combination with the above-mentioned devices, have excellent VF characteristics and noise characteristics, and are inexpensive and have not appeared on the market. I'm waiting.
That is, a technique for realizing a JBS with a shorter reverse recovery time (trr), lower VF, and lower noise is desired.
First of all, it is necessary to fully grasp the shortcomings of current devices, and to find out concrete means for improving and overcoming them. In particular, it is the handling of the lifetime killer that is expected to be difficult in the development of such ultra-high-speed devices.
[0007]
As is well known, there are various methods for shortening the lifetime of the device, and the representatives are the following three methods.
I. Heavy metal (gold or platinum) N^-A method to reduce the lifetime by diffusing in the mold substrate.
The inventors of the present application have studied this technique. However, since the JBS structure is a structure in which both the PN junction and the SBD junction coexist, the above heavy metal diffusion inevitably involves a high temperature treatment of about 800 to 950 ° C. For this reason, first, a PN junction which is the highest temperature heat treatment (1000 to 1200 ° C.) is formed, then heavy metal diffusion is performed, and then an SBD junction is formed (300 to 500 ° C.). . However, the N when forming the SBD junction after heavy metal diffusion^-There is a problem that it is difficult to ensure the cleanliness of the mold substrate surface.
Unless this problem is basically solved, the present inventors abandoned this technique because a JBS structure that meets the above-mentioned requirements cannot be obtained.
[0008]
II. Proton (H⁺) Or helium (He⁺) A method of irradiating light ions.
It is well known that these are widely used for certain types of devices, for example, IGBTs themselves, and devices such as relatively medium-to-high speed FWDs used in combination with the above-described IGBTs.
However, this approach is suitable for local lifetime control (ie, controlling only the part that you want to work, and maintaining sufficient electrical conductivity without controlling the other part). On the other hand, it seems that it is basically difficult to obtain the reverse recovery time trr for ultra-high-speed devices, that is, the reverse recovery time trr is further reduced from a certain point no matter how much the irradiation amount is increased. In addition, there is a limit that can not be achieved, and in addition, since irradiation is usually performed from the backside of the wafer, if the wafer thickness varies, the nature of local distribution is strong, so if you want to achieve the desired lifetime killer distribution Then, there is a problem that the half width at the time of irradiation is shifted by the variation of the thickness of the wafer and it is difficult to obtain a desired lifetime killer distribution.
For example, when the epitaxial layer laminated on the wafer has a thickness of 20 to 30 μm, the variation in the thickness of the wafer plate is larger. For example, when the wafer plate thickness is shifted to the thicker side, the half-value width is within the epitaxial layer. There may even be a center in the wafer that deviates from the desired lifetime killer distribution.
The present inventors originally made it difficult to achieve a sufficiently short reverse recovery time trr for ultra-high-speed devices, and eliminated the thickness variation of the purchased wafer (within 10% in the normal specification). This technique was also abandoned from the conclusion that this would be extremely difficult unless added in a special polishing step.
[0009]
III. A method using electron beam irradiation.
This method is well known to be widely used in the IGBT manufacturing process, but has the greatest advantage that the lifetime can be shortened after an SBD junction that is indispensable for the JBS structure is formed.
However, it is feared that it is difficult to achieve a sufficiently short reverse recovery time trr for an ultrahigh-speed device, and it is important to appropriately set annealing conditions suitable for electron beam irradiation conditions.
[0010]
The present invention has been made in view of the above problems in the prior art, and various conditions such as the area ratio of the Schottky junction, electron beam irradiation conditions, annealing treatment conditions, etc. are appropriately selected, and the reverse recovery time trr is further increased. It is an object to realize a low-noise JBS with a low reverse voltage VR, a low forward voltage drop VF, a low reverse leakage current IR, and a low reverse voltage VR.
[0011]
[Means for Solving the Problems]
  The invention according to claim 1 for solving the above-described problem is, for example, as shown in FIG. 1, using the same mask, the second conductivity type is the opposite conductivity type to the surface of the first conductivity type semiconductor material. By selectively introducing the impurities, a second conductivity type guard ring and a plurality of second conductivity type active regions surrounded by the guard ring are formed,
Each of the patterns in which the second conductivity type active regions are exposed on the surface of the semiconductor material has a circular shape, and one second conductivity type active region (excluding those arranged on the outermost periphery). There are a total of six other second conductivity type active regions closest to each other, and the center of the other second conductivity type active region is arranged at each vertex of a regular hexagon centering on the center of the one second conductivity type active region. Pattern,
A barrier metal that adheres to the second conductive type active region exposed on the surface of the semiconductor material and the first conductive type region adjacent to the second conductive type active region exposed on the surface of the semiconductor material in a region surrounded by the guard ring is laid on the surface of the semiconductor material. And
An insulating film having an opening that opens on a region surrounded by the guard ring, and laid on the surface of the semiconductor material;
A first electrode connected to the barrier metal and the guard ring through the opening;
In the semiconductor device comprising the second electrode on the first conductivity type region side,
(1) When the area of the region surrounded by the guard ring is S, the area of the second conductivity type active region is Sp, and the area of the first conductivity type region is Sn (S = Sp + Sn), Sn / S ≧ 40% of the relationship is satisfied,
(2) The maximum electric field intensity Emax is generated at the outer end corner portion of the guard ring, and Emax ≦ 3.0 × 10 when a reverse voltage is applied.^Five(V / cm) having an impurity concentration (Nd) and thickness (dl) of the semiconductor material and a depth (Xjp) of the second conductivity type active region,
(3) A maximum value of the electric field strength higher than the maximum value of the electric field strength generated at the inner end corner portion of the guard ring is generated at the lower end portion of the second conductivity type active region, and the lower end portion of the second conductivity type active region The maximum value of the electric field strength generated in the second conductive type active region on the inner side is lower, and the maximum electric field strength Ejbs generated in the region between the two second conductive type active regions is lower than that of the semiconductor material. It has a value of Sp / S that satisfies the relationship of Ejbs ≦ 0.86 × Esbd with respect to the electric field strength Esbd generated at a position deeper than the surface and generated at the Schottky junction when Sp = 0.
(4) The Schottky barrier height φBN for the first conductivity type region of the barrier metal is φBN ≧ 0.68 eV,
(5) A semiconductor device in which a lifetime killer is introduced into the semiconductor material by electron beam irradiation.In the semiconductor device manufacturing method, when the impurity concentration of the semiconductor material is Nd, the specific resistance is ρ, and the thickness is dl,
Substituting the desired trrs value into Equation 1, obtaining the dose ΦEI that satisfies Equation 1 with the desired trrs value substituted, and irradiating the electron beam with the obtained dose ΦEI, the temperature is 300 ° C. or higher and 350 ° C. or lower. A method of manufacturing a semiconductor device, wherein a lifetime killer is introduced into the semiconductor material by performing an annealing process in a temperature range of 30 minutes to 60 minutes.
[Expression 2]

[0012]
As the semiconductor material of the first conductivity type, N⁺Mold or P⁺N stacked on type semiconductor substrate^-A type semiconductor layer and an N type single crystal substrate are preferably used, but a P type may also be used. It is sufficient that the second electrode on the first conductivity type region side is provided on the back surface of these semiconductor substrates.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following is one embodiment of the present invention and does not limit the present invention.
First, the structure of the present JBS will be described with reference to FIG. FIG. 1 is a cross-sectional view (lower part) and a plan view (upper part) showing a JBS according to an embodiment of the present invention. In the present embodiment, the P-type active region 4 corresponds to the second conductivity type active region, and N^-The mold region 3 corresponds to the first conductivity type region.
[0016]
As shown in FIG.⁺Type semiconductor substrate 1 and N on the semiconductor substrate 1^-And a semiconductor layer 2 formed by epitaxial growth in a mold.
In the central portion of the surface layer of the semiconductor layer 2, a large number of P-type active regions 4 having a circular shape when viewed from the surface are formed at equal intervals by introducing impurities, and a P-type guard ring 5 is formed so as to surround them. N on the outermost periphery of the surface layer of the semiconductor layer 2⁺Mold or P⁺A type channel stop region 6 is formed by introducing impurities with a gap from the guard ring 5. The remaining part of the semiconductor layer 2 is N^-This is the mold region 3.
[0017]
The JBS further includes a barrier metal 7 laid on the surface of the semiconductor layer 2, a semiconductor oxide film 8, and a PSG (phosphorus / silicic acid / glass) protective film 23b.
The barrier metal 7 covers the inner periphery of the guard ring 5 and the entire region surrounded by the guard ring 5. Therefore, the exposed surface of the P-type active region 4 exposed on the surface of the semiconductor layer 2 in the region surrounded by the guard ring 5 and N^-The exposed surface of the mold region 3 is covered with a barrier metal 7. P-type active region 4 and N^-A PN junction is formed by the mold region 3 and N^-A Schottky junction is formed by the mold region 3 and the barrier metal 7.
N which is the first conductivity type region of the barrier metal 7^-The Schottky barrier height (φBN) for the mold region 3 is φBN ≧ 0.68 eV. Examples of combinations of semiconductors and metals that satisfy such conditions are listed with the φBN values in each combination shown in parentheses. For example, for Si (n-type), Ag (φBN = 0.78 eV), Al (φBN = 0.72 eV), Au (φBN = 0.80 eV), Mo (φBN = 0.68 eV), Pd (φBN = 0.81 eV) , Pt (φBN = 0.90 eV). For GaAs (n-type), Ag (φBN = 0.88 eV), Al (φBN = 0.80 eV), Au (φBN = 0.90 eV), Cu (φBN = 0.82 eV), Hf (φBN = 0.72 eV), Pt (ΦBN = 0.84 eV), Ta (φBN = 0.85 eV), W (φBN = 0.80 eV). For GaAs (p-type), Hf (φBN = 0.68 eV).
The semiconductor oxide film 8 is exposed between the outer periphery of the guard ring 5 and the inner periphery of the channel stop region 6 and between the guard ring 5 and the channel stop region 6.^-The exposed surface of the mold area 3 is covered.
The PSG protective film 23 b is laid on the semiconductor oxide film 8.
[0018]
The JBS further includes a first electrode metal 9, a second electrode metal 10, an equipotential-ring electrode metal 11, and a final insulating protective film 24. In this JBS, the first electrode metal 9 is an anode electrode, and the second electrode metal 10 is a cathode electrode, and this JBS forms a diode having these two electrodes as terminals.
The first electrode metal 9 is bonded to the guard ring 5 and the barrier metal 7 through the opening of the semiconductor oxide film 8.
N^-A second electrode metal 10 that is an electrode on the mold region 3 side is attached to the back surface of the semiconductor substrate 1.
The equipotential ring electrode metal 11 is held at the same potential as the second electrode metal 10 and is connected to the channel stop region 6 through the outer peripheral opening of the semiconductor oxide film 8.
The first electrode metal 9, the second electrode metal 10, and the equipotential ring electrode metal 11 can be made of aluminum or the like.
The final insulating protective film 24 is laid in a ring shape in the peripheral region of the element, covers the edge of the first electrode metal 9 and the equipotential ring electrode metal 11, and protects it from an electrical / mechanical load. As the final insulating protective film 24, silicon nitride or a PSG film can be used.
[0019]
As shown in FIG. 1, this JBS is manufactured by planar technology, and the lower end edges of the P-type active region 4 and the guard ring 5 are rounded to form a curved surface joint. In particular, this JBS is configured such that the maximum electric field is generated at the outer end corner portion 12 which is the outer peripheral edge of the lower end of the guard ring 5. As a result, when a high voltage is applied, high energy is applied to the element peripheral portion where the guard ring 5 is formed, and durability is achieved. By forming the guard ring 5 in this way and forming the maximum electric field in the guard ring 5, a high breakdown voltage JBS can be obtained.
[0020]
Next, the Schottky junction area ratio Sn / S of this JBS will be described with reference to FIG. In this JBS, the area of the region surrounded by the guard ring 5 is S, the area of the P-type active region 4 which is the second conductivity type active region is Sp, and N is the first conductivity type region.^-When the area of the mold region 3 is Sn (S = Sp + Sn), the relationship of Sn / S ≧ 40% is satisfied. FIG. 2 is a partially enlarged view of the surface of the semiconductor layer 2 in a region surrounded by the guard ring 5 in FIG.
[0021]
As shown in FIG. 2A, a P-type active region 4 is exposed in a circular shape on the surface of the semiconductor layer 2, and N is formed around the P-type active region 4.^-The mold area 3 is exposed.
Six P-type active regions 4b are formed in a dot pattern arranged at equal intervals adjacent to the periphery of one arbitrary P-type active region 4a (excluding the outermost periphery). Connecting the centers of the six P-type active regions 4b forms a regular hexagon. The center of one P-type active region 4a coincides with the center of this regular hexagon. Note that a striped pattern may be used.
[0022]
A regular hexagon can be divided into six regular triangles. Now, let us consider one equilateral triangle as shown in FIG. The entire region surrounded by the guard ring 5 is formed in a repetitive pattern with the equilateral triangle shown in FIG. 2B as a unit. Therefore, Sp / S and Sn / S in the equilateral triangle shown in FIG. 2B can be adopted as Sp / S and Sn / S of the entire region surrounded by the guard ring 5. When the length of one side of the equilateral triangle is a and the distance between two adjacent P-type active regions (circular dots) 4 is b (= Wn), Sp / S and Sn / S are respectively It is expressed by a formula.
Sp / S = π (a-b)²/ {2√3 · a²}, Sn / S = 1-π (a-b)²/ {2√3 · a²}
[0023]
For example, a = 15 μm and b = 3 μm can be given as numerical values satisfying the relationship of Sn / S ≧ 40%. In this case, if calculated by substituting into the above equation, Sp / S = about 58% and Sn / S = about 42%. In this case, the diameter of the P-type active region (circular dot) 4 is 12 μm in (a−b). When the depth Xjp of the P-type active region (circular dot) 4 is set to 6 μm, for example, the diameter of the P-type active region (circular dot) 4 is set to 12 μm by (a−b). It can be formed by setting the width of the opening of the mask to be formed to about 2 μm. This is obtained by Wp−0.8 × 2 × Xjp, where Wp is the width of formation of the single P-type active region 4 (diameter in this embodiment) and Xjp is the depth of the P-type active region 4. It is done.
[0024]
In order to improve the forward voltage drop VF, the reverse leakage current IR, and the breakdown voltage, the Schottky junction area Sn should be small, but it should be less than 40%, that is, the P-type active region 4 should be 60% or more. In this case, it is difficult to form the P-type active region 4 in a dispersed manner. Further, N formed between two adjacent P-type active regions 4^-When the formation width of the mold region 3 is Wn, by satisfying the relationship of Wn ≧ 1 μm, the P-type activation can be easily performed without causing inconvenience such as two P-type active regions 4 being continuous due to the formation error. The regions 4 can be formed in a dispersed manner.
[0025]
Next, main manufacturing steps of the present JBS will be described with reference to FIGS. 3 and 4 are cross-sectional views in the main process for manufacturing the JBS of one embodiment of the present invention.
[0026]
First, as shown in FIG.⁺N epitaxially grown on a type semiconductor substrate 1^-The wafer having the semiconductor layer 2 of the mold is oxidized, and semiconductor oxide films 21a and 22 are formed on the front and back sides thereof. For example, silicon is used for the semiconductor substrate 1 and the semiconductor layer 2. In this case, for example, a silicon oxide film of about 0.5 μm is formed as the semiconductor oxide films 21a and 22 by a wet oxidation method at 1000 ° C. for 90 minutes.
[0027]
Next, as shown in FIG. 3B, the semiconductor oxide film 21a on the surface of the semiconductor layer 2 is opened using a well-known lithography / etching technique to form an oxide film mask pattern 21b. Further, a P-type impurity is introduced into the semiconductor layer 2 using the oxide film mask pattern 21b as a mask. For example, boron is ion-implanted. After introducing the P-type impurity, thermal diffusion is performed to activate the P-type impurity. Thereby, the P-type active region 4 and the guard ring 5 are formed. At this time, in order to obtain the pattern shown in FIG. 2, the opening width K1 for forming the P-type active region 4 is set to 2 μm, the interval K2 between adjacent openings is set to 13 μm, and the depth of the P-type active region 4 is obtained. P-type impurities are implanted so that (Xjp) is about 6 μm. As a result, the P-type impurity also proceeds in the lateral direction, and the P-type active region 4 having a width of 12 μm is formed with an interval K3 of 3 μm.
The width of the opening for forming the guard ring 5 is, for example, 30 μm, thereby forming the guard ring 5 having a width of about 40 μm.
[0028]
As shown in FIG. 3C, in the thermal diffusion process after introducing the P-type impurity, the wafer surface including the opening of the semiconductor oxide film 21b is oxidized to form a new semiconductor oxide film 21c.
The peripheral portions of the semiconductor oxide film 21b and the semiconductor oxide film 21c are etched and opened using a well-known photolithography technique. N through the opening thus opened⁺Type impurities, N⁺A type channel stop layer 6 is formed. For example, phosphorus is ion-implanted. The depth Xjn + is, for example, 1.2 to 1.3 μm. N⁺After the introduction of type impurities, N⁺Activate type impurities.
[0029]
Next, as shown in FIG. 4D, a PSG (phosphorus / silicate / glass) film 23a is formed. The semiconductor oxide films 21b and 21c shown in FIG. 3 (3) are collectively shown in FIG. 4 (4) as a semiconductor oxide film 21d.
[0030]
Next, the PSG film 23a and the semiconductor oxide film 21d are opened by using a well-known lithography / etching / metal film forming technique to form the PSG film 23b and the semiconductor oxide film 8 as shown in FIG. As shown in FIG. 4 (5), the barrier metal 7 described above through the openings of the PSG film 23b and the semiconductor oxide film 8 is connected to the guard ring 5, the P-type active region 4, and the N therebetween.^-Formed on the mold region 3. As shown in FIG. 4 (5), the barrier metal 7 may be laid not only on the entire opening of the PSG film 23 b and the semiconductor oxide film 8 but also on the inner periphery of the PSG film 23 b and the semiconductor oxide film 8. However, the barrier metal 7 may be formed in a range slightly smaller than the opening except for the periphery of the opening of the PSG film 23b and the semiconductor oxide film 8.
[0031]
Thereafter, the above-described first electrode metal 9 and equipotential ring electrode metal 11 are formed by using a known lithography / etching / metal film forming technique. As shown in FIG. 4 (5), the barrier metal 7 is completely covered with the first electrode metal 9 described above.
The semiconductor oxide film 8 remaining after the above steps corresponds to the semiconductor oxide film 8 shown in FIG. Note that a PSG film 23 b is formed on the semiconductor oxide film 8.
On the other hand, the back surface of the wafer is ground. Thereby, the semiconductor oxide film 22 on the back surface is removed.
[0032]
Thereafter, the second electrode metal 10 described above is formed on the back surface of the wafer as shown in FIG.
Further, as shown in FIG. 4 (6), a final insulating protective film 24 is formed in the peripheral region. The central first electrode metal 9 is exposed. As the final insulating protective film 24, silicon nitride or a PSG film can be used.
[0033]
  The device formed as described above is irradiated with an electron beam for introducing a lifetime killer, and then annealed. Although it is sufficient to irradiate the electron beam from the front surface side, the inventors of the present application have confirmed by experiment that there is no great difference in the result even when the electron beam is irradiated from the back surface side.
  Lifetime killerΦEI is a value satisfying the expression 1 for the electron beam irradiation amount for introducing. The annealing temperature is 300 to 350 ° C.
[0034]
Further, the maximum electric field strength Emax is a guard ring in the impurity concentration (Nd) and thickness (dl) of the semiconductor layer 2 which is a semiconductor material and the depth (Xjp) of the P-type active region 4 which is the second conductivity type active region. 5 and Emax ≦ 3.0 × 10 when reverse voltage is applied^FiveIt determines so that it may become below (V / cm).
Further, when the maximum electric field strength generated in the region between the two P-type active regions 4 and 4 is Ejbs and the electric field strength generated in the Schottky junction when Sp = 0 is Esbd, Ejbs ≦ 0.86 × Esbd The Sp / S ratio is determined so as to satisfy the relationship.
[0035]
【Example】
Next, preliminary experiments 1 and 2, simulations, and main experiments 1 to 4 performed for the configuration and comparative example corresponding to the above embodiment are disclosed.
First, common items of experimental samples in preliminary experiments 1 and 2 and main experiments 1 to 4 will be described. These experimental samples and calculation target structures follow the structure shown in FIG. 1 of the above embodiment. Conditions that are not specified in the above embodiment are further described.
The semiconductor substrate 1 and the semiconductor layer 2 were made of silicon, and the semiconductor oxide film 8 was made of a silicon oxide film. The semiconductor layer 2 is an epitaxial layer formed by an epitaxial growth method. Boron was used as the P-type impurity and phosphorus was used as the N-type impurity.
As the barrier metal 7, a palladium metal was used.
The first electrode metal 9, the second electrode metal 10, and the potential ring electrode metal 11 are made of aluminum as a main component.
The thickness of the semiconductor substrate 1 was 280 to 285 μm.
The width of the guard ring 5 was 40 μm.
N⁺The type channel stop layer 6 was formed by ion implantation of phosphorus, and the depth Xjn + was set to 1.2 to 1.3 μm.
[0036]
[Preliminary experiment 1]
Preliminary experiment 1 is a measurement of device characteristics for different Sn / S ratios. The table of FIG. 5 shows the measurement objects and the measurement results. There are three device characteristics to be measured: forward voltage drop VF (at 3A), reverse leakage current IR (at 180V), and reverse voltage VR (at 100μA).
As shown in the table of FIG. 5, a total of 12 samples having a specific resistance ρ = 6.0 Ω · cm of the semiconductor layer 2 were prepared. Among them, 6 samples were constructed in Wafer (1) in which the thickness of the semiconductor layer 2 was dl = 21 μm, and FIG. 5 (a) shows a table of measurement results. The other six samples are composed of wafer (2) in which the thickness of the semiconductor layer 2 is dl = 28 μm. FIG. 5 (b) shows a table of measurement results. As shown in the tables of FIGS. 5 (a) and 5 (b), the Sn / S ratio was 42%, 58.3%, 67.2%, 77.3%, 85.5%, and 100%. A sample having an Sn / S ratio of 100% is an SBD for comparison. Others are JBS. None of the samples introduced a lifetime killer.
In addition, graphs of the measurement results shown in the table of FIG. 5A for each characteristic are shown in FIGS. 6A, 6B, and 6C. FIGS. 7A, 7B, and 7C show graphs of the measurement results shown in the table of FIG. 5B for each characteristic.
[0037]
[Preliminary experiment 2]
Preliminary experiment 2 is a measurement of device characteristics with respect to different Sn / S ratios for wafer (3) in which the specific resistance ρ = 8.5 Ω · cm and the thickness dl = 30 μm of the semiconductor layer 2. The table of FIG. 8 shows the measurement objects and the measurement results. The device characteristics to be measured are the four items of forward voltage drop VF (at 1A), reverse leakage current IR (at 280V), reverse recovery time trr (at 1A), and reverse voltage VR (at 200 μA).
As shown in the table of FIG. 8, the Sn / S ratio was 42% and 100%. A sample having an Sn / S ratio of 100% is an SBD for comparison. A sample having a Sn / S ratio of 42% is JBS. None of the samples introduced a lifetime killer.
The graphs of the measurement results shown in the table of FIG. 8 for each characteristic are shown in FIGS. 9 (a), 9 (b), 9 (c) and 9 (d).
[0038]
〔simulation〕
This simulation is a simulation in which the electric field relating to the JBS model and the SBD model is calculated. 10A and 11A are cross-sectional views of the calculation target region of the SBD model, and FIGS. 10B and 11B are cross-sectional views of the calculation target region of the JBS model.
As the JBS model, the specific resistance ρ = 8.5 Ω · cm and the thickness dl = 29 μm of the semiconductor layer 2 were set. The surface concentration of the P-type active region 4 and guard ring 5 is Cs≈3 × 10¹⁷/ Cm^ThreeThe applied reverse voltage was set to VR = 300V. The semiconductor layer 2 was made of silicon, and the semiconductor oxide film 8 was made of a silicon oxide film.
The barrier metal 7 was a palladium metal. The first electrode metal 9 was aluminum.
The SBD model is different only in that there is no P-type active region 4, that is, Sp = 0, and the other points are the same as the JBS model.
[0039]
(result)
FIG. 10 shows the equipotential curves superimposed on each other. FIG. 11 shows the equal electric field strength curve superimposed. FIG. 12 is a partially enlarged view of FIG. Further, the electric field intensity distribution curve on the vertical line 1 shown in FIG. 13 is shown in FIG. 14A, the electric field intensity distribution curve on the vertical line 2 shown in FIG. 13 is shown in FIG. 14B, and the vertical line 3 shown in FIG. The upper electric field strength distribution curve is shown in FIG. The electric field intensity distribution curve on the vertical line 4 shown in FIG. 13 is shown in FIG. 14A to 14D also show the impurity concentration distribution curves on the corresponding lines 1 to 4.
[0040]
As shown by the equal electric field curve in FIG. 11, the maximum electric field strength is generated at the outer end corner portion (inside the guard ring 5) of the guard ring 5 in both the JBS model and the SBD model, and the value is about 3E5 (V / cm). became. In addition, a maximum value occurred at the inner end corner of the guard ring 5 (inside the guard ring 5). Further, in the JBS model, a maximum value occurred at the lower end of the P-type active region 4 (in the P-type active region 4).
In the JBS model, the maximum value of the lower end portion of the P-type active region 4 was higher than the maximum value of the inner end corner portion of the guard ring 5. The maximum value at the lower end of the P-type active region 4 was lower in the P-type active region 4 on the inner side (element center side). Moreover, the same value in the JBS model was lower than the maximum value of the inner end corner of the guard ring 5 in the SBD model.
[0041]
Further, the table of FIG. 15 shows the maximum electric field values on the vertical lines 1 to 4 shown in FIG. 13 and the maximum electric field value of the outer end corner portion of the guard ring 5 for each of the SBD model and the JBS model. A value obtained by dividing the electric field value of the model by the electric field value of the SBD model at the corresponding location (JBS / SBD electric field ratio), and a value obtained by subtracting the electric field value of the SBD model at the corresponding location from the electric field value of the JBS model (ΔE) Indicated.
As shown in the JBS / SBD electric field ratio in line 3 of the table of FIG. 15, the maximum electric field strength generated in the region between the two P-type active regions 4 and 4 is Ejbs, and the Schottky junction is set when Sp = 0. When the generated electric field strength is Esbd, the relationship of Ejbs ≦ 0.86 × Esbd is satisfied. The effect of decreasing the electric field strength increases as the value of Sp / S is increased, that is, the area occupation ratio of the P-type active region 4 is increased.
[0042]
[This experiment 1]
This experiment 1 is a measurement of the JBS device characteristic change with respect to the change of electron beam irradiation amount ΦEI.
(conditions)
In Samples JBS1 to 4, the specific resistance ρ = 6.5Ω · cm and the thickness dl = 23 μm of the semiconductor layer 2 were set. The Sn / S ratio was 42%. The depth Xjp of the P-type active region 4 was 6 μm. The electron beam dose ΦEI was changed to 0, 200, 300, and 400KGy.
As a comparative sample (FRD), a PN junction diode (Sn / S ratio = 100%) having ρ = 5.7 Ω · cm and a thickness of 28 μm was used. The junction depth Xjp of the comparative sample was 6 μm.
The device characteristics measured for the above samples (JBS1-4, FRD) are: forward voltage drop VF (IF = 0.1A, 1.0A, 5.0A, 10A, 20A / 25 ° C, 100 ° C), reverse voltage VR ( 200 μA), reverse recovery time trr (25 ° C., 100 ° C.), and reverse leakage current IR (25 ° C., 100 ° C.). Measurement was performed on 40 samples, and the average value was calculated to obtain the following results.
[0043]
(result)
Table (a1) in FIG. 16 shows the actual measurement results of the forward voltage drop VF with respect to different electron beam irradiation doses ΦEI at a temperature of 25 ° C. and each forward current IF. The VF characteristics of the comparative sample FRD under the same conditions are shown in the table (a2) of FIG.
Table (b1) in FIG. 16 shows the actual measurement results of the forward voltage drop VF with respect to different electron beam doses ΦEI at the temperature of 100 ° C. and the respective forward currents IF. The VF characteristics of the comparative sample FRD under the same conditions are shown in the table (b2) of FIG.
FIG. 17 is a graph showing the relationship of ΦEI−VF, which is a graph of the table of FIGS. 16 (a1) and (b1). FIG. 18A shows a graph representing the IF-VF relationship obtained by graphing the table of FIGS. 16A1 and 16A2. FIG. 18B shows a graph showing the IF-VF relationship obtained by graphing the table of FIGS. 16B1 and 16B2.
[0044]
19 (a1) (a2), other characteristics (VR (at IR = 200 μA), trr (at IF = 5 A, 25 ° C.), trr (at IF = 5 A, 100 ° C.), IR (at VR = 180V, 25 ° C.), IR (at VR = 200 V, 100 ° C.).
FIG. 19B shows a graph representing the relationship of ΦEI−VR which is graphed based on the table of FIGS. 19A1 and 19A2.
FIG. 20A shows a graph representing the relationship of ΦEI-trr graphed based on the table of FIGS. 19A1 and 19A2.
FIG. 20B shows a graph representing the relationship of ΦEI-IR graphed based on the tables of FIGS. 19A1 and 19A2.
FIGS. 21A1 and 21A2 are a table and a graph showing the trade-off characteristics of VF-trr at 25.degree.
21 (b1) and 21 (b2) are a table and a graph showing the trade-off characteristics of VF-trr at 100 ° C.
[0045]
[This experiment 2]
This experiment 2 is an experiment for verifying annealing conditions. The forward voltage drop VF and the reverse recovery time trr were measured when the electron beam dose ΦEI and the annealing conditions (temperature and time) were changed.
(conditions)
In the samples S- (1) to S- (17), two levels of specific resistance ρ = 5.0 Ω · cm and thickness dl = 19,21 μm of the semiconductor layer 2 were adopted.
Pre-oxidation presence / absence, irradiation amount ΦEI, annealing temperature, and annealing time are assigned conditions as shown in the table of FIG. 22 (a) and the table of FIG. 22 (b). Under such conditions, the forward voltage drop VF (at 1A, 5A, 20A) and the reverse recovery time trr (25 ° C., 100 ° C.) were measured. Each sample was measured for 20 samples, and the average value was calculated to obtain the following results.
[0046]
(result)
In the table of FIG. 22 (a), the measurement results of the VF characteristics of a sample having a thickness dl = 19 μm are shown. In the table of FIG. 22 (b), the measurement results of the VF characteristics of a sample having a thickness dl = 21 μm are shown.
FIG. 23 (a) shows a graph based on the table of FIG. 22 (a). FIG. 23 (b) shows a graph based on the table of FIG. 22 (b).
In the table of FIG. 24 (a), the measurement results of trr characteristics of a sample having a thickness dl = 19 μm are shown. In the table of FIG. 24 (b), the measurement results of trr characteristics of a sample having a thickness dl = 21 μm are shown. FIG. 25 (a) shows a graph based on the table of FIG. 24 (a). FIG. 25 (b) shows a graph based on the table of FIG. 24 (b).
[0047]
[This experiment 3]
In this experiment 3, the reverse voltage VR, the forward voltage drop VF, the reverse recovery time trr, and the reverse leakage current IR with respect to different electron beam doses ΦEI were measured. Also, IFSM surge test, B / P (back power) tolerance test and ESD tolerance test are performed.
(conditions)
As samples JBS1A (1) to (4), two levels of specific resistance ρ = 5.0 Ω · cm and thickness dl = 19,21 μm of the semiconductor layer 2 were adopted. The junction depth Xjp of the comparative sample was 6 μm.
As a comparative sample (FRD1A), a PN junction diode (Sn / S ratio = 0%) having a specific resistance ρ = 5.0 Ω · cm and a thickness dl = 19,21 μm of the semiconductor layer 2 was used. The junction depth Xjp of the comparative sample was 6 μm.
VR (25 ° C), VF (25 ° C, 100 ° C), trr (25 ° C, 100 ° C), IFSM, B / P, ESD, IR for different electron beam doses ΦEI (0, 200, 300, 400KGy) Measure each characteristic at 25 ℃ and 100 ℃. Each sample was measured for 20 samples, and the average value was calculated to obtain the following results.
[0048]
(result)
26 (a) and 26 (b) show VR (25 ° C.), VF (25 ° C., 100 ° C.), trr (25 ° C., 100 ° C.) with respect to different electron beam irradiation doses ΦEI in a sample having a thickness of dl = 21 μm. , ISFM, B / P (back power) resistance, ESD resistance, IR (25 ° C, 100 ° C) measurement results are shown. The graphs of these measurement results are shown in FIGS. 27 (a) (b) (c) (d) and FIGS. 28 (a) (b) (c).
29 (a) and 29 (b) show VR (25 ° C.), VF (25 ° C., 100 ° C.), trr (25 ° C., 100 ° C.) with respect to different electron beam irradiation doses ΦEI in a sample with a thickness dl = 19 μm. , ISFM, B / P (back power) resistance, ESD resistance, IR (25 ° C, 100 ° C) measurement results are shown. A graph of these measurement results is not shown.
[0049]
Next, the switching characteristics (ON → OFF characteristics) waveforms of the JBS and the comparative device are compared and disclosed.
FIG. 30 (a) shows the current at ON → OFF of JBS (ρ = 5.0Ω · cm, dl = 19μm) and SBD, FRD (ρ = 5.0Ω · cm, dl = 19μm) as a comparative device at 25 ° C. The waveform diagram showing the change of is shown.
In FIG. 30 (b), when JBS (ρ = 5.0 Ω · cm, dl = 19 μm) at 100 ° C. and SBD and FRD (ρ = 5.0 Ω · cm, dl = 19 μm) as a comparative device are turned on and off. A waveform diagram showing a change in current is shown.
[0050]
[This experiment 4]
In this experiment 4, the reverse voltage VR, the forward voltage drop VF, the reverse recovery time trr, and the reverse leakage current IR with respect to different electron beam doses ΦEI are measured.
(conditions)
Six types of samples JBS5A (1) to (6) were prepared. Two types of comparative samples FRD5A (1) and (2) were prepared.
Among the samples of the present invention, JBS 5A (1) to (4) are those having a specific resistance ρ = 8.5 Ω · cm and a thickness dl = 29 μm of the semiconductor layer 2, and the electron beam dose ΦEI = 0, 40 , 100, 300 KGy.
The sample JBS5A (5) of the present invention has a specific resistance ρ = 8.3 Ω · cm and a thickness dl = 27.7 μm of the semiconductor layer 2, and the electron beam irradiation dose ΦEI = 400 KGy.
The sample JBS5A (6) of the present invention has a specific resistance ρ = 10 Ω · cm and a thickness dl = 33 μm of the semiconductor layer 2, and the electron beam irradiation amount ΦEI = 0 KGy.
The comparative sample FRD5A (1) has a specific resistance ρ = 9.0Ω · cm and a thickness dl = 29 μm of the semiconductor layer 2, and the comparative sample FRD5A (2) has a specific resistance specific resistance ρ = The one with 8.3Ω · cm and thickness dl = 27.7 μm was used.
The device characteristics measured for the above samples are VR (25 ° C.), VF (25 ° C., 100 ° C.), trr (25 ° C., 100 ° C.), and IR (25 ° C., 100 ° C.). Each sample was measured for 20 samples, and the average value was calculated to obtain the following results.
[0051]
(result)
31A and 31B show measurement results of the reverse voltage VR, the forward voltage drop VF, the reverse recovery time trr, and the reverse leakage current IR in each sample. The graphs based on the tables of FIGS. 31 (a) and 31 (b) are shown in FIGS. 32 (a) to 32 (f).
[0052]
[Verification]
Next, the technical effects of the present invention will be verified based on the results of the above experiments and simulations.
(1) Sn / S ratio, VF characteristics, IR characteristics and VR characteristics
From the results of preliminary experiments 1 and 2, the following can be understood.
As the Sn / S ratio increases, VF increases, that is, the VF characteristics tend to decrease.
Further, IR increases as the Sn / S ratio increases, that is, the IR characteristics tend to decrease.
Further, VR decreases as the Sn / S ratio increases, that is, VR characteristics tend to decrease.
Therefore, lowering the Sn / S ratio is preferable for obtaining excellent VF characteristics, IR characteristics, and VR characteristics.
However, lowering the Sn / S ratio to less than 40 makes it difficult to form the P-type active region 4 in a dispersed manner. Further, when the Sn / S ratio is lowered, the noise characteristic at the time of switching is lowered as shown in FIG.
Therefore, Sn / S ≧ 40% is preferable.
Further, as shown in FIGS. 6 (c) and 7 (c), the bottom of the VR characteristic is in the range where the Sn / S ratio is around 80%, so that 40% ≦ Sn / S ≦ 70%. More preferably, it is more preferable that 40% ≦ Sn / S ≦ 70%, so that switch characteristics with lower noise and shorter reverse recovery time can be obtained.
[0053]
(2) Electron beam dose ΦEI
Based on the results of [Preliminary Experiments 1 & 2] and [Main Experiments 1, 2, 3, 4], it was possible to define the above Equation 1 expressed in the following format.
[0054]
The overall form of Equation 1 is a well-known equation that describes the relationship between the amount of radiation (injection amount) and the lifetime in the irradiated material.
Δ (1 / τ) = (1 / τs) − (1 / τo) = KΦ
[Ref. Radiation and industry 64 (1994), pp. 14-18 Yasuhiro Mochizuki].
The above equation was modified with respect to the dose Φ to obtain Equation 1.
Here, τs, τo → trrs, trro is set so that trr is in the element (N^-This is because it is closely related to the lifetime of holes in the layer.
[] In the above equation 1 is the entire correction term from τ → trr in formulating the experimental result.
[0055]
The first term ln (IF × Cl) / ln (Cl) in [] is a correction unit defined as device area correction. In the present invention, since two types of devices, 1A type and 5A type, are used, the representative description is made with the rated current IF. Besides this, some current density (J ≒ 165A / cm²) May be described in terms of an active region area ratio of an actual element, a chip size area ratio, or the like.
In this case, the trr increase ratio of the 5A type element to the 1A type element is merely an example of expressing the rated current ratio. After that, it can be considered that the value of Cl, the ln type proportional relationship, or the linear type proportional relationship can express all the experimental results well and express the truth more closely. In the present invention, it is as described above.
The second term in [] (dl²/ Nd²Needless to say, this defines a correction term when various combinations of ρ and t are selected for a desired device characteristic (especially VR).
[0056]
The derivation is based on the following Ref. It is in.
[Ref. IEEE, ED, Vol.37, No.5, May 1990, pp.1364 ~ 1372 "An Analysis of Positive & Negative Resistance Characteristics In High-Current-Density Region of SBD", by Yamamoto et al.]
That is, among the formulas for determining VF written in the above-mentioned document, N is particularly determined from the SBD interface at high current density.^-The product of the parasitic resistance (Rs) due to minority carriers (hole current) injected into the layer (Rs) and IF, (Rs · IF) = VF2 part varies greatly with IF, but it is related to this part Organizing the formula, VF2∝ (dl²/ Nd²) Relationship.
That is, an increase in ΦEI is accompanied by an increase in VF. VF is (dl²/ Nd²) ΦEI∝ (dl²/ Nd²).
[0057]
Also (dl²/ Nd²) Α for further correcting the α term is a correction coefficient called a power correction coefficient. N in the above document^-In the present invention, the degree of minority carrier injection into the layer has been considered on the basis of the material (ρ = 5Ω · cm / t = 21 μm), but in higher voltage devices, this minority carrier injection is more likely to occur. (Dl²/ Nd²) Term alone cannot be expressed, that is, ΦEI∝ (dl / Nd)²There is an intention to further fine-tune the squared term (in a larger direction) to fit the experimental result data.
Taking some ρ and t, (dl / Nd) and (dl / Nd)²The value of is determined. FIG. 33 shows the value of α used in Equation 1 above.
The value of α is calculated from the graph of FIG. 34 (a) by (dl / Nd).²Can be determined by reading the value of α corresponding to 、, but α is also an empirical formula. α is (dl²/ Nd²), The curve is slightly convex upward, so that it does not become a complete linear relationship, but can be approximated as the following equation 2. The 0.999th power in Equation 2 indicates the degree of slight deviation (convex upward) from (1.000 in the case of the primary relationship).
[0058]
[Equation 3]

<Check result>
  The value of ΦEI_sim obtained from the data related to trr in the experiments 1, 3 and 4 and the theoretical calculation formula is compared with the experimental value ΦEI.
  FIG. 35 (a) shows ΦEI_sim calculated by substituting the experimental result (trr_m) in this experiment 1 and each parameter in this experiment 1 into equation 1. Each parameter of this experiment 1 used for this calculation is shown in FIG.
  The calculated values of ΦEI corresponding to 70.7 ns, 52.0 ns, 48.7 ns, and 44.9 ns when irradiated with 0,200,300,400 [KGy] at the experimental value of trr (trr_m25 ° C.) are 0,246. , 309, 392 [KGy]. (Accuracy of K = 38.1)
[0059]
Similarly, at Ta = 100 ° C. (trr_m100 ° C.), each of 0, 200, 300, and 400 [KGy], Equation 1 returns a slightly higher value of 0, 258, 350, and 438 [KGy]. (K = 20.1) is not so bad.
Similarly, FIGS. 36A and 36B show the calculation result ΦEI_sim calculated by substituting the experimental result (trr_m) in this experiment 3 and each parameter in this experiment 3 into Equation 1. FIG. Each parameter of this experiment 3 used for this calculation is shown in FIG.
Since both 300 and 400 [KGy] at trr_m25 ° C are 26 ns, both ΦEI_sim 25 ° C return 423 [KGy], but ΦEI_sim 25 ° C for 30 ns at 200 [KGy] returns 234 [KGy]. It is almost OK.
It is difficult to fit the same value of trr_m100 ° C. = 33 ns for both 200 and 300 [KGy] at trr_m100 ° C. However, since it returns 360 [KGy] at 300 [KGy], it is almost OK.
Compared to FIG. 36 (a), FIG. 36 (b) of the 5A type is considerably matched between the experimental value ΦEI and the calculated value ΦEI_sim.
[0060]
Similarly, the verification result in this experiment 4 is shown in FIG. Each parameter of this experiment 4 used for calculation is shown in FIG.37 (b).
In the case of 8.5 Ω · cm / 29 μm thickness, the values 37.8 [KGy] and 105 [KGy] returned for 40 and 100 [KGy] at ΦEI_sim25 ° C. have good accuracy. Also, the values ΦEI_sim100 ° C. returned for 300 [KGy] and 400 [KGy] at ΦEI_sim100 ° C. are 105 [KGy] and 322 [KGy], which are quite accurate.
From the above, although calculated from a small number of experimental factors and data, trro is known even if there are various (dl / Nd), rated current, difference of Ta = 25 ° C / 100 ° C, etc. (before electron beam irradiation) If the desired trrs (for example, about 1.5 times the FRD trr (known)) is determined and input, the irradiation dose ΦEI necessary to obtain the trr is obtained. Can be predicted with considerable accuracy.
[0061]
<Conversion of formula>
Equation 1 can be converted to Equation 3 for obtaining trrs from trro and ΦEI.
[0062]
[Expression 4]

[1] From equation 1, if trro is known and desired trrs is input, ΦEI can be obtained.
[2] From Equation 3, trrs can be predicted from known trro and ΦEI. The above [1] is a mathematical expression convenient for the device designer, and [2] is a mathematical expression extremely useful for the device manufacturer. These are graphed.
  The values of trrs obtained by substituting each parameter of Experiment 1 into Equation 3 are shown in the table of FIG. 38 (a) and the graph of (b). Each parameter of this experiment 1 used for this calculation is shown in FIG. In FIG. 38 (b), the ◯ and x marks are experimental values of trr.
[0063]
The values of trrs obtained by substituting the parameters of Experiment 3 into Equation 3 are shown in the table of FIG. 39 (a) and the graph of (b). Each parameter of this experiment 3 used for this calculation is shown in FIG. 39 (c). In FIG. 39 (b), the ◯ and X marks are experimental values of trr.
[0064]
The values of trrs obtained by substituting each parameter of this experiment 4 into Equation 3 are shown in the table of FIG. 40 (a) and the graph of (b). Each parameter of this experiment 4 used for this calculation is shown in FIG. In FIG. 40 (b), the ◯ and X marks are experimental values of trr.
[0065]
Subsequently, all ΦEI-trrs characteristics and Ta = 100 ° C ΦEI-trrs characteristics of devices (JBS structure) used in various experiments at Ta = 25 ° C are graphed and summarized for easy comparison. Show.
FIG. 41 (a) shows the relationship between ΦEI and trr obtained by Equation 3. FIG. 41 (b) shows the ΦEI-trrs characteristic at Ta = 25 ° C. FIG. 41 (c) shows the ΦEI-trrs characteristic at Ta = 100 ° C.
[0066]
  Based on the above, it is assumed that the JBS structure is superior in the unprecedented breakdown voltage region, and that the electron beam irradiation is optimal and indispensable for speeding up the JBS structure in the JBS structure according to the present invention. ,
(1) Through [Preliminary Experiments 1 & 2] and [Main Experiments 1 to 4], various characteristics of 180V type and 280V type JBS elements were investigated. It also showed how the characteristics interact with each other.
(2) Based on the simulation, the electric field (Wn region) at the SBD interface of this structure is considerably lower than that of the conventional SBD structure (when the same VR voltage is applied), and appropriate ρ and t are selected. Therefore, it was confirmed that the maximum electric field equivalent to Ecrit was generated in the guard ring portion.
(3) The data obtained from the various experimental results of (1) above are summarized in the expression 1 and trro with respect to changes in parameters of chip size, ρ, t (dl, Nd), Ta = 25 ° C., 100 ° C. And trrs are known, it is possible to predict how much ΦEI can be obtained in order to realize trrs.
(4) In Expression 3, by converting from Expression 1, it is possible to predict how much trrs can be finally obtained if trro and ΦEI are known.
(5) As shown in FIGS. 38 to 40, it is clear that the accuracy of the above formulas 1 and 3 will be a highly practical finish.
(6) According to the JBS of the present invention, the VF (100 ° C.) characteristic does not exceed that of the rated voltage / current equivalent type FRD, and the trr characteristic is 1.5 times that of the FRD. Be within, AndMoreover, it can be said that a device with a new structure having Soft-Recovery characteristics has been optimized and embodied. Also, since it is an electron beam, IR (when ΦEI is large) is not bad.
  It is clear from the above explanation that the most difficult part of the optimization was in the process of determining and predicting the lifetime killer amount based on the selection of appropriate ρ, t, and Xjp. is there.
[0067]
(3) Annealing conditions
As can be seen from the results of Experiment 2, the annealing temperature is preferably in the range of 300 ° C. to 350 ° C. If the annealing temperature is less than 300 ° C., the effectiveness of the lifetime killer of the electron beam irradiated area cannot be fully exploited, and if it exceeds 350 ° C., the electron beam irradiated area is annealed and the lifetime killer Effectiveness will be diminished.
The annealing time is preferably in the range of 20 minutes to 60 minutes. More preferably, it is the range of 30 minutes or more and 60 minutes or less. In addition, it is preferable that the annealing time be relatively long as a relatively low annealing temperature (for example, 300 ° C.) is used within the annealing temperature range.
[0068]
【The invention's effect】
According to the present invention, various conditions such as the area ratio of the Schottky junction, the electron beam irradiation conditions, and the annealing conditions are appropriately selected, the reverse recovery time trr is shorter, the forward voltage drop VF is lower, and the reverse direction A JBS with a low leakage current IR, a low noise and a high reverse withstand voltage VR can be realized at low cost.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view (lower part) and a plan view (upper part) showing a JBS according to an embodiment of the present invention.
2 is a partially enlarged view of the surface of a semiconductor layer 2 in a region surrounded by a guard ring 5 in FIG.
FIG. 3 is a cross-sectional view in a main process for manufacturing a JBS according to an embodiment of the present invention.
4 is a cross-sectional view of the main process following FIG. 3 for manufacturing the JBS of one embodiment of the present invention;
FIG. 5 is a table showing measurement conditions and measurement results of preliminary experiment 1.
FIG. 6 is a graph showing the measurement results shown in the table of FIG. 5A for each characteristic.
FIG. 7 is a graph of the measurement results shown in the table of FIG. 5B for each characteristic.
FIG. 8 is a table showing measurement conditions and measurement results of preliminary experiment 2.
FIG. 9 is a graph of the measurement results shown in the table of FIG. 8 for each characteristic.
FIG. 10 is an equipotential curve obtained by simulation.
FIG. 11 is an equal electric field strength curve obtained by simulation.
12 is a partially enlarged view of FIG.
FIG. 13 is a cross-sectional view for specifying the positions of vertical lines 1 to 4 for measuring the electric field intensity distribution.
14 is a diagram showing electric field intensity distribution curves on vertical lines 1 to 4 shown in FIG.
FIG. 15 is a table summarizing important values and the like obtained by simulation.
FIG. 16 is a table showing measurement conditions of this experiment 1 and measurement results of VF characteristics.
FIG. 17 is a graph showing the relationship of ΦEI−VF, which is a graph of the table of FIGS. 16 (a1) and (b1).
FIG. 18A is a graph showing the IF-VF relationship obtained by graphing the table of FIGS. 16A1 and 16A2. (b) is a graph showing the IF-VF relationship obtained by graphing the table of FIGS. 16 (b1) and (b2).
FIGS. 19A and 19B are tables showing measurement conditions of the experiment 1 and measurement results of characteristics other than the VF characteristics. (B) is a graph showing the relationship of ΦEI−VR that is graphed based on the tables of (a1) and (a2).
20 (a) is a graph showing the relationship of ΦEI−trr graphed based on the tables of FIGS. 19 (a1) and (a2). (b) is a graph showing the relationship of ΦEI-IR graphed based on the tables of FIGS. 19 (a1) and (a2).
FIG. 21 (a1) is a table showing the trade-off characteristics of VF-trr at 25 ° C., and (a2) is a graph thereof. (b1) is a table showing the trade-off characteristics of VF-trr at 100 ° C., and (b2) is a graph thereof.
22 is a table showing the measurement conditions of this experiment 2 and the measurement results of forward voltage drop VF (at 1A, 5A, 20A). FIG.
FIG. 23 (a) is a graph based on the table of FIG. 22 (a). (b) is a graph based on the table of FIG. 22 (b).
FIG. 24 is a table showing measurement conditions and measurement results of reverse recovery time trr (25 ° C., 100 ° C.) in Experiment 2.
FIG. 25 (a) is a graph based on the table of FIG. 24 (a). (b) is a graph based on the table of FIG. 24 (b).
FIG. 26 is a table showing measurement conditions and measurement results of Experiment 3.
FIG. 27 is a graph of the measurement results listed in the table of FIG.
FIG. 28 is a graph showing other measurement results listed in the table of FIG.
FIG. 29 is a table showing measurement conditions and measurement results for different samples of Experiment 3.
FIG. 30 is a waveform diagram showing a change in current when JBS (ρ = 5.0Ω · cm, dl = 19 μm) and SBD and FRD (ρ = 5.0Ω · cm, dl = 19 μm) as a comparative device are turned on and off. It is. (a) is a waveform diagram at 25 ° C, and (b) is a waveform diagram at 100 ° C.
FIG. 31 is a table showing measurement conditions and measurement results of Experiment 4.
32 is a graph based on the tables of FIGS. 31 (a) and 31 (b).
FIG. 33 shows the relationship between α and specific resistance ρ used in Equation 1.
FIG. 34 (dl / Nd)²Graph (a) and table (b) showing the relationship between and α
FIG. 35 (a) is a table showing a comparison between an experimental result (trr_m) in this experiment 1 and ΦEI_sim obtained by putting each parameter of this experiment 1 in equation 1. (b) is a table | surface which shows the value of each parameter of this experiment 1 substituted to Formula 1. FIG.
36 (a) and 36 (b) are tables showing a comparison between the experimental result (trr_m) in this experiment 3 and ΦEI_sim obtained by putting each parameter in this experiment 3 in Equation 1. (c) is a table | surface which shows the value of each parameter of this experiment 3 substituted to Formula 1. FIG.
FIG. 37 (a) is a table showing a comparison between the experimental result (trr_m) in the present experiment 4 and ΦEI_sim obtained by putting each parameter of the present experiment 1 in the equation 1. (b) is a table | surface which shows the value of each parameter of this experiment 4 substituted to Formula 1. FIG.
FIG. 38 is a table (a) and a graph (b) showing trrs values obtained by substituting each parameter of Experiment 1 into Equation 3. (c) is a table | surface which shows each parameter of this experiment 1 used for this calculation.
FIG. 39 is a table (a) and a graph (b) showing trrs values obtained by substituting each parameter of Experiment 3 into Equation 3. (c) is a table | surface which shows each parameter of this experiment 3 used for this calculation.
40 is a table (a) and a graph (b) showing values of trrs obtained by substituting each parameter of Experiment 4 into Equation 3. FIG. (c) is a table | surface which shows each parameter of this experiment 4 used for this calculation.
41 (a) is a table showing the relationship between ΦEI and trr determined by Equation 3. FIG. FIG. 41 (b) is a graph showing the ΦEI-trrs characteristic at Ta = 25 ° C. FIG. 41 (c) is a graph showing the ΦEI-trrs characteristic at Ta = 100 ° C.
FIG. 42 is a curve showing a relationship between a rated voltage (V) and a loss (W) of each device of SBD and FRD.
FIG. 43 is a current change waveform schematically showing reverse recovery when the SBD and FRD devices are switched from forward bias to reverse bias.
[Explanation of symbols]
1 ... Semiconductor substrate 2 ... Semiconductor layer 3 ... N^-Type region 4 ... P-type active region ... 5 ... Guard ring 6 ... Channel stop region 7 ... Barrier metal 8 ... Semiconductor oxide film ... 9 ... First electrode metal 10 ... Second electrode metal 11 ... Equipotential ring electrode metal 23b ... PSG protective film 24 ... Final insulation protective film

Claims (1)

By using the same mask and selectively introducing the second conductivity type impurity of the opposite conductivity type into the surface of the first conductivity type semiconductor material, the second conductivity type guard ring and the guard ring are surrounded. A plurality of second conductivity type active regions formed,
Each of the patterns in which the second conductivity type active regions are exposed on the surface of the semiconductor material has a circular shape, and one second conductivity type active region (excluding those arranged on the outermost periphery). There are a total of six other second conductivity type active regions closest to each other, and the center of the other second conductivity type active region is arranged at each vertex of a regular hexagon centering on the center of the one second conductivity type active region. Pattern,
A barrier metal that adheres to the second conductive type active region exposed on the surface of the semiconductor material and the first conductive type region adjacent to the second conductive type active region exposed on the surface of the semiconductor material in a region surrounded by the guard ring is laid on the surface of the semiconductor material. And
An insulating film having an opening that opens on a region surrounded by the guard ring, and laid on the surface of the semiconductor material;
A first electrode connected to the barrier metal and the guard ring through the opening;
In the semiconductor device comprising the second electrode on the first conductivity type region side,
(1) When the area of the region surrounded by the guard ring is S, the area of the second conductivity type active region is Sp, and the area of the first conductivity type region is Sn (S = Sp + Sn), Sn / S ≧ 40% of the relationship is satisfied,
(2) Impurity concentration (Nd) of the semiconductor material in which the maximum electric field intensity Emax is generated at the outer end corner portion of the guard ring and Emax ≦ 3.0 × 10 ⁵ (V / cm) or less when reverse voltage is applied. And the thickness (dl) thereof and the depth (Xjp) of the second conductivity type active region,
(3) A maximum value of the electric field strength higher than the maximum value of the electric field strength generated at the inner end corner portion of the guard ring is generated at the lower end portion of the second conductivity type active region, and the lower end portion of the second conductivity type active region The maximum value of the electric field strength generated in the second conductive type active region on the inner side is lower, and the maximum electric field strength Ejbs generated in the region between the two second conductive type active regions is lower than that of the semiconductor material. It has a value of Sp / S that satisfies the relationship of Ejbs ≦ 0.86 × Esbd with respect to the electric field strength Esbd generated at a position deeper than the surface and generated at the Schottky junction when Sp = 0.
(4) The Schottky barrier height φBN for the first conductivity type region of the barrier metal is φBN ≧ 0.68 eV,
(5) In the semiconductor device , wherein a lifetime killer is introduced into the semiconductor material by electron beam irradiation , when the impurity concentration of the semiconductor material is Nd, the specific resistance is ρ, and the thickness is dl, In this method of manufacturing a semiconductor device, after substituting the desired trrs value into Equation 1, obtaining the dose ΦEI that satisfies Equation 1 with the desired trrs value substituted, and irradiating the electron beam with the obtained dose ΦEI A method of manufacturing a semiconductor device, comprising performing a annealing treatment in a temperature range of 300 ° C. to 350 ° C. and a time range of 30 minutes to 60 minutes to introduce a lifetime killer into the semiconductor material.

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