JP4316831B2 - Method for manufacturing semiconductor device - Google Patents

Description

【００４５】
ここで、図２７に加熱処理後の応力の変化を測定した結果を示す。常圧条件での加熱処理では応力が圧縮側に移行しており、Ｗが酸化されていることがわかる。逆に、減圧条件での加熱処理を行うと応力は引張側に移行している。
【００４６】
次に、図２６に常圧条件（グラフ中に記載）で処理を行った基板および減圧条件で処理を行った基板に対して、シート抵抗の変化を測定した結果を示す。常圧条件で処理を行った基板は処理後にシート抵抗が高くなってしまっている。これは、炉内雰囲気中に含まれる酸素によりＷ表面が酸化してしまったことが原因と考えられる。逆に、減圧条件で処理を行った基板は、処理後にシート抵抗が下がっている。表１に示す条件での処理により炉内雰囲気中の酸素濃度を低減することができるため、Ｗの酸化防止にかなりの効果があると考えられる。
【００４７】
なお、本実施例では、上記活性化処理と同時に、結晶化の際に触媒として使用したニッケルがｎ型不純物領域（Ａ）（１３１、１３２）にゲッタリングされ、主にチャネル形成領域となる半導体層中のニッケル濃度が低減される。このようにして作製したチャネル形成領域を有するＴＦＴはオフ電流値が下がり、結晶性が良いことから高い電界効果移動度が得られ、良好な特性を達成することができる。
【００４８】
本活性化処理は、低濃度の酸素雰囲気下で行われるため、無機層間絶縁膜を形成する前に活性化処理を行うことができる。ただし、用いた配線材料が熱に弱い場合には、配線等を保護するため無機層間絶縁膜（シリコンを主成分とする絶縁膜、例えば窒化珪素膜）を形成した後で活性化処理を行うことが好ましい。
【００４９】
活性化工程後、ソース線に沿うようにかつ接して補助配線１４０を形成する。補助配線は、ゲート電極を形成する導電膜より抵抗率の小さい材料からなる導電膜、例えばＡｌ、Ｃｕ、Ａｇのいずれかの元素からなる導電膜、または前記元素を含む合金からなる導電膜からなる。また、この抵抗率の小さい導電膜からなる配線（配線（Ａ）とする）を保護するために、Ｔａ、Ｗ、Ｔｉ、Ｍｏ、Ｃｒ、ＮｄもしくはＮｂのいずれかの元素からなる導電膜、前記元素を主成分とする合金からなる導電膜、または前記元素を主成分とする化合物からなる導電膜からなる配線（Ｂ）を配線（Ａ）上に形成してもよい。
以上のように、低抵抗材料からなる補助配線をソース線に沿うようにかつ接して設けることで、ソース線全体の抵抗率を抑えることができる。（図５（Ａ））なお、図１１におけるＡ−Ａ’線での断面図は、図５（Ｂ）で示す。
【００５０】
次いで、全面を覆う無機層間絶縁膜１４１を形成する。この無機層間絶縁膜６４６は、プラズマＣＶＤ法またはスパッタ法を用いて、厚さ１００〜２００ｎｍとしてシリコンを含む絶縁膜から形成される。（図５（Ｃ））なお、図１１におけるＡ−Ａ’線での断面図は、図５（Ｄ）で示す。
【００５１】
無機層間絶縁膜１４１を形成した後、窒素雰囲気中で４１０℃、１時間の熱処理を行った。なお、水素を含む窒素雰囲気下で加熱処理を行ってもよい。この工程は層間絶縁膜に含まれる水素により半導体層のダングリングボンドを終端する工程である。水素化の他の手段として、水素雰囲気下におけるファーネスアニール、もしくはプラズマ水素化（プラズマにより励起された水素を用いる）を行っても良い。
【００５２】
また、活性化処理としてレーザーアニール法を用いる場合には、上記水素化を行った後、エキシマレーザーやＹＡＧレーザー等のレーザー光を照射することが望ましい。それぞれの半導体層に添加された不純物元素を活性化処理する工程を行う。
【００５３】
次いで、無機層間絶縁膜１４１上に有機樹脂材料からなる有機層間絶縁膜１４２を形成する。本実施例では、アクリル樹脂を用いた。次いで、各不純物領域に達するコンタクトホールを形成するためのパターニングを行う。
【００５４】
その後、透明導電膜を８０〜１２０nmの厚さで形成し、パターニングすることにより画素電極１５０を形成する。透明導電膜には、酸化インジウム・スズ（ITO）、酸化インジウム酸化亜鉛合金（In₂O₃-ZnO）、酸化亜鉛（ZnO）も適した材料であり、さらに可視光の透過率や導電率を高めるためにガリウム（Ga）を添加した酸化亜鉛（ZnO:Ga）を好適に用いることができる。
【００５５】
次いで、不純物領域を電気的に接続する配線１５６〜１６２を形成する。なお、これらの配線は、膜厚５０nmのＴｉ膜と膜厚５００nmの合金膜（ＡｌとＴｉとの合金膜）との積層膜をパターニングして形成する。配線１５９は不純物領域１３２とソース線１２４とを電気的に接続している。（図５）
【００５６】
なお、本実施例では、ｎ型不純物領域（Ａ）１３２とソース線１２４とを直接接続するようにコンタクトホールを形成し配線を設けたが、ｎ型不純物領域（Ａ）１３２と補助配線１４０とを直接接続するように配線１５９を設けたり、ｎ型不純物領域（Ａ）１３２、補助配線１４０およびソース線１２４を直接接続するように配線１５９を設けたりしてもよい。
【００５７】
本実施例では、画素電極として、透明導電膜を用いた例を示したが、反射性を有する導電性材料を用いて画素電極を形成すれば、反射型の表示装置を作製することができる。その場合、電極を作製する工程で画素電極を同時に形成でき、その画素電極の材料としては、ＡｌまたはＡｇを主成分とする膜、またはそれらの積層膜の反射性の優れた材料を用いることが望ましい。
【００５８】
以上のようにして、ｎチャネル型ＴＦＴ２０１およびｐチャネル型ＴＦＴ２０２を有する駆動回路２０６と、画素ＴＦＴ２０３および保持容量２０４とを有する画素部２０７を同一基板上に形成することができる。本明細書中では、このような基板を便宜上、アクティブマトリクス基板と呼ぶ。
【００５９】
本実施例で形成されたｎチャネル型ＴＦＴの半導体層において、ｎ型不純物領域（Ｂ）およびｎ型不純物領域（Ｃ）の幅をそれぞれＷ１、Ｗ２とすると、Ｗ１は、０．５〜１．５μｍ、Ｗ２は、１．０〜３．０μｍの幅となるように形成することができる。なお、Ｗ１＋Ｗ２が１．５〜４．５μｍ（好ましくは２．０〜３．０μｍ）となるようにレジストからなるマスク１２９、１３０を形成すればよい。本実施例で示した作製工程によれば、ｎ型不純物領域（Ｂ）およびｎ型不純物領域（Ｃ）の幅を長く形成することができるため、オフ電流を下げるのに有効である。
【００６０】
（実施例２）
本実施例では、実施例１で作製したアクティブマトリクス基板から、アクティブマトリクス型液晶表示装置を作製する工程を以下に説明する。説明には図７を用いる。なお、図２の上面図におけるＡ−Ａ'線に対する断面図（ソース線）は、図７（Ｂ）に、図２のＢ−Ｂ'線に対する断面図（画素ＴＦＴ）は図７のＢ−Ｂ'線の領域、図２のＣ−Ｃ'線に対する断面図（保持容量）は図７のＣ−Ｃ'線の領域を示す。
【００６１】
まず、実施例１に従い、図６の状態のアクティブマトリクス基板を得た後、図６のアクティブマトリクス基板上に配向膜１８０を形成しラビング処理を行う。なお、本実施例では配向膜１８０を形成する前に、アクリル樹脂膜等の有機樹脂膜をパターニングすることによって基板間隔を保持するための柱状のスペーサを所望の位置に形成した。また、柱状のスペーサに代えて、球状のスペーサを基板全面に散布してもよい。
【００６２】
次いで、対向基板１８１を用意する。この対向基板には、着色層１８６、遮光層１８７が各画素に対応して配置されたカラーフィルタが設けられている。また、駆動回路の部分にも遮光層１８９を設けた。このカラーフィルタと遮光層１８９とを覆う平坦化膜１８８を設けた。次いで、平坦化膜１８８上に透明導電膜からなる対向電極１８２を画素部に形成し、対向基板の全面に配向膜１８３を形成し、ラビング処理を施した。
【００６３】
そして、画素部と駆動回路が形成されたアクティブマトリクス基板と対向基板とをシール材１８４で貼り合わせる。シール材１８４にはフィラーが混入されていて、このフィラーと柱状スペーサによって均一な間隔を持って２枚の基板が貼り合わせられる。その後、両基板の間に液晶材料１８５を注入し、封止剤（図示せず）によって完全に封止する。液晶材料１８５には公知の液晶材料を用いれば良い。このようにして図７に示すアクティブマトリクス型液晶表示装置が完成する。そして、必要があれば、アクティブマトリクス基板または対向基板を所望の形状に分断する。さらに、公知の技術を用いて偏光板等を適宜設けた。そして、公知の技術を用いてＦＰＣを貼りつけた。
【００６４】
こうして得られた液晶表示パネルの構成を図８の上面図を用いて説明する。なお、図７と対応する部分には同じ符号を用いた。
【００６５】
図８（Ａ）で示す上面図は、画素部、駆動回路、ＦＰＣ（フレキシブルプリント配線板：Flexible Printed Circuit）を貼り付ける外部入力端子２１０、外部入力端子と各回路の入力部までを接続する配線２１１などが形成されたアクティブマトリクス基板と、カラーフィルタなどが設けられた対向基板１８１とがシール材１８４を介して貼り合わされている。
【００６６】
ゲート線側駆動回路２０６ａと重なるように対向基板側に遮光層１８９ａが設けられ、ソース線側駆動回路２０６ｂと重なるように対向基板側に遮光層１８９ｂが形成されている。また、画素部２０７上の対向基板側に設けられたカラーフィルタ２１２は遮光層と、赤色（Ｒ）、緑色（Ｇ）、青色（Ｂ）の各色の着色層とが各画素に対応して設けられている。実際に表示する際には、赤色（Ｒ）の着色層、緑色（Ｇ）の着色層、青色（Ｂ）の着色層の３色でカラー表示を形成するが、これら各色の着色層の配列は任意なものとする。
【００６７】
ここでは、カラー化を図るためにカラーフィルタ２１２を対向基板に設けているが特に限定されず、アクティブマトリクス基板を作製する際、アクティブマトリクス基板にカラーフィルタを形成してもよい。
【００６８】
また、カラーフィルタにおいて隣り合う画素の間には遮光層が設けられており、表示領域以外の箇所を遮光している。また、ここでは、駆動回路を覆う領域にも遮光層１８９ａ、１８９ｂを設けているが、駆動回路を覆う領域は、後に液晶表示装置を電気器具の表示部として組み込む際、カバーで覆うため、特に遮光層を設けない構成としてもよい。また、アクティブマトリクス基板を作製する際、アクティブマトリクス基板に遮光層を形成してもよい。
【００６９】
また、上記遮光層を設けずに、対向基板と対向電極の間に、カラーフィルタを構成する着色層を複数層重ねた積層で遮光するように適宜配置し、表示領域以外の箇所（各画素電極の間隙）や、駆動回路を遮光してもよい。
【００７０】
また、外部入力端子にはベースフィルム２１３と配線２１４から成るＦＰＣが異方性導電性樹脂２１５で貼り合わされている。さらに補強板で機械的強度を高めている。
【００７１】
図８（Ｂ）は図８（Ａ）で示す外部入力端子２０７のｅ−ｅ'線に対する断面図を示している。２１７は、画素電極１５６を形成するために成膜した導電膜からなる配線である。導電性粒子２１６の外径は配線２１７のピッチよりも小さいので、接着剤２１５中に分散する量を適当なものとすると隣接する配線と短絡することなく対応するＦＰＣ側の配線と電気的な接続を形成することができる。
【００７２】
以上のようにして作製される液晶表示パネルは各種電気器具の表示部として用いることができる。
【００７３】
（実施例３）
実施例１の図５（Ａ）で示す活性化工程終了後、補助配線３０１（配線（Ａ）３０１ａおよび配線（Ｂ）３０１ｂからなる）を形成する。（図９（Ｂ））配線（Ａ）は、抵抗率の小さいＡｌ、Ｃｕ、Ａｇのいずれかの元素からなる導電膜、または前記元素を含む合金からなる導電膜からなる。また配線（Ｂ）は、▲１▼無機層間絶縁膜および有機層間絶縁膜にコンタクトホールを形成する際に、配線（Ａ）をエッチング液から保護する、▲２▼半導体層および補助配線を接続するゲート線と同一の面上に形成される配線と配線（Ａ）が接触して電気的な腐食が起こるのを防ぐ、という▲１▼、▲２▼の目的で形成される。配線（Ｂ）は、Ｔａ、Ｗ、Ｔｉ、Ｍｏ、Ｃｒ、ＮｄもしくはＮｂのいずれかの元素からなる導電膜、前記元素を主成分とする合金からなる導電膜または前記元素を主成分とする化合物からなる導電膜からなる。配線（Ａ）、配線（Ｂ）を形成するそれぞれの導電膜を形成しエッチングして、ソース配線全面に沿うようにかつ接するような補助配線３０１を形成する。
【００７４】
次いで、補助配線３０１、ゲート電極（第１の導電膜１４０および第２の導電膜１２６）を覆うようにして、無機層間絶縁膜３０２を形成し、水素を約３％含む窒素雰囲気中で４１０℃、１時間の加熱処理して、半導体層を水素化する工程を行う。水素化の工程後、その上に有機層間絶縁膜３０３を形成する。（図９（Ｃ））
無機層間絶縁膜３０２としては、酸化窒化シリコン膜、または窒化シリコン膜を用いればよく、有機層間絶縁膜３０３としては、アクリル樹脂膜を用いた。
【００７５】
その後、各不純物領域および配線（Ｂ）３０１ｂに達するコンタクトホールを形成する。
次いで、実施例１の図６に示す工程に沿って画素電極１５０を形成した後、ゲート線１６４、配線１５６〜１６２を形成し、アクティブマトリクス基板が完成する。（図１０、図１１）なお、配線１５９は、補助配線３０１および不純物領域１３２を電気的に接続しており、かつ配線１５９は補助配線３０１および不純物領域１３２に直接接して設けられている。
【００７６】
本実施例で完成したアクティブマトリクス基板は、実施例２と組み合わせてアクティブマトリクス型液晶表示装置を作製することができる。
【００７７】
（実施例４）
実施例１の図４（Ｃ）の工程まで行ったら、無機層間絶縁膜４０１を形成する。この無機層間絶縁膜４０１としては、プラズマＣＶＤ法またはスパッタ法を用い、厚さを１００〜２００ｎｍとしてシリコンを含む絶縁膜で形成する。本実施例では、プラズマＣＶＤ法により膜厚１５０ｎｍの酸化窒化シリコン膜を形成した。酸化窒化シリコン膜に限定されるものでなく、他のシリコンを含む絶縁膜を単層または積層構造として用いても良い。
【００７８】
次に、それぞれの半導体層に添加された不純物元素を活性化処理する工程を行う。（図１２（Ａ））この活性化工程はファーネスアニール炉を用いる熱アニール法で行う。熱アニール法としては、酸素濃度が２０ｐｐｍ以下、好ましくはロータリーポンプおよびメカニカルブースターポンプにより０．１Ｐａ以下まで排気を行って酸素濃度が１０ｐｐｍ以下にし、減圧状態（大気圧以下、好ましくは１００００Ｐａ以下）の窒素雰囲気で４００〜７００℃、代表的には５００〜６００℃で行えばよく、本実施例では６００℃、４時間の加熱処理で活性化処理を行う。
【００７９】
なお、活性化処理と同時に、結晶化の際に触媒として使用したニッケルが高濃度のリンを含む不純物領域にゲッタリングされ、主にチャネル形成領域となる半導体層中のニッケル濃度が低減される。このようにして作製したチャネル形成領域を有するＴＦＴはオフ電流値が下がり、結晶性が良いことから高い電界効果移動度が得られ、良好な特性を達成することができる。
【００８０】
さらに、半導体層を水素化するために、窒素雰囲気中で４１０℃、１時間の加熱処理を行った。なお、水素を含む雰囲気下で加熱処理を行ってもよい。次いで、無機層間絶縁膜４０１上に配線（Ａ）、配線（Ｂ）を形成するそれぞれの導電膜を形成し、エッチングして、無機層間絶縁膜４０１を介してソース配線に沿うように補助配線４０２（配線（Ａ）４０２ａ、配線（Ｂ）４０２ｂ）を成膜する。（図１２（Ｂ））配線（Ａ）は、抵抗率の小さいＡｌ、Ｃｕ、Ａｇのいずれかの元素からなる導電膜、または前記元素を含む合金からなる導電膜からなる。配線（Ｂ）は、Ｔａ、Ｗ、Ｔｉ、Ｍｏ、Ｃｒ、ＮｄもしくはＮｂのいずれかの元素からなる導電膜、前記元素を主成分とする合金からなる導電膜または前記元素を主成分とする化合物からなる導電膜からなる。
【００８１】
次いで、補助配線４０２を覆うように有機絶縁物材料から成る有機層間絶縁膜４０３を形成する。本実施例では膜厚１．６μｍのアクリル樹脂膜を形成した。次いで、各不純物領域ソース線２０５、および補助配線４０２（配線（Ｂ）４０２ｂ）に達するコンタクトホールを形成するためのパターニングを行う（図１３）。
【００８２】
本実施例では、無機層間絶縁膜４０１の下に、ソース線２０５が形成されており、無機層間絶縁膜４０１を介してソース線２０５に沿うように補助配線４０２を形成しているが、ソース配線２０５を形成せず、無機層間絶縁膜４０１上に（ゲート電極と同一の面上に）補助配線４０２を形成して低抵抗の配線を実現することもできる。
【００８３】
その後、各不純物領域および配線（Ｂ）３０１ｂに達するコンタクトホールを形成する。次いで、実施例１の図６に示した工程から後の工程にしたがって、画素電極１５０、ゲート線１６４、配線１５６〜１６２を形成し、アクティブマトリクス基板を作製することができる。配線１５９は、ソース線２０５、補助配線４０２、および不純物領域１３２を電気的に接続しており、かつ配線１５９は、ソース線２０５および補助配線４０２に直接接するように設けられている。（図１３）
【００８４】
以上の様にして、ｎチャネル型ＴＦＴ２０１及びｐチャネル型ＴＦＴ２０２を有する駆動回路２０６と、画素ＴＦＴ２０３及び保持容量２０４とを有する画素部２０７を同一基板上に形成することができる。（図１４）
【００８５】
本実施例は、実施例２と組み合わせて、アクティブマトリクス型液晶表示装置を形成することが可能である。
【００８６】
（実施例５）
本実施例では、求められる特性によってＴＦＴを作りわける方法について説明する。なお、実施例１と同一の工程については同一の符号を用いる。
【００８７】
実施例１の工程に従い、基板１００上に下地膜１０１およびアモルファスシリコン膜を形成し、結晶化の工程を行って島状の半導体層を得る。次に、島状半導体層５０２〜５０６をゲート絶縁膜５０７で覆う。ゲート絶縁膜５０７はプラズマＣＶＤ法やスパッタ法で形成する。厚さは、４０〜１５０ｎｍとし、シリコンを含む絶縁膜から形成する。もちろん、このゲート絶縁膜５０７は、シリコンを含む絶縁膜を単層または積層にして用いることができる。
【００８８】
ゲート絶縁膜５０７上に膜厚２０〜１００ｎｍの導電膜（Ａ）５０８および膜厚１００〜４００ｎｍの導電膜（Ｂ）５０９を形成する。導電膜（Ａ）および導電膜（Ｂ）は、Ｔａ、Ｗ、Ｔｉ、Ｍｏ、Ａｌ、Ｃｕから選ばれた元素、またはこれらの元素を主成分とする合金材料もしくは化合物材料から形成する。また、リン（Ｐ）等の不純物元素をドーピングした多結晶シリコン膜に代表される半導体膜を用いてもよい。なお、本実施形態では、導電膜（Ａ）５０８としてＴａＮ、導電膜（Ｂ）５０９としてＷを用いた。（図２０（Ｂ））
【００８９】
次に、フォトリソグラフィー法を用いてレジストからなるマスク５１０〜５１６を形成し、ゲート電極および容量配線を形成するための第１のエッチング処理を行う。本実施例では、ＩＣＰ（Inductively Coupled Plasma:誘導結合型プラズマ）エッチング法を用い、エッチングガスにＣＦ₄、Ｃｌ₂およびＯ₂を用い、それぞれのガス流量比を２５／２５／１０（SCCM）とし、１Paの圧力でコイル型の電極に５００ＷのＲＦ（１３．５６MHz）電力を投入してプラズマを生成してエッチングを行う。基板側（試料ステージ）にも１５０ＷのＲＦ（１３．５６MHz）電力を投入し、実質的に負の自己バイアス電圧を印加する。
【００９０】
この後、レジストからなるマスク５１０〜５１６を除去せずに第２のエッチング条件に変え、エッチング用ガスにＣＦ₄およびＣｌ₂を用い、それぞれのガス流量比を３０／３０（SCCM）とし、１Paの圧力でコイル型の電極に５００ＷのＲＦ（１３．５６MHz）電力を投入してプラズマを生成して約３０秒程度のエッチングを行う。基板側（試料ステージ）にも２０ＷのＲＦ（１３．５６MHz）電力を投入し、実質的に負の自己バイアス電圧を印加する。ＣＦ₄およびＣｌ₂を混合した第２のエッチング条件では、Ｗ膜およびＴａＮ膜が同程度にエッチングされ、第１の形状のゲート電極および配線５１７〜５２３が形成される。
【００９１】
レジストからなるマスク５１０〜５１６を除去せずに第１のドーピング処理を行う。半導体層５０２〜５０６に、ｎ型を付与する不純物元素（以下、ｎ型不純物元素という）を添加する。ドーピング処理は、イオンドープ法、もしくはイオン注入法で行えばよい。ｎ型不純物元素としては、周期律表の第１５族に属する元素、典型的にはリン（Ｐ）またはヒ素（Ａｓ）といった元素を用いる。この場合、第１の形状のゲート電極および容量配線５１７〜５２１がマスクとなって自己整合的にｎ型不純物濃度が１×１０²⁰〜１×１０²¹atoms/cm³のｎ型不純物領域（ｎ⁺）５２４ａ〜５２４ｅが形成される。（図２０（Ｃ））
【００９２】
次に、レジストからなるマスク５１０〜５１６をそのままに第２のエッチング処理を行う。エッチングガスにＣＦ₄、Ｃｌ₂およびＯ₂を用い、それぞれのガス流量比を２０／２０／２０（SCCM）とし、１．０Paの圧力でコイル型の電極に５００ＷのＲＦ（１３．５６MHz）電力を投入してプラズマを生成してエッチングを行う。基板側（試料ステージ）には、２０ＷのＲＦ（１３．５６MHz）電力を投入して約８０秒のエッチング処理を行う。これにより第２の形状のゲート電極および配線５２５〜５３１が形成される。
【００９３】
次いで、レジストからなるマスク５１０〜５１６をそのままに、第２の形状のゲート電極および容量配線５２５〜５２９をマスクとして用い、第２の形状の導電層（Ａ）（ＴａＮ膜）の下部にもｎ型不純物元素が添加されるように第２のドーピング処理を行う。この処理により、ｎ型不純物領域（ｎ⁺）よりチャネル形成領域側にｎ型不純物元素濃度が１×１０¹⁸〜１×１０¹⁹atoms/cm³のｎ型不純物領域（ｎ^-）５３２ａ〜５３２ｅが形成される。（図２１（Ａ））
【００９４】
次いで、レジストからなるマスク５１０〜５１６を除去し、後のｎチャネル型ＴＦＴおよび後の画素ＴＦＴを覆うレジストからなるマスク５３３、５３４を形成し、第３のドーピング処理を行う。後の第１のｐチャネル型ＴＦＴおよび後の第２のｐチャネル型ＴＦＴの半導体層に第２の形状のゲート電極５２６、５２７、容量配線５２９をマスクにしてｐ型不純物元素を添加して、自己整合的にｐ型不純物領域（ｐ⁺）５３５ａ〜５３５ｃおよびｐ型不純物領域（ｐ^-）５３５ｄ〜５３５ｆを形成する。本実施例では、ｐ型不純物領域はジボラン（Ｂ₂Ｈ₆）を用いたイオンドープ法で形成する。あらかじめ、ｐチャネル型ＴＦＴの半導体層には、ｎ型不純物元素が添加されているが、第３のドーピング処理の際に添加されるｐ型不純物元素の濃度の方が高くなるようにドーピング処理することにより、後のｐチャネル型ＴＦＴのソース領域およびドレイン領域として機能するために何ら問題は生じない。なお、本明細書において、後のｎチャネル型ＴＦＴとは、作製工程中にあり完成後にｎチャネル型ＴＦＴとして機能するＴＦＴのことを指す。いずれのＴＦＴにも適応する。（図２１（Ｂ））
【００９５】
次いで、レジストからなるマスク５３６、５３７で駆動回路のｎチャネル型ＴＦＴおよび第１のｐチャネル型ＴＦＴを覆い、第３のエッチング処理を行う。エッチングガスには、Ｃｌ₂を用い、ガスの流量は８０（SCCM）とし、１．２Paの圧力でコイル型の電極に３５０ＷのＲＦ（１３．５６MHz）電力を投入してプラズマを生成して約３０秒エッチングを行う。基板側（試料ステージ）、には５０ＷのＲＦ（１３．５６MHz）電力を投入し、実質的に負の自己バイアス電圧を印加する。こうして第３の形状のゲート電極５３８、５３９、容量配線５４０、配線５４１、５４２が形成される。（図２１（Ｃ））
【００９６】
以上までの工程で、それぞれの半導体層に不純物領域が形成される。
【００９７】
この後、それぞれの半導体層に添加された不純物元素を活性化処理する工程を行う。この活性化工程は炉を用いる熱アニール法を行う。熱アニール法の条件としては、酸素濃度が２０ppm以下、好ましくはロータリーポンプおよびメカニカルブースターポンプにより０．１Ｐａ以下まで排気を行い酸素濃度が１０ｐｐｍ以下にして、減圧状態（大気圧以下好ましくは、１００００Ｐａ以下）の窒素雰囲気中で４００〜７００℃、代表的には５００〜６００℃で行えばよく、本実施例では５５０℃、４時間の加熱処理で活性化処理を行った。なお、熱アニール法の他に、レーザーアニール法、またはラピッドサーマルアニール法（ＲＴＡ法）を適用することができる。
【００９８】
なお、本実施例では、上記活性化処理と同時に、結晶化の際に触媒として使用したニッケルがｎ型不純物領域（ｎ⁺）（５２４ａ、５２４ｃ、５２４ｄ）にゲッタリングされ、主にチャネル形成領域となる半導体層中のニッケル濃度が低減される。このようにして作製したチャネル形成領域を有するＴＦＴはオフ電流値が下がり、結晶性が良いことから高い電界効果移動度が得られ、良好な特性を達成することができる。
【００９９】
本活性化処理は、酸素の濃度を低減した減圧雰囲気下で行われるため、無機層間絶縁膜を形成する前に活性化処理を行うことができる。ただし、用いた配線材料が熱に弱い場合には、配線等を保護するため無機層間絶縁膜（シリコンを主成分とする絶縁膜、例えば窒化珪素膜）を形成した後で活性化処理を行うことが好ましい。
【０１００】
活性化工程後、ソース線に沿うようにかつ接して補助配線５４３を形成する。補助配線は、ゲート電極を形成する導電膜より抵抗率の小さい材料からなる導電膜、例えばＡｌ、Ｃｕ、Ａｇのいずれかの元素からなる導電膜、または前記元素を含む合金からなる導電膜からなる。また、この抵抗率の小さい導電膜からなる配線（配線（Ａ）とする）を保護するために、Ｔａ、Ｗ、Ｔｉ、Ｍｏ、Ｃｒ、ＮｄもしくはＮｂのいずれかの元素からなる導電膜、前記元素を主成分とする合金からなる導電膜、または前記元素を主成分とする化合物からなる導電膜からなる配線（Ｂ）を配線（Ａ）上に形成してもよい。
以上のように、低抵抗材料からなる補助配線をソース線に沿うようにかつ接して設けることで、ソース線全体の抵抗率を抑えることができる。（図２２（Ａ））なお、図１１におけるＡ−Ａ’線での断面図は、図２２（Ｂ）に示す。
【０１０１】
次いで、全面を覆う無機層間絶縁膜１４１を形成し、実施例１の図６からの工程に従ってアクティブマトリクス基板を完成させることができる。
【０１０２】
本実施例で完成したアクティブマトリクス基板は、実施例２と組み合わせてアクティブマトリクス型液晶表示装置を作製することができる。
【０１０３】
（実施例５）
第１の導電膜および第２の導電膜からなるゲート電極を図２３〜２５に示すような形状に形成し、補助配線を形成する工程と同一工程において、補助配線と同一の導電膜から保持容量配線を形成してもよい。本実施例によると、エッチング工程により薄くなったゲート絶縁膜を半導体層と保持容量配線とで挟むため、実施例１〜４の方法と比較して、容量の大きな保持容量を形成することができる。
【０１０４】
（実施例６）
図１６（Ｂ）に示す画素ＴＦＴは実施例１を用いて作製することができるＴＦＴを上面から観察した図面代用写真である。なお、図１６（Ａ）は、従来のように抵抗値を下げるための補助配線が形成されていない画素ＴＦＴを上面から観察した図面代用写真である。
【０１０５】
この図１６（Ａ）および（Ｂ）についてソース線の抵抗値を測定した結果を図１７に示す。ソース線に抵抗をさげるためにＡｌ−Ｎｄ配線を形成した図１６（Ｂ）の抵抗値と従来例の図１６（Ａ）の抵抗値とを比較すると、図１７から、抵抗値は１／２程度に低減できていることが確認できる。
【０１０６】
また、ソース線のシート抵抗値（Ω／□）を測定した。図１８は、測定結果を示している。測定ポイントを１０点とり、電圧を０〜０．１（Ｖ）で０．００１（Ｖ）ずつ、変動させ、各電圧における電流を測定することで、シート抵抗値を算出している。なお、ソース線は以下の表のように設計されている。
【０１０７】
【表２】

【０１０８】
図１８に示すように、本発明を用いることによりソース線のシート抵抗値を従来の１／４程度にまで低減することができた。
【０１０９】
（実施例７）
実際に、静止画を表示させた様子を観察した図面代用写真を図１９に示す。
【０１１０】
（実施例８）
本実施例では、実施例４で作製したアクティブマトリクス基板からアクティブマトリクス駆動の発光装置を作製する工程を図２８を用いて説明する。図２８（Ｂ）は、画素部を上面から見た図であり、Ａ−Ａ'線で切った断面図が図２８（Ａ）である。
【０１１１】
基板１６０１はガラス基板を用いる。このガラス基板１６０１上には駆動回路（図示せず）にｎチャネル型ＴＦＴおよびｐチャネル型ＴＦＴが形成され、画素部１６３２にスイッチング用ＴＦＴ１６３０、電流制御用ＴＦＴ１６３１が形成されている。これらのＴＦＴは、半導体層１６０３、１６０４、ゲート絶縁膜１６０５、ゲート電極１６０６、１６０７などを用いて形成されている。
【０１１２】
基板１６０１上に形成する下地絶縁膜１６０２は、酸化窒化シリコン膜、窒化シリコン膜などを５０〜２００ｎｍの厚さに形成する。無機層間絶縁膜１６１８は、窒化シリコン膜または酸化窒化シリコン膜などから形成し、有機層間絶縁膜１６１９はアクリルまたはポリイミドなどから形成される。
【０１１３】
陽極、陰極およびその間にエレクトロルミネセンス（Electro Luminescence）が得られる有機化合物を含む層（以下、ＥＬ層という）を有するＥＬ素子は画素部のＴＦＴ上に形成される。なお、有機化合物におけるルミネセンスには一重項励起状態から基底状態に戻る際の発光（蛍光）と三重項励起状態から基底状態に戻る際の発光（リン光）とがあり、その両者を含むものとする。
【０１１４】
ＥＬ素子は、配線を覆うようにアクリルやポリイミドなどの有機樹脂、好ましくは感光性の有機樹脂を用いてバンク１６１５を形成した後に設ける。本実施例では、ＥＬ素子１６２０は、ＩＴＯ（酸化インジウム・スズ）で形成される陽極１６１６、ＥＬ層１６１７、ＭｇＡｇやＬｉＦなどのアルカリ金属または、アルカリ土類金属などの材料を用いて形成される陰極１６１８とからなっている。バンク１６１５は陽極１６１６の端部を覆うように設けられ、この部分で陰極と陽極とがショートすることを防ぐために設けている。
【０１１５】
ＥＬ層１６１７上には、ＥＬ素子の陰極１６１８が設けられる。陰極１６１８としては、仕事関数の小さいマグネシウム（Ｍｇ）、リチウム（Ｌｉ）もしくはカルシウム（Ｃａ）を含む材料を用いる。好ましくは、ＭｇＡｇ（Ｍｇ：Ａｇ＝１０：１で混合した材料）からなる電極を用いればよい。他にも、ＭｇＡｇＡｌ電極、ＬｉＡｌ電極、またＬｉＦＡｌ電極があげられる。
【０１１６】
ＥＬ層１６１７と陰極１６１８とでなる積層体は、各画素で個別に形成する必要があるが、ＥＬ層１６１７は極めて水分に弱いため、通常のフォトリソグラフィ技術を用いることができない。また、アルカリ金属を用いて作製される陰極１６１８は容易に酸化されてしまう。従って、メタルマスク等の物理的名マスク材料を用いて、真空蒸着法、スパッタ法、プラズマＣＶＤ法等の気相法で選択的に形成することが好ましい。また、陰極１６１８上に外部の水分等から保護するための保護電極を積層してもよい。保護電極としては、アルミニウム（Ａｌ）、銅（Ｃｕ）、もしくは銀（Ａｇ）を含む低抵抗な材料を用いることが望ましい。
【０１１７】
少ない消費電力で高い輝度を得るためには、ＥＬ層を形成する材料に三重項励起子（トリプレット）により発光する有機化合物（以下、トリプレット化合物という）を用いる。なお、シングレット化合物とは一重項励起のみを経由して発光する化合物を指し、トリプレット化合物とは三重項励起を経由して発光する化合物を指す。
【０１１８】
トリプレット化合物としては、以下の論文に記載の有機化合物が代表的な材料として挙げられる。（１）T.Tsutsui, C.Adachi, S.Saito, Photochemical Processes in Organized Molecular Systems, ed.K.Honda, (Elsevier Sci.Pub.,Tokyo,1991)p.437. （２）M.A.Baldo, D.F.O'Brien, Y.You, A.Shoustikov, S.Sibley, M.E.Thompson, S.R.Forrest, Nature 395 (1998)p.151.（３）M.A.Baldo, S.Lamansky, P.E.Burrows, M.E.Thompson, S.R.Forrest, Appl.Phys.Lett.,75 (1991) p.4. （４）T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T.Watanabe, T.Tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.
【０１１９】
上記トリプレット化合物は、シングレット化合物よりも発光効率が高く、同じ発光輝度を得るにも動作電圧（ＥＬ素子を発光させるに要する電圧）を低くすることが可能である。
【０１２０】
図２８では、スイッチング用ＴＦＴ１６３０をマルチゲート構造とし、電流制御用ＴＦＴ１６３１にはゲート電極とオーバーラップするＬＤＤ領域を設けている。多結晶シリコンを用いたＴＦＴは高い動作速度を示すが、ホットキャリア注入などの劣化も起こりやすい。そのため、図２８のように画素内において機能に応じて構造の異なるＴＦＴ（オフ電流の十分に低いスイッチング用ＴＦＴと、ホットキャリア注入に強い電流制御用ＴＦＴ）を形成することは、高い信頼性を有し良好な画像表示が可能な動作性能が高い表示装置を作製する上で非常に有効である。以上のようにして作製されるアクティブマトリクス駆動の発光装置を完成させることができる。また、ソース線１６０８および電流供給線１６１０に補助配線を形成することで、比較的大きな電流を供給する電流供給線１６１０の抵抗率を効果的に低減することができる。
【０１２１】
（実施例９）
本発明を実施して形成されたＣＭＯＳ回路や画素部は様々な半導体装置（アクティブマトリクス型液晶表示装置、アクティブマトリクス型ＥＬ表示装置）に用いることができる。即ち、それら半導体装置を表示部に組み込んだ電気器具全てに本発明を実施できる。
【０１２２】
その様な電気器具としては、パーソナルコンピュータ、ディスプレイなどが挙げられる。それらの一例を図１５に示す。
【０１２３】
図１５（Ａ）はパーソナルコンピュータであり、本体２００１、画像入力部２００２、表示部２００３、キーボード２００４等を含む。本発明を表示部２００３に適用することができる。
【０１２４】
図１５（Ｂ）はプログラムを記録した記録媒体（以下、記録媒体と呼ぶ）を用いるプレーヤーであり、本体２４０１、表示部２４０２、スピーカ部２４０３、記録媒体２４０４、操作スイッチ２４０５等を含む。なお、このプレーヤーは記録媒体としてＤＶＤ（Ｄｉｇｔｉａｌ Ｖｅｒｓａｔｉｌｅ Ｄｉｓｃ）、ＣＤ等を用い、音楽鑑賞や映画鑑賞やゲームやインターネットを行うことができる。本発明は表示部２４０２に適用することができる。
【０１２５】
図１５（Ｃ）はディスプレイであり、本体３１０１、支持台３１０２、表示部３１０３等を含む。本発明は表示部３１０３に適用することができる。本発明のディスプレイは特に大画面化した場合において有利であり、対角１０インチ以上（特に３０インチ以上）のディスプレイには有利である。
【０１２６】
以上の様に、本発明の適用範囲は極めて広く、あらゆる分野の電気器具に適用することが可能である。また、本実施例の電気器具は実施例１〜４のどのような組み合わせからなる構成を用いても実現することができる。
【０１２７】
【発明の効果】
本発明によれば、画面の大型化に伴う配線の抵抗率の上昇、配線終端での信号伝達の遅れ等の問題を解決することができる。また、本発明の構造を適応することで開口率の向上と、半導体装置の動作性能や信頼性の向上を実現することができる。
【図面の簡単な説明】
【図１】 本発明の半導体装置の画素部の上面を示す図。
【図２】 本発明の半導体装置の画素部の上面を示す図。
【図３】 本発明の半導体装置の作製工程を示す図。
【図４】 本発明の半導体装置の作製工程を示す図。
【図５】 本発明の半導体装置の作製工程を示す図。
【図６】 本発明の半導体装置の作製工程を示す図。
【図７】 本発明の半導体装置を示す図。
【図８】 本発明の半導体装置を示す図。
【図９】 本発明の半導体装置の作製工程を示す図。
【図１０】 本発明の半導体装置の作製工程を示す図。
【図１１】 本発明の半導体装置の作製工程を示す図。
【図１２】 本発明の半導体装置の作製工程を示す図。
【図１３】 本発明の半導体装置の作製工程を示す図。
【図１４】 本発明の半導体装置の作製工程を示す図。
【図１５】 本発明の半導体装置の作製工程を示す図。
【図１６】 ＴＦＴを上面から観察した図面代用写真。
【図１７】 配線の抵抗の測定結果を示す図。
【図１８】 配線のシート抵抗の測定結果を示す図。
【図１９】 静止画を表示した半導体装置を示す図面代用写真。
【図２０】 本発明の半導体装置の作製工程を示す図。
【図２１】 本発明の半導体装置の作製工程を示す図。
【図２２】 本発明の半導体装置の作製工程を示す図。
【図２３】 本発明の実施の一例を示す図。
【図２４】 本発明の実施の一例を示す図。
【図２５】 本発明の実施の一例を示す図。
【図２６】 加熱処理をした基板のシート抵抗測定結果を示す図。
【図２７】 加熱処理をした基板の応力測定結果を示す図。
【図２８】 本発明を用いて作製されたアクティブマトリクス基板を用いた発光装置の一例を示す図。
【図２９】 本発明の加熱処理を行う装置の一例を示す図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a circuit manufactured by a thin film transistor (hereinafter referred to as TFT) formed over an insulator and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device typified by a liquid crystal display device in which a pixel portion and a drive circuit provided around the pixel portion are provided on the same substrate, and an electric appliance using the liquid crystal display device as a display portion.
[0002]
[Prior art]
Development of a semiconductor device including a large-area integrated circuit formed using a thin film transistor (hereinafter referred to as TFT) using a semiconductor film with a thickness of about several nanometers to several hundred nanometers formed over a substrate having an insulating surface is in progress. In addition, TFTs having a crystalline silicon film (typically polysilicon film) as an active layer (hereinafter referred to as polysilicon TFT) have high field effect mobility, so that various functional circuits can be formed. There is a lot of attention. An active matrix liquid crystal display device is known as a typical example of a semiconductor device that has been developed.
[0003]
In a pixel circuit of an active matrix liquid crystal display device, a TFT (referred to as a pixel TFT. In this specification, a pixel TFT refers to a source region and a source region formed in a pixel portion. A field-effect transistor having a semiconductor layer having a channel formation region sandwiched between drain regions and a gate electrode.), And each pixel TFT is provided with a pixel electrode.
[0004]
Applications of such active matrix type liquid crystal display devices continue to expand, and demands for higher definition, higher aperture ratio, and higher reliability are increasing year by year as the screen size increases. At the same time as the above requirements, there are also increasing demands for improving productivity and reducing costs.
[0005]
[Problems to be solved by the invention]
However, in the active matrix liquid crystal display device, the number of wirings and the length thereof are increased due to the increase in size and definition of the screen, so that the resistivity of the wiring is increased and the signal transmission to the terminal of the wiring is delayed. This is a cause of signal writing failure or gradation failure to the pixel.
[0006]
As the number of scanning lines increases, the charging time for the liquid crystal becomes shorter. Therefore, it is necessary to reduce the time constant (resistance × capacitance) of the gate line and to respond at high speed. For example, when the specific resistance of the material forming the gate line is 100 μΩcm, the screen size is almost limited to the 6-inch class, but when it is 3 μΩcm, display up to the 27-inch class is possible.
[0007]
Although it is conceivable to use aluminum (Al) or copper (Cu) as a wiring material, these metals have the drawback of poor corrosion resistance and heat resistance. Therefore, it is not always preferable to form the gate electrode of the TFT with such a material, and it is not easy to introduce such a material into the TFT manufacturing process. Of course, it is possible to form the wiring with other conductive materials, but there is no material as low as aluminum (Al) or copper (Cu), and a large-screen liquid crystal display device could not be manufactured. .
[0008]
In addition to the increase in resistivity due to the increase in the wiring, the cause of the increase in the resistivity of the wiring is an increase in the resistance of the wiring due to the oxidation of the wiring material accompanying the heat treatment. If the heat treatment for activation is performed with the gate electrode and the source line made of the heat-resistant conductive film exposed, the surface of the wiring made of the same material as the gate electrode and the gate electrode is oxidized, and the resistivity further increases. There is a problem that it ends up.
[0009]
In order to solve this problem, in order to prevent oxidation of the gate electrode during the activation process, a protective film covering the gate electrode and the like is provided for activation, and the protective film is removed after the activation process is completed. Later steps can also be performed. However, in this method, not only the number of steps is increased, but it is difficult to secure a selection ratio between the insulating film and the heat-resistant conductive film by etching for removing the protective film.
[0010]
In addition, wiring resistance reduction technology is also required. As a method for reducing the wiring resistance, first, a method of increasing the line width of the wiring has been considered. However, the aperture ratio is reduced by increasing the line width. In addition, the method of increasing the film thickness of the wiring increases the level difference, and the coverage deteriorates when forming an insulating film or a metal film for electrodes after the wiring is formed, resulting in poor yield. Occurs.
[0011]
The above-described problems in a semiconductor device having a plurality of integrated circuits such as the above active matrix liquid crystal display device have become apparent as the required performance increases.
[0012]
Accordingly, the present invention provides a processing method and a manufacturing method for realizing a reduction in resistance of a wiring accompanying a large size and high definition in a manufacturing method of a semiconductor device typified by an active matrix liquid crystal display device manufactured using a TFT. The purpose is to do.
[0013]
[Means for solving the problems]
In view of the above-described problems, in the present invention, the oxygen concentration is specifically 20 ppm or less (preferably 10 ppm) in a low oxygen atmosphere in which the gate electrode and the source line are not oxidized so that it is not necessary to form a protective film. The following activation process is performed in a nitrogen gas or rare gas atmosphere.
In order to lower the oxygen concentration in the atmosphere, first, after exhausting with a rotary pump and a mechanical booster pump in order to reduce the oxygen concentration as much as possible, the pressure in the furnace is reduced to atmospheric pressure or less (preferably 10,000 Pa or less) as a nitrogen atmosphere It is preferable to perform heat treatment for activation.
[0014]
Further, in the method for manufacturing a semiconductor device of the present invention, heat (400 to 700 ° C., typically 500 to 700 ° C.) applied in the step of activating the impurity element added to the semiconductor layer as a material for the gate electrode and the source line. A heat resistant conductive film (typically a conductive film made of an element of W, Ta, Mo, Ti, Cr, Si, or Nb, or a conductive film made of an alloy containing the element) that can withstand 600 ° C.) Yes. However, since these heat-resistant conductive films have high resistivity, signal delay due to wiring resistance becomes a problem when the wiring length is long. Therefore, a wiring made of a material having a lower resistivity than the heat-resistant conductive film forming the gate electrode and the source line is used as an auxiliary wiring for reducing the resistivity of the source line so that it follows the source line after the activation process. And it is provided in contact. By providing this auxiliary wiring, the resistivity of the entire source line can be reduced. Note that in this specification, wiring provided to reduce the resistivity of the entire source line is referred to as auxiliary wiring.
Further, since the auxiliary wiring is in direct contact with the source line without providing an insulating film between the layers, the step of forming a contact hole for connecting the source line and the auxiliary wiring can be reduced.
[0015]
As described above, by implementing the present invention, it is possible to suppress an increase in resistivity due to oxidation accompanying heat treatment of the bus line (particularly source line) material, and to keep the bus line resistivity small. Therefore, it is possible to reduce image quality defects due to signal delay.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
A pixel portion of a semiconductor device disclosed in the present invention will be described with reference to FIGS. 1 and 2 are top views of the pixel portion.
[0017]
A base insulating film 11 is formed on the substrate 10. (FIG. 1B) Next, a semiconductor film is formed on the base insulating film 11 and patterned into a desired shape to form semiconductor layers 12 and 13. The semiconductor layer 12 becomes an active layer of the pixel TFT, and the semiconductor layer 13 functions as a lower electrode of the storage capacitor.
[0018]
A gate electrode 15, a storage capacitor line 15 a, and a source line 16 made of the same heat resistant conductive film as the gate electrode are formed on the gate insulating film 14 (FIG. 1B) covering the semiconductor layers 12 and 13. Provided on the same surface. In the present specification, the term “on the same plane” refers to the case where the layer formed immediately below the A layer and the B layer is an α layer formed in the same process, for example. In the embodiment of the present invention, since the layer formed immediately below the gate electrode 15 and the source line 16 is the gate insulating film 14 formed in the same process, the gate electrode 15 (the storage capacitor line 15a ) And the source line 16 can be said to be provided on the same surface. Further, as can be confirmed from the top view, the gate electrode of the pixel in the n-th row has a structure that also serves as the storage capacitor line in the (n−1) -th row. Note that as a typical heat-resistant conductive film, a conductive film made of any element of Ta, W, Ti, Mo, Cr, Nd, or Nb, or a conductive film made of an alloy containing the element as a main component. Or the electrically conductive film which consists of a compound which has the said element as a main component is mention | raise | lifted. In addition, a semiconductor film typified by a polycrystalline silicon film doped with an element belonging to Group 13 or 15 of the periodic table as an impurity element, or an AgPdCu alloy made of silver (Ag), palladium (Pd), and copper (Cu). A conductive film may be used. The source line 16 has a laminated structure of a first conductive film (TaN in the embodiment of the present invention) 16a and a second conductive film (W in the embodiment of the present invention) 16b having a smaller outer shape than the first conductive film. It is. Note that the gate electrode 15 also has a stacked structure of a first conductive film and a second conductive film like the source line 16.
Since the source line 16 is made of the same heat-resistant conductive film as the gate electrode that places importance on heat resistance, there is a problem that the resistivity is high. Therefore, for the purpose of reducing the resistivity of the entire source line, an auxiliary wiring 17 made of a material having a resistivity lower than that of the source line 16 is provided along and in contact with the source line. As shown in FIG. 1A, the auxiliary wiring 17 is provided on and in contact with the source line 16 without being separated from the source line 16 and without an insulating film between layers as shown in FIG. It has been.
[0019]
When the steps up to here are completed, an inorganic interlayer insulating film 18 and an organic interlayer insulating film 19 are provided (FIG. 2B). Next, the pixel electrode 20 formed is made of indium tin oxide (ITO) or indium zinc oxide alloy (InO) as a transparent conductive film. ₂ O _Three -ZnO), zinc oxide (ZnO), and a conductive film such as zinc oxide (ZnO: Ga) to which gallium (Ga) is added in order to increase the transmittance and conductivity of visible light can be applied. The pixel electrode 20 is provided on the auxiliary wiring 17 so as to overlap with the inorganic interlayer insulating film 18 and the organic interlayer insulating film 19. Therefore, the effective pixel area can be increased.
The gate line 21 and the wiring 22 are formed on the same surface. The gate line 21 is connected to the gate electrode 15, and the wiring 22 is formed to electrically connect the semiconductor layer 12 and the source line 16. The wiring 22 is formed of a laminated film of a Ti film having a thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a thickness of 500 nm.
The Ti film is laminated for the purpose of preventing Al from diffusing into Si when the semiconductor layer (Si) 12 and the wiring 22 are connected, and the pixel electrode (ITO) 20 and Al. This is to prevent electrical corrosion caused by direct contact.
[0020]
Note that a reflective display device can be provided by providing a film made of a conductive material having reflectivity as the pixel electrode 20.
[0021]
A method for manufacturing a semiconductor device according to the present invention having the above-described structure will be described in the following examples.
[0022]
Example 1
Here, a method for simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driver circuit provided around the pixel portion on the same substrate will be described in detail with reference to FIGS. .
[0023]
First, in this embodiment, a substrate 100 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is used. The substrate 100 is not limited as long as it is a light-transmitting substrate, and a quartz substrate may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.
[0024]
Next, a base film 101 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 100. Although a two-layer structure is used as the base film 101 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 101, a plasma CVD method is used, and SiH _Four , NH _Three And N ₂ A silicon oxynitride film 101a formed using O as a reaction gas is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm). In this embodiment, a silicon oxynitride film 101a having a film thickness of 50 nm (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) is formed. Next, as the second layer of the base film 101, a plasma CVD method is used, and SiH _Four And N ₂ A silicon oxynitride film 101b formed using O as a reaction gas is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm). In this embodiment, a silicon oxynitride film 101b (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) having a thickness of 100 nm is formed.
[0025]
Next, semiconductor layers 102 to 105 are formed over the base film. The semiconductor layers 102 to 105 are formed by forming a semiconductor film having an amorphous structure by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like), and then a known crystallization treatment (laser crystallization method, heat A crystalline semiconductor film obtained by performing a crystallization method or a thermal crystallization method using a catalyst such as nickel) is formed by patterning into a desired shape. The semiconductor layers 102 to 105 are formed to have a thickness of 25 to 80 nm (preferably 30 to 60 nm). In this example, a 55 nm amorphous silicon film was formed by plasma CVD, and then a solution containing nickel was held on the amorphous silicon film. This amorphous silicon film is dehydrogenated (500 ° C., 1 hour), then thermally crystallized (550 ° C., 4 hours), and then laser annealing treatment is performed to improve crystallization. Thus, a crystalline silicon film was formed. Then, the semiconductor layers 102 to 105 were formed by patterning the crystalline silicon film using a photolithography method.
[0026]
When a crystalline semiconductor film is formed by laser crystallization, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO _Four A laser can be used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. Crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz and the laser energy density is 100 to 400 mJ / cm. ² (Typically 200-300mJ / cm ² ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 10 kHz, and the laser energy density is 300 to 600 mJ / cm. ² (Typically 350-500mJ / cm ² ) Then, when the laser beam condensed linearly with a width of 100 to 1000 μm, for example, 400 μm is irradiated over the entire surface of the substrate, the superposition ratio (overlap ratio) of the linear laser light at this time is 80 to 98%. Good.
[0027]
Next, a gate insulating film 106 that covers the semiconductor layers 102 to 105 is formed. The gate insulating film 106 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by plasma CVD or sputtering. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 110 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0028]
When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.
[0029]
In addition, after forming the semiconductor layers 102 to 105, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT. Note that the impurity addition step may be performed either before the crystallization step of the semiconductor film, after the crystallization step of the semiconductor film, or after the step of forming the gate insulating film 106.
[0030]
Next, as illustrated in FIG. 3A, a first conductive film 107 with a thickness of 20 to 100 nm and a second conductive film 108 with a thickness of 100 to 400 nm are stacked over the gate insulating film 106. In this example, a first conductive film 107 made of a TaN film with a thickness of 30 nm and a second conductive film 108 made of a W film with a thickness of 370 nm were stacked. The TaN film was formed by sputtering, and was sputtered in a nitrogen-containing atmosphere using a Ta target. The W film was formed by sputtering using a W target. In addition, tungsten hexafluoride (WF ₆ It can also be formed by a thermal CVD method using In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in the W film, the crystallization is hindered and the resistance is increased. Therefore, in this embodiment, sufficient consideration is given so that impurities are not mixed from the gas phase during film formation by sputtering using a target of high purity W (purity 99.9% to 99.9999%). By forming a W film, a resistivity of 9 to 20 μΩcm could be realized.
[0031]
In this embodiment, the first conductive film 107 is TaN and the second conductive film 108 is W. However, there is no particular limitation, and all of them are Ta, W, Ti, Mo, Al, Cu, Cr, Nd. You may form with the electrically conductive film consisting of the element chosen from these, the electrically conductive film consisting of the alloy containing the said element, or the electrically conductive film consisting of the compound containing the said element. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, arsenic, or boron may be used. Further, an AgPdCu alloy may be used. In addition, the first conductive film is formed using a tantalum (Ta) film, the second conductive film is formed using a W film, the first conductive film is formed using a titanium nitride (TiN) film, and the second conductive film is formed. The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of an Al film, and the first conductive film is formed of a tantalum nitride (TaN) film. The second conductive film may be a combination of Cu films.
[0032]
Next, resist masks 109 to 113 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, and CF is used as an etching gas. _Four And Cl ₂ Etching was performed by generating 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa to generate plasma. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ Under the etching conditions in which is mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.
[0033]
By the first etching process, the ends of the first conductive film and the second conductive film are tapered due to the effect of the bias voltage applied to the substrate side. The angle of this taper portion is 15 to 45 °. In this way, the W film and the TaN film are etched to form the gate electrodes (A) 114 to 116 (first conductive films 114a to 116a and second conductive films 114b to 116b), the storage capacitor line 117, and the source line. A conductive film 118 is formed. Reference numeral 119 denotes a gate insulating film, and a region not covered with the gate electrodes (A) 114 to 116, the storage capacitor line 117, and the conductive film 118 serving as the source line is etched by about 20 to 50 nm to form a thinned region. Is done.
[0034]
Next, a second etching process is performed without removing the masks 109 to 113 made of resist. CF as etching gas _Four And Cl ₂ And O ₂ Etching was performed by generating 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa to generate plasma. 20 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process.
[0035]
The W film is anisotropically etched by the second etching process, and the TaN film as the first conductive film is slightly etched at a slower etching rate than the W film, and the gate electrodes (B) 120 to 122 (first Conductive films 120a to 122a and second conductive films 120b to 122b), a storage capacitor line 123, and a source line (B) 124 are formed. (In the present specification, the portion indicated simply as the source line indicates the source line in the shape of the source line (B).)
[0036]
Next, a first doping process is performed. In the doping process, an impurity element imparting n-type conductivity is doped by an ion doping method or an ion implantation method. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used, but here phosphorus (P) was used. Using the gate electrodes (B) 120 to 122 and the storage capacitor line 123 as masks, doping is performed so that impurities are also added to the semiconductor layers below the tapered portions of the first conductive films 120a to 123a. As a result, the impurity concentration is 5 × 10 5. ¹⁷ ~ 5x10 ¹⁹ atoms / cm ^Three N-type impurity regions 125a to 128a and n-type impurity regions 125b to 128b having impurity concentrations slightly lower than those of 125a to 128a are formed. (Fig. 4 (A))
[0037]
Next, after removing the masks 109 to 113, new masks 129 and 130 made of resist are formed and a second doping process is performed. Using the masks 129 and 130 as masks, the impurity concentration is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three N-type impurity regions (hereinafter, n-type impurity regions (A)) 131 and 132 are formed. At this time, n-type impurity regions 125c and 127c that do not overlap with the gate electrode are determined. When the length of the region in the channel length direction is 1.5 μm or more, the off-current is reduced.
[0038]
Through the steps so far, the semiconductor layers 102 and 104 forming the n-channel TFT have an impurity concentration of 1 × 10 6. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three N-type impurity regions (hereinafter referred to as n-type impurity regions (A)) 131 and 132, and the impurity concentration is 5 × 10 ¹⁷ ~ 5x10 ¹⁹ atoms / cm ^Three N-type impurity regions (hereinafter referred to as n-type impurity regions (B)) 125c and 127c, and n-type impurity regions (hereinafter referred to as n-type impurity regions (C) having impurity concentrations slightly lower than those of 125c and 127c. )) 125d and 127d are formed. Note that the impurity regions 131 and 132 formed here serve as a source region or a drain region of the n-channel TFT. (Fig. 4 (B))
[0039]
The n-type impurity regions (B) 125c and 127c function as LDD regions of the n-channel TFT. In addition, the impurity element added to the n-type impurity regions (B) 125c and 127c is added mainly in the later gettering step in order to reduce the nickel concentration in the semiconductor layer to be a channel formation region. Then, after removing the resist masks 129 and 130, new resist masks 133 and 134 are formed, and a third doping process is performed.
[0040]
By this third doping treatment, an impurity element imparting p-type conductivity is added to the semiconductor layer that becomes the active layer of the p-channel TFT, and p-type impurity regions 135 to 138 are formed. Using gate electrodes (B) 121 and 123 as masks, p-type impurity elements 135 to 138 are formed in a self-aligned manner by adding a p-type impurity element. All regions have an impurity concentration of 2 × 10 ²⁰ ~ 2x10 ^{twenty one} atoms / cm ^Three By performing the doping treatment so as to become, no problem arises because it functions as the source region and drain region of the p-channel TFT. (Fig. 4 (C))
[0041]
Thereafter, a step of activating the impurity element added to each semiconductor layer is performed. In this activation step, a thermal annealing method using a furnace is performed. As conditions for the thermal annealing method, the oxygen concentration was 20 ppm or less, preferably exhausted by a rotary pump and a mechanical booster pump, and reduced to 0.1 Pa or less to reduce the oxygen concentration to 10 ppm or less (more preferably 2 ppm or less). Thereafter, nitrogen is introduced so that the pressure in the furnace is kept at 10000 Pa or less, and it may be carried out at 400 to 700 ° C., typically 500 to 600 ° C. In this embodiment, the activation treatment is performed at 600 ° C. for 4 hours. Went. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0042]
In addition, since W used as a material for the gate electrode may be increased in resistance due to oxidation, the oxygen concentration in the atmosphere is first reduced to reduce the oxygen concentration in the atmosphere, and then the treatment is performed in a nitrogen atmosphere. May be. In this example, the treatment was performed under the reduced pressure conditions shown in Table 1 below. After reducing the oxygen concentration by exhausting the furnace to 0.1 Pa or less with a rotary pump and mechanical booster pump, N ₂ The furnace pressure was kept at 5 l / min and the pressure in the furnace was kept at atmospheric pressure or lower, preferably 10000 Pa or lower (180 Pa in this embodiment), and heat treatment for activating the impurity elements was performed. Nitrogen gas used in the atmosphere contains O as an impurity. ₂ , CO, CO ₂ , CH _Four , H ₂ And H ₂ O is a highly pure nitrogen gas of 1 ppb or less. For comparison, normal heat treatment conditions are also shown.
[0043]
Furthermore, in the present embodiment, the heat treatment is performed by an apparatus as shown in FIG. 29, but a vacuum pump (rotary pump 2 and mechanical booster pump 3) is used on the exhaust side of the furnace 5 where the treatment is performed. Since backflow can be prevented, heat treatment in a low oxygen atmosphere can be performed more effectively.
[0044]
[Table 1]

[0045]
Here, FIG. 27 shows the result of measuring the change in stress after the heat treatment. It can be seen that in the heat treatment under normal pressure conditions, the stress shifts to the compression side and W is oxidized. Conversely, when heat treatment is performed under reduced pressure, the stress shifts to the tension side.
[0046]
Next, FIG. 26 shows the results of measuring changes in sheet resistance with respect to a substrate processed under normal pressure conditions (described in the graph) and a substrate processed under reduced pressure conditions. A substrate processed under normal pressure conditions has a high sheet resistance after processing. This is presumably because the W surface was oxidized by oxygen contained in the furnace atmosphere. Conversely, a substrate that has been processed under reduced pressure conditions has a reduced sheet resistance after processing. Since the oxygen concentration in the furnace atmosphere can be reduced by the treatment under the conditions shown in Table 1, it is considered that there is a considerable effect in preventing oxidation of W.
[0047]
In this embodiment, at the same time as the activation treatment, nickel used as a catalyst during crystallization is gettered to the n-type impurity regions (A) (131, 132) and becomes a semiconductor mainly serving as a channel formation region. The nickel concentration in the layer is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0048]
Since this activation process is performed in a low-concentration oxygen atmosphere, the activation process can be performed before the inorganic interlayer insulating film is formed. However, if the wiring material used is vulnerable to heat, activation processing should be performed after an inorganic interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like. Is preferred.
[0049]
After the activation process, the auxiliary wiring 140 is formed along and in contact with the source line. The auxiliary wiring is made of a conductive film made of a material having a lower resistivity than the conductive film forming the gate electrode, for example, a conductive film made of any element of Al, Cu, or Ag, or a conductive film made of an alloy containing the element. . Further, in order to protect the wiring made of a conductive film having a low resistivity (referred to as wiring (A)), the conductive film made of any element of Ta, W, Ti, Mo, Cr, Nd, or Nb, A wiring (B) made of a conductive film made of an alloy containing the element as a main component or a conductive film made of a compound containing the element as a main component may be formed on the wiring (A).
As described above, by providing the auxiliary wiring made of the low resistance material along and in contact with the source line, the resistivity of the entire source line can be suppressed. Note that a cross-sectional view taken along the line AA ′ in FIG. 11 is shown in FIG.
[0050]
Next, an inorganic interlayer insulating film 141 covering the entire surface is formed. The inorganic interlayer insulating film 646 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method. (FIG. 5C) A cross-sectional view taken along line AA ′ in FIG. 11 is shown in FIG.
[0051]
After the inorganic interlayer insulating film 141 was formed, heat treatment was performed at 410 ° C. for 1 hour in a nitrogen atmosphere. Note that heat treatment may be performed in a nitrogen atmosphere containing hydrogen. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the interlayer insulating film. As another means of hydrogenation, furnace annealing in a hydrogen atmosphere or plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0052]
In the case where a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the hydrogenation. A step of activating the impurity element added to each semiconductor layer is performed.
[0053]
Next, an organic interlayer insulating film 142 made of an organic resin material is formed on the inorganic interlayer insulating film 141. In this example, acrylic resin was used. Next, patterning is performed to form contact holes that reach the impurity regions.
[0054]
Thereafter, a transparent conductive film is formed with a thickness of 80 to 120 nm and patterned to form the pixel electrode 150. Transparent conductive films include indium tin oxide (ITO), indium zinc oxide alloy (In ₂ O _Three -ZnO) and zinc oxide (ZnO) are also suitable materials, and zinc oxide added with gallium (Ga) (ZnO: Ga) can be suitably used to increase the transmittance and conductivity of visible light. .
[0055]
Next, wirings 156 to 162 that electrically connect the impurity regions are formed. Note that these wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a thickness of 500 nm. The wiring 159 electrically connects the impurity region 132 and the source line 124. (Fig. 5)
[0056]
In this embodiment, the contact hole is formed and the wiring is provided so as to directly connect the n-type impurity region (A) 132 and the source line 124, but the n-type impurity region (A) 132 and the auxiliary wiring 140 are provided. The wiring 159 may be provided so as to be directly connected, or the wiring 159 may be provided so as to directly connect the n-type impurity region (A) 132, the auxiliary wiring 140, and the source line 124.
[0057]
In this embodiment, an example in which a transparent conductive film is used as the pixel electrode is described; however, when a pixel electrode is formed using a conductive material having reflectivity, a reflective display device can be manufactured. In that case, the pixel electrode can be formed at the same time in the step of manufacturing the electrode, and as the material of the pixel electrode, a film containing Al or Ag as a main component or a material having excellent reflectivity of the laminated film can be used. desirable.
[0058]
As described above, the driver circuit 206 including the n-channel TFT 201 and the p-channel TFT 202, and the pixel portion 207 including the pixel TFT 203 and the storage capacitor 204 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0059]
In the n-channel TFT semiconductor layer formed in this embodiment, when the widths of the n-type impurity region (B) and the n-type impurity region (C) are W1 and W2, respectively, W1 is 0.5 to 1.. 5 μm and W2 can be formed to have a width of 1.0 to 3.0 μm. Note that the resist masks 129 and 130 may be formed so that W1 + W2 is 1.5 to 4.5 μm (preferably 2.0 to 3.0 μm). According to the manufacturing process shown in this embodiment, the n-type impurity region (B) and the n-type impurity region (C) can be formed long, which is effective in reducing the off-state current.
[0060]
(Example 2)
In this embodiment, a process for manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 7 is used for the description. 2 is a cross-sectional view (source line) with respect to the line AA ′ in the top view of FIG. 2, and FIG. 7B is a cross-sectional view (pixel TFT) with respect to the line BB ′ of FIG. A cross-sectional view (retention capacitor) with respect to the region of line B ′ and the line CC ′ of FIG. 2 shows the region of line CC ′ of FIG.
[0061]
First, after obtaining the active matrix substrate in the state of FIG. 6 according to the first embodiment, an alignment film 180 is formed on the active matrix substrate of FIG. 6 and a rubbing process is performed. In this embodiment, before the alignment film 180 is formed, columnar spacers for maintaining the distance between the substrates are formed at desired positions by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0062]
Next, a counter substrate 181 is prepared. The counter substrate is provided with a color filter in which a colored layer 186 and a light shielding layer 187 are arranged corresponding to each pixel. Further, a light shielding layer 189 is also provided in the drive circuit portion. A planarizing film 188 is provided to cover the color filter and the light shielding layer 189. Next, a counter electrode 182 made of a transparent conductive film was formed on the planarizing film 188 in the pixel portion, an alignment film 183 was formed on the entire surface of the counter substrate, and a rubbing process was performed.
[0063]
Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are attached to each other with a sealant 184. A filler is mixed in the sealing material 184, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 185 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 185. In this way, the active matrix liquid crystal display device shown in FIG. 7 is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Furthermore, a polarizing plate or the like was appropriately provided using a known technique. And FPC was affixed using the well-known technique.
[0064]
The structure of the liquid crystal display panel thus obtained will be described with reference to the top view of FIG. The same reference numerals are used for portions corresponding to those in FIG.
[0065]
The top view shown in FIG. 8A shows a pixel portion, a driving circuit, an external input terminal 210 to which an FPC (Flexible Printed Circuit Board: Flexible Printed Circuit) is pasted, and wiring for connecting the external input terminal to the input portion of each circuit. An active matrix substrate 211 and a counter substrate 181 provided with a color filter or the like are attached to each other with a sealant 184 interposed therebetween.
[0066]
A light shielding layer 189a is provided on the counter substrate side so as to overlap with the gate line side driver circuit 206a, and a light shielding layer 189b is formed on the counter substrate side so as to overlap with the source line side driver circuit 206b. In addition, the color filter 212 provided on the counter substrate side over the pixel portion 207 is provided with a light shielding layer and a colored layer of each color of red (R), green (G), and blue (B) corresponding to each pixel. It has been. When actually displaying, a color display is formed with three colors of a red (R) colored layer, a green (G) colored layer, and a blue (B) colored layer. It shall be arbitrary.
[0067]
Here, the color filter 212 is provided on the counter substrate for colorization; however, there is no particular limitation. When an active matrix substrate is manufactured, a color filter may be formed on the active matrix substrate.
[0068]
In addition, a light-shielding layer is provided between adjacent pixels in the color filter to shield light other than the display area. Here, the light shielding layers 189a and 189b are also provided in the region covering the driving circuit. However, the region covering the driving circuit is covered with a cover when the liquid crystal display device is incorporated later as a display unit of an electric appliance. It is good also as a structure which does not provide a light shielding layer. Further, when the active matrix substrate is manufactured, a light shielding layer may be formed on the active matrix substrate.
[0069]
Further, without providing the light-shielding layer, the light-shielding layer is appropriately disposed between the counter substrate and the counter electrode so as to be shielded from light by stacking a plurality of colored layers constituting the color filter. Or the drive circuit may be shielded from light.
[0070]
Further, an FPC composed of a base film 213 and a wiring 214 is bonded to the external input terminal with an anisotropic conductive resin 215. Furthermore, the mechanical strength is increased by the reinforcing plate.
[0071]
FIG. 8B is a cross-sectional view of the external input terminal 207 shown in FIG. Reference numeral 217 denotes a wiring made of a conductive film formed to form the pixel electrode 156. Since the outer diameter of the conductive particles 216 is smaller than the pitch of the wirings 217, if the amount dispersed in the adhesive 215 is appropriate, it is electrically connected to the corresponding wiring on the FPC side without short-circuiting with the adjacent wirings. Can be formed.
[0072]
The liquid crystal display panel manufactured as described above can be used as a display portion of various electric appliances.
[0073]
(Example 3)
After the activation step shown in FIG. 5A of Embodiment 1, the auxiliary wiring 301 (consisting of the wiring (A) 301a and the wiring (B) 301b) is formed. (FIG. 9B) The wiring (A) is made of a conductive film made of any one of Al, Cu, and Ag having a low resistivity, or a conductive film made of an alloy containing the element. The wiring (B) protects the wiring (A) from the etching solution when the contact hole is formed in the inorganic interlayer insulating film and the organic interlayer insulating film, and (2) connects the semiconductor layer and the auxiliary wiring. It is formed for the purposes of (1) and (2) to prevent electrical corrosion from occurring due to contact between the wiring formed on the same surface as the gate line and the wiring (A). The wiring (B) includes a conductive film made of any element of Ta, W, Ti, Mo, Cr, Nd, or Nb, a conductive film made of an alloy containing the element as a main component, or a compound containing the element as a main component. It consists of the electrically conductive film which consists of. Each conductive film for forming the wiring (A) and the wiring (B) is formed and etched to form an auxiliary wiring 301 along and in contact with the entire surface of the source wiring.
[0074]
Next, an inorganic interlayer insulating film 302 is formed so as to cover the auxiliary wiring 301 and the gate electrode (the first conductive film 140 and the second conductive film 126), and is 410 ° C. in a nitrogen atmosphere containing about 3% hydrogen. A step of hydrogenating the semiconductor layer is performed by heat treatment for 1 hour. After the hydrogenation step, an organic interlayer insulating film 303 is formed thereon. (Figure 9 (C))
A silicon oxynitride film or a silicon nitride film may be used as the inorganic interlayer insulating film 302, and an acrylic resin film is used as the organic interlayer insulating film 303.
[0075]
Thereafter, contact holes reaching the impurity regions and the wiring (B) 301b are formed.
Next, after forming the pixel electrode 150 along the process shown in FIG. 6 of the first embodiment, the gate line 164 and the wirings 156 to 162 are formed, and the active matrix substrate is completed. (FIGS. 10 and 11) Note that the wiring 159 electrically connects the auxiliary wiring 301 and the impurity region 132, and the wiring 159 is provided in direct contact with the auxiliary wiring 301 and the impurity region 132.
[0076]
The active matrix substrate completed in this embodiment can be combined with Embodiment 2 to produce an active matrix liquid crystal display device.
[0077]
(Example 4)
When the process up to the step of FIG. 4C of Example 1 is performed, an inorganic interlayer insulating film 401 is formed. The inorganic interlayer insulating film 401 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film with a thickness of 150 nm is formed by a plasma CVD method. It is not limited to a silicon oxynitride film, and an insulating film containing other silicon may be used as a single layer or a stacked structure.
[0078]
Next, a step of activating the impurity element added to each semiconductor layer is performed. (FIG. 12A) This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 20 ppm or less, preferably exhausted to 0.1 Pa or less by a rotary pump and a mechanical booster pump to reduce the oxygen concentration to 10 ppm or less, and in a reduced pressure state (atmospheric pressure or less, preferably 10,000 Pa or less). What is necessary is just to perform by 400-700 degreeC by nitrogen atmosphere, typically 500-600 degreeC, and an activation process is performed by the heat processing for 4 hours at 600 degreeC in a present Example.
[0079]
At the same time as the activation treatment, nickel used as a catalyst in crystallization is gettered to an impurity region containing a high concentration of phosphorus, so that the nickel concentration in the semiconductor layer that mainly serves as a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0080]
Further, in order to hydrogenate the semiconductor layer, heat treatment was performed at 410 ° C. for 1 hour in a nitrogen atmosphere. Note that heat treatment may be performed in an atmosphere containing hydrogen. Next, each conductive film for forming the wiring (A) and the wiring (B) is formed on the inorganic interlayer insulating film 401, etched, and auxiliary wiring 402 along the source wiring through the inorganic interlayer insulating film 401. (Wiring (A) 402a and wiring (B) 402b) are formed. (FIG. 12B) The wiring (A) is made of a conductive film made of any element of Al, Cu, and Ag having a low resistivity, or a conductive film made of an alloy containing the element. The wiring (B) includes a conductive film made of any element of Ta, W, Ti, Mo, Cr, Nd, or Nb, a conductive film made of an alloy containing the element as a main component, or a compound containing the element as a main component. It consists of the electrically conductive film which consists of.
[0081]
Next, an organic interlayer insulating film 403 made of an organic insulating material is formed so as to cover the auxiliary wiring 402. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed. Next, patterning is performed to form contact holes that reach the impurity region source lines 205 and the auxiliary wiring 402 (wiring (B) 402b) (FIG. 13).
[0082]
In this embodiment, the source line 205 is formed under the inorganic interlayer insulating film 401, and the auxiliary wiring 402 is formed along the source line 205 via the inorganic interlayer insulating film 401. It is also possible to form a low resistance wiring by forming the auxiliary wiring 402 on the inorganic interlayer insulating film 401 (on the same surface as the gate electrode) without forming 205.
[0083]
Thereafter, contact holes reaching the impurity regions and the wiring (B) 301b are formed. Next, the pixel electrode 150, the gate line 164, and the wirings 156 to 162 are formed in accordance with a process subsequent to the process illustrated in FIG. 6 of Embodiment 1, and an active matrix substrate can be manufactured. The wiring 159 electrically connects the source line 205, the auxiliary wiring 402, and the impurity region 132, and the wiring 159 is provided so as to be in direct contact with the source line 205 and the auxiliary wiring 402. (Fig. 13)
[0084]
As described above, the driver circuit 206 including the n-channel TFT 201 and the p-channel TFT 202 and the pixel portion 207 including the pixel TFT 203 and the storage capacitor 204 can be formed over the same substrate. (Fig. 14)
[0085]
This embodiment can be combined with Embodiment 2 to form an active matrix liquid crystal display device.
[0086]
(Example 5)
In this embodiment, a method for making TFTs according to required characteristics will be described. In addition, the same code | symbol is used about the process same as Example 1. FIG.
[0087]
According to the steps of Embodiment 1, a base film 101 and an amorphous silicon film are formed on the substrate 100, and a crystallization step is performed to obtain an island-shaped semiconductor layer. Next, the island-shaped semiconductor layers 502 to 506 are covered with a gate insulating film 507. The gate insulating film 507 is formed by a plasma CVD method or a sputtering method. The thickness is 40 to 150 nm, and the insulating film containing silicon is used. Needless to say, this gate insulating film 507 can be formed using a single layer or a stacked layer of an insulating film containing silicon.
[0088]
A conductive film (A) 508 with a thickness of 20 to 100 nm and a conductive film (B) 509 with a thickness of 100 to 400 nm are formed over the gate insulating film 507. The conductive film (A) and the conductive film (B) are formed from an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing these elements as main components. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus (P) may be used. In this embodiment, TaN is used as the conductive film (A) 508, and W is used as the conductive film (B) 509. (Fig. 20 (B))
[0089]
Next, resist masks 510 to 516 are formed by photolithography, and a first etching process is performed to form a gate electrode and a capacitor wiring. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, and CF is used as an etching gas. _Four , Cl ₂ And O ₂ Each gas flow rate ratio is 25/25/10 (SCCM), and 500 W of RF (13.56 MHz) power is applied to the coil electrode at a pressure of 1 Pa to generate plasma and perform etching. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied.
[0090]
Thereafter, the resist masks 510 to 516 are not removed and the second etching condition is changed, and the etching gas is changed to CF. _Four And Cl ₂ Each gas flow rate ratio is 30/30 (SCCM), 500 W of RF (13.56 MHz) power is applied to the coil type electrode at a pressure of 1 Pa, plasma is generated, and etching is performed for about 30 seconds. I do. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ Under the second etching condition in which is mixed, the W film and the TaN film are etched to the same extent, and the first shape gate electrode and wirings 517 to 523 are formed.
[0091]
The first doping process is performed without removing the masks 510 to 516 made of resist. An impurity element imparting n-type conductivity (hereinafter referred to as an n-type impurity element) is added to the semiconductor layers 502 to 506. The doping process may be performed by an ion doping method or an ion implantation method. As the n-type impurity element, an element belonging to Group 15 of the periodic table, typically an element such as phosphorus (P) or arsenic (As) is used. In this case, the n-type impurity concentration is 1 × 10 10 in a self-aligning manner using the first shape gate electrode and the capacitor wirings 517 to 521 as a mask. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three N-type impurity region (n ⁺ ) 524a to 524e are formed. (Figure 20 (C))
[0092]
Next, a second etching process is performed with the resist masks 510 to 516 as they are. CF as etching gas _Four , Cl ₂ And O ₂ Each gas flow ratio is 20/20/20 (SCCM), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.0 Pa to generate plasma and perform etching. Do. On the substrate side (sample stage), 20 W of RF (13.56 MHz) power is applied and etching is performed for about 80 seconds. As a result, second-shaped gate electrodes and wirings 525 to 531 are formed.
[0093]
Next, the masks 510 to 516 made of resist are used as they are, and the second shape gate electrode and the capacitor wirings 525 to 529 are used as masks. The n shape is also formed below the second shape conductive layer (A) (TaN film). A second doping process is performed so that the type impurity element is added. By this treatment, the n-type impurity region (n ⁺ ) The n-type impurity element concentration is 1 × 10 in the channel formation region side. ¹⁸ ~ 1x10 ¹⁹ atoms / cm ^Three N-type impurity region (n ^- ) 532a to 532e are formed. (FIG. 21 (A))
[0094]
Next, the masks 510 to 516 made of resist are removed, masks 533 and 534 made of resist covering the subsequent n-channel TFT and the subsequent pixel TFT are formed, and a third doping process is performed. A p-type impurity element is added to the semiconductor layers of the later first p-channel TFT and the later second p-channel TFT using the second shape gate electrodes 526 and 527 and the capacitor wiring 529 as a mask. A p-type impurity region (p ⁺ ) 535a to 535c and a p-type impurity region (p ^- ) 535d to 535f are formed. In this embodiment, the p-type impurity region is diborane (B ₂ H ₆ ) Using an ion doping method. An n-type impurity element is added to the semiconductor layer of the p-channel TFT in advance, but the doping process is performed so that the concentration of the p-type impurity element added in the third doping process is higher. Thus, no problem arises because it functions as a source region and a drain region of a later p-channel TFT. Note that in this specification, an n-channel TFT later refers to a TFT that is in the manufacturing process and functions as an n-channel TFT after completion. Applicable to any TFT. (Fig. 21 (B))
[0095]
Next, the n-channel TFT and the first p-channel TFT of the driver circuit are covered with resist masks 536 and 537, and a third etching process is performed. The etching gas is Cl ₂ The gas flow rate is 80 (SCCM), 350 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa, plasma is generated, and etching is performed for about 30 seconds. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Thus, gate electrodes 538 and 539 having a third shape, a capacitor wiring 540, and wirings 541 and 542 are formed. (Fig. 21 (C))
[0096]
Through the above steps, impurity regions are formed in the respective semiconductor layers.
[0097]
Thereafter, a step of activating the impurity element added to each semiconductor layer is performed. In this activation step, a thermal annealing method using a furnace is performed. As conditions for the thermal annealing method, the oxygen concentration is 20 ppm or less, preferably exhausted to 0.1 Pa or less by a rotary pump and a mechanical booster pump, the oxygen concentration is 10 ppm or less, and a reduced pressure state (atmospheric pressure or less, preferably 10,000 Pa or less). ) In a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 600 ° C. In this example, the activation treatment was performed by heat treatment at 550 ° C. for 4 hours. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0098]
In this example, simultaneously with the activation treatment, nickel used as a catalyst during crystallization is converted into an n-type impurity region (n ⁺ ) (524a, 524c, 524d), and the nickel concentration in the semiconductor layer mainly serving as a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0099]
Since this activation process is performed in a reduced-pressure atmosphere with a reduced oxygen concentration, the activation process can be performed before the inorganic interlayer insulating film is formed. However, if the wiring material used is vulnerable to heat, activation processing should be performed after an inorganic interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like. Is preferred.
[0100]
After the activation step, an auxiliary wiring 543 is formed along and in contact with the source line. The auxiliary wiring is made of a conductive film made of a material having a lower resistivity than the conductive film forming the gate electrode, for example, a conductive film made of any element of Al, Cu, or Ag, or a conductive film made of an alloy containing the element. . Further, in order to protect the wiring made of a conductive film having a low resistivity (referred to as wiring (A)), the conductive film made of any element of Ta, W, Ti, Mo, Cr, Nd, or Nb, A wiring (B) made of a conductive film made of an alloy containing the element as a main component or a conductive film made of a compound containing the element as a main component may be formed on the wiring (A).
As described above, by providing the auxiliary wiring made of the low resistance material along and in contact with the source line, the resistivity of the entire source line can be suppressed. Note that a cross-sectional view taken along line AA ′ in FIG. 11 is shown in FIG.
[0101]
Next, an inorganic interlayer insulating film 141 covering the entire surface is formed, and the active matrix substrate can be completed according to the steps from FIG.
[0102]
The active matrix substrate completed in this embodiment can be combined with Embodiment 2 to produce an active matrix liquid crystal display device.
[0103]
(Example 5)
A gate electrode made of the first conductive film and the second conductive film is formed in a shape as shown in FIGS. A wiring may be formed. According to this embodiment, since the gate insulating film thinned by the etching process is sandwiched between the semiconductor layer and the storage capacitor wiring, a storage capacitor having a larger capacity can be formed as compared with the methods of Embodiments 1 to 4. .
[0104]
(Example 6)
The pixel TFT shown in FIG. 16B is a drawing-substituting photograph in which a TFT that can be manufactured using Example 1 is observed from the upper surface. FIG. 16A is a drawing-substituting photograph in which a pixel TFT in which an auxiliary wiring for lowering the resistance value is not formed as in the conventional case is observed from the upper surface.
[0105]
FIG. 17 shows the result of measuring the resistance value of the source line for FIGS. 16A and 16B. Comparing the resistance value of FIG. 16B in which an Al—Nd wiring is formed to reduce resistance to the source line and the resistance value of FIG. 16A of the conventional example, the resistance value is ½ from FIG. It can be confirmed that it is reduced to the extent.
[0106]
In addition, the sheet resistance value (Ω / □) of the source line was measured. FIG. 18 shows the measurement results. The sheet resistance value is calculated by taking 10 measurement points, varying the voltage by 0.001 (V) from 0 to 0.1 (V), and measuring the current at each voltage. The source line is designed as shown in the following table.
[0107]
[Table 2]

[0108]
As shown in FIG. 18, by using the present invention, the sheet resistance value of the source line could be reduced to about 1/4 of the conventional value.
[0109]
(Example 7)
FIG. 19 shows a drawing-substituting photograph in which a state in which a still image is actually displayed is observed.
[0110]
(Example 8)
In this embodiment, a process for manufacturing an active matrix light-emitting device from the active matrix substrate manufactured in Embodiment 4 will be described with reference to FIGS. FIG. 28B is a top view of the pixel portion, and FIG. 28A is a cross-sectional view taken along the line AA ′.
[0111]
A glass substrate is used as the substrate 1601. On the glass substrate 1601, an n-channel TFT and a p-channel TFT are formed in a driver circuit (not shown), and a switching TFT 1630 and a current control TFT 1631 are formed in the pixel portion 1632. These TFTs are formed using semiconductor layers 1603 and 1604, a gate insulating film 1605, gate electrodes 1606 and 1607, and the like.
[0112]
As the base insulating film 1602 formed over the substrate 1601, a silicon oxynitride film, a silicon nitride film, or the like is formed to a thickness of 50 to 200 nm. The inorganic interlayer insulating film 1618 is formed from a silicon nitride film or a silicon oxynitride film, and the organic interlayer insulating film 1619 is formed from acrylic or polyimide.
[0113]
An EL element having an anode, a cathode, and a layer containing an organic compound (hereinafter referred to as an EL layer) from which electroluminescence is obtained is formed on the TFT of the pixel portion. Note that luminescence in an organic compound includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state, and includes both of them. .
[0114]
The EL element is provided after the bank 1615 is formed using an organic resin such as acrylic or polyimide, preferably a photosensitive organic resin so as to cover the wiring. In this embodiment, the EL element 1620 is formed using a material such as an anode 1616 made of ITO (indium tin oxide), an EL layer 1617, an alkali metal such as MgAg or LiF, or an alkaline earth metal. And a cathode 1618. The bank 1615 is provided so as to cover the end portion of the anode 1616, and is provided to prevent a short circuit between the cathode and the anode at this portion.
[0115]
On the EL layer 1617, a cathode 1618 of an EL element is provided. As the cathode 1618, a material containing magnesium (Mg), lithium (Li), or calcium (Ca) having a low work function is used. Preferably, an electrode made of MgAg (material mixed at Mg: Ag = 10: 1) may be used. Other examples include MgAgAl electrodes, LiAl electrodes, and LiFAl electrodes.
[0116]
A stacked body including the EL layer 1617 and the cathode 1618 needs to be formed individually for each pixel. However, since the EL layer 1617 is extremely sensitive to moisture, a normal photolithography technique cannot be used. Further, the cathode 1618 manufactured using an alkali metal is easily oxidized. Therefore, it is preferable to selectively form by a vapor phase method such as a vacuum deposition method, a sputtering method, or a plasma CVD method using a physical name mask material such as a metal mask. Further, a protective electrode for protecting from external moisture or the like may be stacked on the cathode 1618. As the protective electrode, it is desirable to use a low-resistance material containing aluminum (Al), copper (Cu), or silver (Ag).
[0117]
In order to obtain high luminance with low power consumption, an organic compound that emits light by triplet excitons (triplet compound) is used as a material for forming the EL layer. The singlet compound refers to a compound that emits light only through singlet excitation, and the triplet compound refers to a compound that emits light via triplet excitation.
[0118]
As the triplet compound, organic compounds described in the following papers can be mentioned as typical materials. (1) T. Tsutsui, C. Adachi, S. Saito, Photochemical Processes in Organized Molecular Systems, ed. K. Honda, (Elsevier Sci. Pub., Tokyo, 1991) p.437. (2) MABaldo, DFO ' Brien, Y.You, A.Shoustikov, S.Sibley, METhompson, SRForrest, Nature 395 (1998) p.151. (3) MABaldo, S.Lamansky, PEBurrows, METhompson, SRForrest, Appl.Phys.Lett., 75 (1991) p.4. (4) T. Tsutsui, M.-J. Yang, M. Yahiro, K. Nakamura, T. Watanabe, T. Tsuji, Y. Fukuda, T. Wakimoto, S. Mayaguchi, Jpn .Appl.Phys., 38 (12B) (1999) L1502.
[0119]
The triplet compound has higher luminous efficiency than the singlet compound, and the operating voltage (voltage required for causing the EL element to emit light) can be lowered to obtain the same light emission luminance.
[0120]
In FIG. 28, the switching TFT 1630 has a multi-gate structure, and the current control TFT 1631 is provided with an LDD region overlapping with the gate electrode. A TFT using polycrystalline silicon exhibits a high operation speed, but is also susceptible to deterioration such as hot carrier injection. Therefore, as shown in FIG. 28, forming TFTs having different structures (switching TFTs with sufficiently low off-state current and TFTs for current control resistant to hot carrier injection) having different structures in accordance with the functions in the pixel has high reliability. It is very effective in manufacturing a display device having a high operation performance capable of having a good image display. An active matrix light-emitting device manufactured as described above can be completed. Further, by forming auxiliary wirings in the source line 1608 and the current supply line 1610, the resistivity of the current supply line 1610 that supplies a relatively large current can be effectively reduced.
[0121]
Example 9
The CMOS circuit and the pixel portion formed by implementing the present invention can be used for various semiconductor devices (active matrix liquid crystal display devices and active matrix EL display devices). That is, the present invention can be applied to all electric appliances in which these semiconductor devices are incorporated in a display portion.
[0122]
Such electric appliances include personal computers and displays. An example of these is shown in FIG.
[0123]
FIG. 15A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention can be applied to the display portion 2003.
[0124]
FIG. 15B shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.
[0125]
FIG. 15C illustrates a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like. The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0126]
As described above, the scope of application of the present invention is extremely wide and can be applied to electric appliances in various fields. Moreover, the electric appliance of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-4.
[0127]
【The invention's effect】
According to the present invention, it is possible to solve problems such as an increase in the resistivity of a wiring accompanying an increase in screen size and a delay in signal transmission at the end of the wiring. Further, by applying the structure of the present invention, it is possible to improve the aperture ratio and improve the operation performance and reliability of the semiconductor device.
[Brief description of the drawings]
FIG. 1 is a diagram showing an upper surface of a pixel portion of a semiconductor device of the present invention.
FIG. 2 is a diagram showing an upper surface of a pixel portion of a semiconductor device of the present invention.
FIGS. 3A to 3D are diagrams illustrating a manufacturing process of a semiconductor device of the present invention. FIGS.
4A to 4C illustrate a manufacturing process of a semiconductor device of the present invention.
FIGS. 5A to 5D are diagrams illustrating a manufacturing process of a semiconductor device of the present invention. FIGS.
6A and 6B illustrate a manufacturing process of a semiconductor device of the present invention.
FIG 7 illustrates a semiconductor device of the present invention.
FIG. 8 shows a semiconductor device of the present invention.
FIGS. 9A to 9C are diagrams illustrating a manufacturing process of a semiconductor device of the present invention. FIGS.
10A to 10C illustrate a manufacturing process of a semiconductor device of the present invention.
11A to 11C illustrate a manufacturing process of a semiconductor device of the present invention.
12A to 12C illustrate a manufacturing process of a semiconductor device of the present invention.
13A to 13C illustrate a manufacturing process of a semiconductor device of the present invention.
FIGS. 14A to 14C are diagrams illustrating a manufacturing process of a semiconductor device of the present invention. FIGS.
FIGS. 15A to 15C are diagrams illustrating a manufacturing process of a semiconductor device of the present invention. FIGS.
FIG. 16 is a drawing substitute photograph in which a TFT is observed from above.
FIG. 17 is a diagram showing a measurement result of wiring resistance;
FIG. 18 is a diagram showing a measurement result of sheet resistance of wiring.
FIG. 19 is a drawing substitute photograph showing a semiconductor device displaying a still image.
20 is a diagram showing a manufacturing process of a semiconductor device of the present invention. FIG.
FIG. 21 illustrates a manufacturing process of a semiconductor device of the present invention.
FIGS. 22A to 22C are diagrams illustrating a manufacturing process of a semiconductor device of the present invention. FIGS.
FIG. 23 is a diagram showing an example of implementation of the present invention.
FIG. 24 is a diagram showing an example of implementation of the present invention.
FIG. 25 is a diagram showing an example of implementation of the present invention.
FIG. 26 is a diagram showing a sheet resistance measurement result of a heat-treated substrate.
FIG. 27 is a diagram showing a stress measurement result of a heat-treated substrate.
FIG. 28 shows an example of a light-emitting device using an active matrix substrate manufactured using the present invention.
FIG. 29 is a diagram showing an example of an apparatus for performing heat treatment of the present invention.

Claims (16)

A semiconductor layer formed on an insulating surface;
A gate insulating film formed on the insulating surface and the semiconductor layer;
A gate electrode and a source wiring formed on the gate insulating film;
Auxiliary wiring directly formed on the source wiring;
An interlayer insulating film formed in contact with the gate electrode and the auxiliary wiring;
Contact holes formed in the interlayer insulating film;
A gate wiring formed on the interlayer insulating film and in contact with the gate electrode through the contact hole, comprising:
On the gate insulating film, the gate electrode and the source wiring are simultaneously formed using a conductive film made of an element containing Ta, W, Ti, Mo, Cr, Nd or Nb, or an alloy containing the element,
Adding an impurity element to the semiconductor layer;
Heat treatment for activating the impurity element is performed in an atmosphere having an oxygen concentration of 20 ppm or less and a reduced pressure,
On the source wiring, the auxiliary wiring is directly formed using a material having a lower resistivity than the conductive film,
Thereafter, the interlayer insulating film, the contact hole, and the gate wiring are sequentially formed. A semiconductor layer formed on an insulating surface;
A gate insulating film formed on the insulating surface and the semiconductor layer;
A gate electrode and a source wiring formed on the gate insulating film;
A first auxiliary wiring formed directly on the source wiring;
A second auxiliary wiring formed directly on the first auxiliary wiring;
An interlayer insulating film formed in contact with the gate electrode and the second auxiliary wiring;
Contact holes formed in the interlayer insulating film;
A gate wiring formed on the interlayer insulating film and in contact with the gate electrode through the contact hole, comprising:
On the gate insulating film, the gate electrode and the source wiring are simultaneously formed using a conductive film made of an element containing Ta, W, Ti, Mo, Cr, Nd or Nb, or an alloy containing the element,
Adding an impurity element to the semiconductor layer;
Heat treatment for activating the impurity element is performed in an atmosphere having an oxygen concentration of 20 ppm or less and a reduced pressure,
The first auxiliary wiring is directly formed on the source wiring using a material having a lower resistivity than the conductive film,
Forming the second auxiliary wiring for protecting the first auxiliary wiring directly on the first auxiliary wiring;
Thereafter, the interlayer insulating film, the contact hole, and the gate wiring are sequentially formed. In claim 2,
The method for manufacturing a semiconductor device, wherein the second auxiliary wiring is formed using a conductive film containing any element of Ta, W, Ti, Mo, Cr, Nd, or Nb. In any one of Claims 1 thru | or 3,
The method for manufacturing a semiconductor device, wherein the interlayer insulating film has a stacked structure. A semiconductor layer formed on an insulating surface;
A gate insulating film formed on the insulating surface and the semiconductor layer;
A gate electrode and a source wiring formed on the gate insulating film;
A first interlayer insulating film formed in contact with the gate electrode and the source wiring;
An auxiliary wiring that is formed directly on the first interlayer insulating film and extends along the source wiring through the first interlayer insulating film;
A second interlayer insulating film formed in contact with the first interlayer insulating film and the auxiliary wiring;
A contact hole formed in the second interlayer insulating film;
A gate wiring formed on the second interlayer insulating film and in contact with the gate electrode through the contact hole;
On the gate insulating film, the gate electrode and the source wiring are simultaneously formed using a conductive film made of an element containing Ta, W, Ti, Mo, Cr, Nd or Nb, or an alloy containing the element,
Adding an impurity element to the semiconductor layer;
Forming the first interlayer insulating film;
Heat treatment for activating the impurity element is performed in an atmosphere having an oxygen concentration of 20 ppm or less and a reduced pressure,
The auxiliary wiring is directly formed on the first interlayer insulating film using a material having a lower resistivity than the conductive film,
Thereafter, the second interlayer insulating film, the contact hole, and the gate wiring are sequentially formed. A semiconductor layer formed on an insulating surface;
A gate insulating film formed on the insulating surface and the semiconductor layer;
A gate electrode and a source wiring formed on the gate insulating film;
A first interlayer insulating film formed in contact with the gate electrode and the source wiring;
A first auxiliary wiring that is formed directly on the first interlayer insulating film and extends along the source wiring through the first interlayer insulating film;
A second auxiliary wiring formed directly on the first auxiliary wiring;
A second interlayer insulating film formed in contact with the first interlayer insulating film and the second auxiliary wiring;
A contact hole formed in the second interlayer insulating film;
A gate wiring formed on the second interlayer insulating film and in contact with the gate electrode through the contact hole;
On the gate insulating film, the gate electrode and the source wiring are simultaneously formed using a conductive film made of an element containing Ta, W, Ti, Mo, Cr, Nd or Nb, or an alloy containing the element,
Adding an impurity element to the semiconductor layer;
Forming the first interlayer insulating film;
Heat treatment for activating the impurity element is performed in an atmosphere having an oxygen concentration of 20 ppm or less and a reduced pressure,
Forming the first auxiliary wiring directly on the first interlayer insulating film using a material having a lower resistivity than the conductive film;
Forming the second auxiliary wiring for protecting the first auxiliary wiring directly on the first auxiliary wiring;
Thereafter, the second interlayer insulating film, the contact hole, and the gate wiring are sequentially formed. In claim 6,
The method for manufacturing a semiconductor device, wherein the second auxiliary wiring is formed using a conductive film containing any element of Ta, W, Ti, Mo, Cr, Nd, or Nb. In any one of Claim 5 thru | or 7,
The method for manufacturing a semiconductor device, wherein the second interlayer insulating film has a stacked structure. In any one of Claims 1 thru | or 8,
A method for manufacturing a semiconductor device, wherein the material having a lower resistivity than the conductive film is a conductive film containing any element of Al, Cu, or Ag. In any one of Claims 1 thru | or 9,
The method for manufacturing a semiconductor device, wherein the heat treatment is thermal annealing at 400 ° C. to 700 ° C. In any one of Claims 1 thru | or 9,
The method for manufacturing a semiconductor device, wherein the heat treatment is laser annealing or rapid thermal annealing. In any one of Claims 1 to 11,
The method for manufacturing a semiconductor device, wherein the reduced-pressure atmosphere is a nitrogen atmosphere of 10,000 Pa or less. In any one of Claims 1 to 12,
The semiconductor is characterized in that the reduced-pressure atmosphere is an atmosphere in which nitrogen is introduced so that the oxygen concentration is reduced to 20 ppm or less by reducing the oxygen concentration to 0.1 Pa or less, and then maintained at 10000 Pa or less. Device fabrication method. In any one of Claims 1 thru / or Claim 13,
The method for manufacturing a semiconductor device, wherein the gate insulating film has a stacked structure. In any one of Claims 1 thru | or 14,
The method for manufacturing a semiconductor device, wherein the conductive film has a stacked structure. In any one of Claims 1 to 15,
The method for manufacturing a semiconductor device, wherein the impurity element is an impurity element imparting n-type or p-type conductivity.

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