JP4314475B2 - IC for receiver - Google Patents

Description

  The present invention relates to a receiver IC and an AGC circuit.

  As a superheterodyne receiver, there is a so-called low IF receiver in which the intermediate frequency is made considerably lower than the reception frequency by bringing the local oscillation frequency close to the reception frequency. There is also a so-called direct conversion system in which the intermediate frequency is made zero by making the local oscillation frequency equal to the reception frequency. These receivers convert the received signal into a pair of intermediate frequency signals orthogonal to each other and improve image characteristics by phase processing.

  FIG. 5 shows an example of a low-IF receiver. That is, a reception signal SRX having a target reception frequency is taken out from the electronic tuning antenna tuning circuit 11, and this reception signal SRX is supplied to the pair of mixer circuits 13A and 13B through the high-frequency amplifier 12.

  In addition, the local oscillation circuit 31 is configured by a PLL, and two signals SLOA and SLOB having a frequency close to the frequency of the reception signal SRX (for example, a frequency higher by 55 kHz when receiving a medium wave broadcast) and phases different from each other by 90 ° These signals SLOA and SLOB are supplied to the mixer circuits 13A and 13B as local oscillation signals.

  Thus, in the mixer circuits 13A and 13B, the received signal SRX is frequency-converted into a pair of intermediate frequency signals SIFA and SIFB by the local oscillation signals SLOA and SLOB. In this case, the intermediate frequency signals SIFA and SIFB include a signal component of the intended reception frequency (original signal component) and a signal component of the image frequency. The signal components of the reception frequency are called intermediate frequency signals SIFA and SIFB, and the signal components of the image frequency are called image components.

  Since the local oscillation signals SLOA and SLOB have a phase difference of 90 °, the intermediate frequency signals SIFA and SIFB are orthogonal with a phase difference of 90 °, and the image components are the intermediate frequency signals SIFA and SIFB. It is orthogonal with a phase difference of 90 ° in the opposite relationship.

  Further, a part of the control voltage supplied to the variable capacitance diode of the VCO (not shown) of the PLL is extracted from the PLL constituting the local oscillation circuit 31, and this control voltage is supplied to the tuning circuit 11 as a tuning voltage. Thus, tuning with respect to the received signal SRX is realized.

  Then, the intermediate frequency signals SIFA and SIFB from the mixer circuits 13A and 13B are supplied to the amplitude phase correction circuit 14 to correct the relative amplitude error and phase error of the intermediate frequency signals SIFA and SIFB, and this error is corrected. The intermediate frequency signals SIFA and SIFB are supplied to the phase shift circuits 16A and 16B through the bandpass filters 15A and 15B. For example, the phase shift is performed so that the intermediate frequency signals SIFA and SIFB are in phase and the image components are out of phase. Is done. Then, the intermediate frequency signals SIFA and SIFB after the phase shift are supplied to and added to the arithmetic circuit 17, and the intermediate frequency signal SIF from which the image component is canceled is extracted from the arithmetic circuit 17.

  Subsequently, the intermediate frequency signal SIF is supplied to the digital processing circuit 20 through the intermediate frequency amplifier 18 and the band pass filter 19 and A / D converted, and predetermined digital processing corresponding to the format of the received signal SRX. And audio signals L and R are extracted.

  The amplifiers 12 and 18 are variable gain amplifiers, and a part of the intermediate frequency signal SIF is supplied from the bandpass filter 19 to the AGC voltage forming circuit 32 to form the AGC voltage VAGC. The AGC voltage VAGC is the amplifier. 18 is supplied as a gain control signal, and AGC is performed for the intermediate frequency stage. Further, the AGC voltage VAGC is supplied as a gain control signal to the high-frequency amplifier 12 through the adding circuit 34, and AGC is performed for the high-frequency stage.

  Further, the intermediate frequency signals SIFA and SIFB output from the mixer circuits 13A and 13B are supplied to the over-input AGC voltage forming circuit 33, and the AGC voltage VOL is increased when the reception level becomes a specified value or more due to an interference wave or the like. Then, this AGC voltage VOL is supplied as a gain control signal to the high-frequency amplifier 12 through the adding circuit 34, and a delay AGC is performed on the high-frequency stage.

  The above receiving circuit is integrated into a one-chip IC except for the tuning circuit 11 and the resonance circuit of the PLL 31.

  Further, a microcomputer 40 is provided as a system control circuit, and an operation switch 41 such as a channel selection switch is connected to the microcomputer 40. When the switch 41 is operated, a predetermined control signal is supplied from the microcomputer 40 to the local oscillation circuit 31, the oscillation frequencies of the local oscillation signals SLOA and SLOB are changed, and the reception frequency is changed.

  Further, for example, when the power is turned on, a correction control signal is supplied from the microcomputer 40 to the correction circuit 14, and as described above, the image components included in the intermediate frequency signals SIFA and SIFB are canceled as inverse homologous amplitudes in the arithmetic circuit 17. Thus, the amplitude / phase correction circuit 14 is controlled.

  The above is an example of a low-IF receiver. This is a case where AGC is performed by analog processing.

  FIG. 6 shows an example in which AGC is performed by digital processing. That is, also in this example, the receiving system is configured in the same manner as in FIG. In the digital processing circuit 20, the AGC voltage VAGC is formed from the intermediate frequency signal SIF supplied thereto, and the output voltage of the AGC voltage forming circuit 33 is supplied to the digital processing circuit 20. Thus, in the digital processing circuit 20, the AGC voltages VAGC and VOL are formed by digital processing, and these AGC voltages VAGC and VOL are supplied to the amplifiers 18 and 12 as gain control signals.

For example, there are the following prior art documents.
JP 2001-36362 A

  In the receiver shown in FIG. 5, the gains of the amplifiers 12 and 18 are controlled by the AGC voltage VAGC so that the amplitude of the intermediate frequency signal SIF supplied to the digital processing circuit 20 is constant. When an interference wave exceeding the specified value is received, the gain of the amplifier 12 is controlled by the AGC voltage VOL, and the signal component of the interference wave is suppressed.

  However, depending on the reception situation, there is a case where it is desired to reduce the gain of the high frequency stage (high frequency amplifier 12) by the user's manual operation regardless of the AGC operation. In such a case, a control voltage that is changed by manual operation is superimposed on the AGC voltage VOL to reduce the gain of the high-frequency amplifier 12, or a variable attenuator circuit is provided in front of the high-frequency amplifier 12, and the variable attenuator circuit is provided. The gain of the high frequency stage is reduced by controlling from the outside.

In the superheterodyne receiver IC, an AGC can be performed for a high-frequency stage and a gain can be controlled manually.

In addition, it can be used for both high-frequency receivers that do not require manual gain control and receivers that require it, and external terminals for manual gain control. It is intended to provide an IC that does not need to be added.

In this invention,
Super heterodyne receiver IC,
A mixer circuit that converts a received signal into an intermediate frequency signal by a local oscillation signal and outputs the intermediate signal;
A variable gain circuit for changing the amplitude of the received signal;
A peak value detection circuit for comparing a level of the intermediate frequency signal with a predetermined reference voltage and detecting a peak value of a waveform portion exceeding the reference voltage in the intermediate frequency signal ;
A voltage follower to which the detection output of the peak value detection circuit is supplied;
A resistor connected to the output of this voltage follower;
An external terminal connected to the output terminal of the voltage follower and connected to a charge / discharge capacitor;
An amplifier that supplies the voltage obtained at the external terminal to the variable gain circuit as a control signal for the gain is integrated into an IC.
The voltage follower is
An operational amplifier to which the detection output of the peak value detection circuit is supplied;
The emitter follower transistor to which the output of this operational amplifier is supplied
Have
The resistor is connected to the emitter of the transistor as its load;
The output of the transistor is negatively fed back to the operational amplifier.
Configured,
The detection output of the peak value detection circuit charges the capacitor through the voltage follower, and the charging voltage of the capacitor is discharged through the resistor.
The voltage obtained at the external terminal by this charging and discharging is supplied as a control signal to the variable gain circuit through the amplifier, and AGC is performed on the received signal,
When a control voltage based on a manual operation is supplied to the external terminal, the control voltage is supplied as a control signal to the variable gain circuit through the amplifier so that the amplitude of the reception signal is controlled. IC
It is what.

  According to the present invention, it is possible to select various AGC operations important for the receiver and improve the reception performance. Moreover, a wider control form can be taken and it is easy to respond to various reception situations. Furthermore, the gain can be controlled manually from the outside.

FIG. 1 shows an embodiment of an AGC circuit according to the present invention, in which a portion surrounded by a chain line is integrated into a one-chip IC. The reception system is configured as described with reference to FIG.

  In this IC, the AGC voltage forming circuit 33 includes a pair of peak value detection circuits 33A and 33B, a low-pass filter 331, and a voltage follower 332. That is, the intermediate frequency signals SIFA and SIFB output from the mixer circuits 13A and 13B are supplied to the peak value detection circuits 33A and 33B, and the reference voltage VREF is supplied to the detection circuits 33A and 33B, from the detection circuits 33A and 33B. In the intermediate frequency signals SIFA and SIFB, voltages VOLA and VOLB indicating peak values of the waveform portions exceeding the reference voltage VREF are extracted as peak value detection voltages.

  The detection voltages VOLA and VOLB are supplied to and added to the low-pass filter 331, the intermediate frequency component is removed, and the output voltage V31 is supplied to the non-inverting input terminal of the operational amplifier Q31. This operational amplifier Q31 constitutes a voltage follower 332 together with an emitter follower transistor Q32.

  That is, the output terminal of the operational amplifier Q31 is connected to the base of the transistor Q32, the collector of the transistor Q32 is connected to the power supply terminal T31, the emitter thereof is connected to the ground terminal T33 through the resistor R32, and the inverting input of the operational amplifier Q31. Connected to the end. The voltage obtained at the emitter of the transistor Q32 is supplied as a gain control signal to the high-frequency amplifier 12 through the amplifier 333 and further through the adder circuit 34.

  Further, the emitter of the transistor Q32 is connected to the external terminal T32, and a capacitor C32 is externally connected between the terminal T32 and the terminal T33. Further, the collector and the emitter of the transistor Q33 are connected between the terminal T31 and the terminal T32, and a variable control voltage VCTL is supplied to the base thereof. The control voltage VCTL is a voltage for manually controlling the gain of the high-frequency amplifier 12, and is changed by a user operation. A predetermined power supply voltage VCC is supplied to the terminal T31.

  In this example, it is assumed that the high frequency amplifier 12 is a variable gain amplifier whose gain decreases as the control voltage (AGC voltage) increases, as shown in FIG.

  In such a configuration, for simplicity, it is first assumed that the transistor Q33 is off. When the voltage at the terminal T32 is a value V32, this voltage V32 is also the input voltage at the inverting input terminal of the operational amplifier Q31.

  Therefore, when V31> V32, the transistor Q32 is turned on, so that a charging current flows through the capacitor Q32 through the transistor Q32 as shown by the solid line A. Since this charging is performed through the transistor Q32 that is turned on, it is performed rapidly, and its charging time constant is short.

  Conversely, when V31 ≦ V32, the transistor Q32 is turned off, so that the charge of the capacitor C32 is discharged through the resistor R32 as indicated by the broken line B. This discharge time constant can be determined by the resistor R32 (and the capacitor C32), and is longer than the above charge time constant.

  Thus, the voltage V32 at the terminal T32 changes following the output voltage V31 of the low-pass filter 331, and the change attack time is short and the release time is long. At this time, the voltage V31 is output when the intermediate frequency signals SIFA and SIFB are larger than the reference voltage VREF.

  Therefore, this voltage V32 is nothing but the AGC voltage VOL. When the voltage V32 is supplied to the high-frequency amplifier 12 through the amplifier and adder circuit 34, the high-frequency amplifier 12 delays AGC. That is, AGC is performed when the reception level exceeds a specified value due to an interference wave or the like.

  In the AGC circuit of FIG. 1, the transistor Q33 is connected to the terminal T32, and the control voltage VCTL is supplied to the base thereof. Therefore, when VCTL> V32, the transistor Q33 is turned on and the capacitor C32 is charged by the voltage VCTL, so that V32 = VCTL. However, when VCTL ≦ V32, the transistor Q33 is turned off, so that the voltage VCTL does not act on the voltage V32.

  Therefore, if the user increases the control voltage VCTL by manual operation (VCTL> V32), the gain of the high-frequency amplifier 12 can be reduced regardless of the presence or absence of the interference wave. At this time, the voltage that controls the gain of the high-frequency amplifier 12 output from the transistor Q32 and the voltage that controls the gain of the high-frequency amplifier 12 through the transistor Q33 are controlled with priority given to the voltage that lowers the gain.

  Thus, according to the AGC circuit of FIG. 1, AGC can be performed on the high-frequency amplifier 12, and the gain of the high-frequency amplifier 12 can be reduced by manual operation.

  The IC of FIG. 1 can be used for both a receiver that does not require manual operation of gain and a receiver that allows manual operation, and in a receiver that allows manual operation. Only the transistor Q33 and the control voltage VCTL need be added. In addition, since the terminal T32 is originally necessary for connecting the capacitor C32 for the AGC time constant, it is not necessary to add an external terminal to the IC for manual operation of gain.

  In addition, since gain control by AGC and gain control by manual operation are given priority to control for lowering gain, it is possible to effectively reduce gain with respect to interference waves and the like. For example, the maximum gain can be limited, and AGC can be performed below the gain.

  In the AGC circuit shown in FIG. 3, the control voltage VCTL by manual operation is supplied to the terminal T32 through the amplifier Q34 having a gain of 1. Therefore, in this case, gain control by manual operation always takes priority. That is, the IC of FIG. 1 can control the gain of the high frequency stage by manual operation when the amplifier Q34 is externally attached.

  FIG. 4 shows a case where both analog processing AGC as shown in FIG. 5 and digital processing AGC as shown in FIG. 6 can be handled. In other words, the drain and source of the FET (Q35) are connected between the operational amplifier Q31 and the ground line of the IC. When the FET (Q35) is on, the operational amplifier Q31 operates effectively, but the FET (Q35) is off. In this case, the operation of the operational amplifier Q31 is stopped.

  Further, the mode switching voltage VMD is supplied to the external terminal T35 of the IC. The mode switching voltage VMD is “H” when analog processing AGC is performed, and is “L” when digital processing AGC is performed. The mode switching voltage VMD is supplied to the gate of the FET (Q35) through the terminal T35, and further supplied to the AND circuit Q37 through the inverter Q36. The output voltage V31 of the low-pass filter 331 is also supplied to the AND circuit Q37, and the output voltage V37 of the AND circuit Q37 is taken out to the external terminal T34.

  When analog processing AGC is performed, a capacitor C32 is connected to the terminals T32 and T33 as indicated by broken lines. Further, the control voltage VCTL is supplied to the terminal T32 through the amplifier Q34. Further, the mode switching voltage VMD is set to “H”. Note that the output voltage V37 of the terminal T34 is not used.

  Then, since VMD = "H", the FET (Q35) is turned on, and the operational amplifier Q31 operates effectively. Therefore, since this AGC circuit is equal to the AGC circuit of FIG. 1, AGC is performed as described above, and the gain of the high-frequency amplifier 12 can be suppressed by the control voltage VCTL.

  On the other hand, when performing AGC of digital processing, the microcomputer 40 equivalently realizes the control voltage VCTL and the amplifier Q34, and supplies the output voltage V37 of the terminal T34 to the microcomputer 40 as a control signal of the control voltage VCTL. To do. Further, the mode switching voltage VMD is set to “L”. At this time, the capacitor C32 is not connected.

  Then, since the FET (Q35) is turned off, the operational amplifier Q31 is deactivated, and the output voltage V31 of the low-pass filter 331 is not extracted from the transistor Q32. Therefore, analog processing AGC is not performed.

  In this case, since the output voltage V31 of the low-pass filter 331 is obtained when the amplitudes of the intermediate frequency signals SIFA and SIFB are larger than the reference voltage VREF, the output voltage V31 has an interference wave corresponding to the reference voltage VREF. It indicates whether it is larger or smaller than the specified value. At this time, since VMD = "L", the output voltage V31 is supplied to the microcomputer 40 through the AND circuit Q37.

  Then, when V37 (= V31) = “H”, the microcomputer 40 increases the control voltage VCTL to increase the AGC voltage VOL, and as a result, decreases the gain of the high-frequency amplifier 12. When the gain of the high-frequency amplifier 12 decreases, the voltage V31 decreases. When V37 = “L”, the microcomputer 40 holds the value at the control voltage VCTL at this time.

  Accordingly, the amplitude of the jamming wave is reduced to a level corresponding to the reference voltage VREF, and reception jamming due to the jamming wave is avoided.

  The response speed at this time can be arbitrarily set by software processing of the microcomputer 40, and can be set to an optimum speed corresponding to the disturbance changing speed.

  Thus, the AGC voltage forming circuit 33 of FIG. 4 can be applied to both AGC by analog processing and AGC by digital processing.

[List of abbreviations]
AGC: Automatic Gain Control
FET: Field Effect Transistor
IC: Integrated Circuit
IF: Intermediate Frequency
PIN: Positive-Intrinsic-Negative
PLL: Phase Locked Loop
VCO: Voltage Controlled Oscillator
Operational Amplifier: Operational Amplifier

It is a connection diagram showing one embodiment of the present invention. It is a characteristic view for demonstrating this invention. It is a connection diagram which shows the other form of this invention. It is a connection diagram which shows the other form of this invention. It is a systematic diagram which shows an example of this receiver. It is a systematic diagram which shows the other example of this receiver.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 12 ... High frequency amplifier, 13A and 13B ... Mixer circuit, 14 ... Amplitude phase correction circuit, 16A and 16B ... Phase shift circuit, 31 ... Local oscillation circuit, 32 and 33 ... AGC voltage formation circuit, 33A and 33B ... Peak value detection circuit , 40 ... microcomputer, 41 ... operation switch

Claims (2)

Super heterodyne receiver IC,
A mixer circuit that converts a received signal into an intermediate frequency signal by a local oscillation signal and outputs the intermediate signal;
A variable gain circuit for changing the amplitude of the received signal;
A peak value detection circuit for comparing a level of the intermediate frequency signal with a predetermined reference voltage and detecting a peak value of a waveform portion exceeding the reference voltage in the intermediate frequency signal ;
A voltage follower to which the detection output of the peak value detection circuit is supplied;
A resistor connected to the output of this voltage follower;
An external terminal connected to the output terminal of the voltage follower and connected to a charge / discharge capacitor;
An amplifier that supplies the voltage obtained at the external terminal to the variable gain circuit as a control signal for the gain is integrated into an IC.
The voltage follower is
An operational amplifier to which the detection output of the peak value detection circuit is supplied;
The emitter follower transistor to which the output of this operational amplifier is supplied
Have
The resistor is connected to the emitter of the transistor as its load;
The output of the transistor is negatively fed back to the operational amplifier.
Configured,
The detection output of the peak value detection circuit charges the capacitor through the voltage follower, and the charging voltage of the capacitor is discharged through the resistor.
The voltage obtained at the external terminal by this charging and discharging is supplied as a control signal to the variable gain circuit through the amplifier, and AGC is performed on the received signal,
When a control voltage based on a manual operation is supplied to the external terminal, the control voltage is supplied as a control signal to the variable gain circuit through the amplifier so that the amplitude of the reception signal is controlled. IC. The receiver IC circuit according to claim 1,
A first external terminal for controlling the operation of the voltage follower;
A second external terminal for taking out the detection output of the peak value detection circuit;
Have
When the capacitor for charging / discharging is connected to the external terminal and the first external terminal is set to a predetermined one level,
Operation of the voltage follower is permitted,
The detection output of the peak value detection circuit charges the capacitor through the voltage follower, and the charging voltage of the capacitor is discharged through the resistor.
The voltage obtained from the external terminal by this charging and discharging is supplied as a control signal to the variable gain circuit, and AGC is performed on the received signal,
When a control voltage based on a manual operation is supplied to the external terminal, the control voltage is supplied as a control signal to the variable gain circuit to control the amplitude of the reception signal.
When not connecting the capacitor for charging / discharging to the external terminal and setting the first external terminal to the predetermined other level,
The operation of the voltage follower is prohibited,
A receiver IC in which AGC is performed on the received signal by the control voltage when a control voltage formed based on a voltage output to the second external terminal is supplied to the external terminal .

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