JP2010252174A - Receiving device and tuner - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiving device and tuner, capable of achieving high-speed operation of the tuner, and accurately optimizing each performance of the receiving device. <P>SOLUTION: The receiving device includes: a memory 119 for storing a first digital value 116 which is obtained by detecting a radio frequency signal 111 for detection corresponding to a received radio frequency signal, and a second digital value 117 which is obtained by detecting an intermediate frequency signal 109 for detection corresponding to an intermediate frequency signal 106; a storage processing unit 121 which causes the memory 119 to store the first digital value 116 and the second digital value 117 at fixed time intervals; and an oscillation frequency change processing unit 122 for increasing the lock frequency of a PLL circuit 104 by a portion of one channel frequency band, each time the first digital value 116 and the second digital value 117 are stored in the memory 119. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a receiving apparatus that mainly receives terrestrial television broadcasting, and a tuner that includes the receiving apparatus.

  For example, when receiving a terrestrial television broadcast by a receiving device inside a tuner, in an environment where various interference signals (unnecessary interference waves) exist, only a signal having a desired channel frequency band is not impaired. In order to receive, it is necessary to suppress the quality deterioration of the signal to be received due to the interference signal.

  In the receiving apparatus, usually, a trade-off relationship is established between the performance relating to the minimum signal receivable level (reception sensitivity) and the performance relating to the tolerance against the interference signal. In order to design the receiving apparatus so that both of these performances are maintained at or above the standard, a technique for performing channel scanning has been proposed.

  In the channel scan, the above-described performance is dynamically changed based on information indicating the signal reception quality in each channel frequency band. As a result, the receiving apparatus can maintain each of the above performances in an optimum degree according to the changing reception environment (see Patent Document 1).

JP 2008-278058 A (published November 13, 2008)

  However, in the technique for performing the channel scan, when acquiring information indicating the reception quality of a signal in each channel frequency band, AGC control (Automatic Gain Control: automatic) according to the setting of the channel frequency band and the level of the received signal. A series of processing of gain control) and demodulation processing of the received signal is performed for all channel frequency bands.

  For this reason, in the technique for performing the channel scan, the time required for the series of processes becomes longer, which causes a problem that the operation speed of the tuner is reduced.

  Further, in the technique for performing the channel scan, only final information such as a bit error rate is acquired as information indicating the reception quality of a signal. This means that information that can be received and demodulated must be included in the signal of the channel frequency band to be subjected to channel scanning. Here, when an interference signal that cannot be received and demodulated is included, the received signal and the interference signal cannot be detected. For this reason, since it is impossible to detect the level of each of the received signal and the interference signal, which is indispensable for optimizing each performance of the receiving device, each performance of the receiving device depends on the changing reception environment. It is difficult to optimize the value accurately.

  For this reason, in the technique for performing the channel scan, there is a problem that it is difficult to accurately optimize each performance of the receiving device when an interference signal is generated.

  The present invention has been made in view of the above problems, and its purpose is to realize a high-speed operation of the tuner and to accurately optimize each performance of the receiving apparatus. It is to provide an apparatus and a tuner.

  In order to solve the above-described problem, the receiving device of the present invention is a receiving device including a PLL (Phase Locked Loop) circuit for frequency-converting a received radio frequency signal into an intermediate frequency signal. A first digital value obtained by converting an analog voltage obtained by detecting a radio frequency signal for detection according to the signal into a digital signal and an intermediate frequency signal for detection according to the intermediate frequency signal are detected. A storage unit for storing the second digital value obtained by converting the analog voltage obtained in this way into a digital signal, and storing the first and second digital values in the storage unit at regular intervals. A storage processing unit that causes the lock frequency of the PLL circuit to increase at a certain frequency interval each time the first and second digital values are stored in the storage unit. Special It is set to.

  In order to solve the above-described problem, the receiving device of the present invention is a receiving device including a PLL circuit for frequency-converting a received radio frequency signal into an intermediate frequency signal, and detects the frequency according to the radio frequency signal. A first digital value obtained by converting an analog voltage obtained by detecting a radio frequency signal for use into a digital signal, and an analog obtained by detecting an intermediate frequency signal for detection corresponding to the intermediate frequency signal. A storage unit that stores a second digital value obtained by converting a voltage into a digital signal; and a storage processing unit that stores the first and second digital values in the storage unit at regular intervals. And an oscillation frequency change processing unit that lowers the lock frequency of the PLL circuit at regular frequency intervals each time the first and second digital values are stored in the storage unit.

  According to the above configuration, the reception apparatus includes: information on the received radio frequency signal; the first digital value indicating the detection result for the radio frequency signal; and the second digital value indicating the detection result for the intermediate frequency signal. Based on this, it is possible to easily realize the same function as the channel scan. Note that the first and second digital values include, for example, information about the frequency and information about the level of the signal to be detected.

  In this receiving apparatus, when realizing a function equivalent to channel scanning, it is not necessary to perform demodulation processing of the received signal, and AGC control can be simplified, so that the time required for processing is shortened. Therefore, the operation of the tuner can be speeded up.

  Further, in this receiving apparatus, information on the level of the received signal can be acquired from information on the received radio frequency signal and information on the frequency and level indicated by the first and second digital values. For this reason, each level of the received signal and the interference signal can be detected, so that each performance of the receiving apparatus can be optimized appropriately according to the changing reception environment.

  In the receiving apparatus of the present invention, the PLL circuit has a frequency sweep function, and the oscillation frequency change processing unit changes the lock frequency of the PLL circuit in association with the sweep frequency of the PLL circuit. It is characterized by letting.

  According to the above configuration, the PLL circuit can raise or lower the frequency of the intermediate frequency signal at a constant frequency interval associated with the sweep frequency.

  The receiving apparatus of the present invention detects the level of an interference signal having substantially the same frequency as the radio frequency signal from the information indicating the frequency of the radio frequency signal and the first and second digital values. An interference signal level detection unit, and a reception performance adjustment unit that adjusts the performance of the reception device so as to optimize the performance of the reception device according to the detection result of the interference signal level detection unit. It is said.

  According to the above configuration, the reception performance adjustment unit can accurately optimize each performance of the reception device itself according to a function equivalent to the channel scan according to the present invention. In addition, the reception performance adjustment unit adjusts the performance of the reception device in consideration of the level of the interference signal detected by the interference signal level detection unit. The possibility of making it higher than necessary can be reduced. As a result, this receiving apparatus can reduce power consumption.

  The receiving apparatus of the present invention further includes an amplifier for amplifying the radio frequency signal, and the reception performance adjusting unit is configured to input an input reflection coefficient of the amplifier (in accordance with a detection result of the interference signal level detecting unit). S11) is adjusted.

  According to the above configuration, by adjusting the input reflection coefficient of the amplifier, various high frequency filter circuits (LC filter, SAW filter, and so on) for limiting the frequency of the signal before detection within a desired frequency band. The frequency characteristics of the dielectric filter or the like can be changed substantially as appropriate. As a result, the level of the interfering signal is attenuated before the receiving apparatus amplifies the radio frequency signal, thereby improving the signal quality of the received radio frequency signal.

  The receiving apparatus of the present invention further includes a first filter circuit that limits a frequency of the supplied intermediate frequency signal within a desired frequency band, and the reception performance adjusting unit includes the interference signal level detecting unit. According to the detection result, it is determined whether to supply the intermediate frequency signal to the first filter circuit.

  According to said structure, a reception performance adjustment part determines whether a 1st filter circuit is functioned according to the level of the interference signal which the interference signal level detection part detected. When the intermediate frequency signal is not supplied to the first filter circuit and the first filter circuit is not functioned, the power consumption can be reduced in the receiving device.

  In the receiving device of the present invention, the PLL circuit has a variable capacitance element, and the lock frequency of the PLL circuit is set according to the capacitance value of the variable capacitance element, and the capacitance of the variable capacitance element is set. The variable range of values is characterized in that it can be expanded to more than twice the minimum variable range necessary for properly receiving the radio frequency signals of all channel frequency bands.

  Further, in the receiving apparatus of the present invention, the PLL circuit includes a prescaler, and the self-resonant frequency of the prescaler is a minimum self-resonant frequency necessary for appropriately receiving the radio frequency signals in all channel frequency bands. It is characterized in that it can be set to be twice or more.

  According to the above configuration, by expanding the capacitance value of the variable capacitance element or by expanding the self-resonance frequency of the prescaler, it is possible to expand the frequency range that the PLL circuit can handle, so a wider frequency range. In, it becomes possible to detect the interference signal.

  The receiving apparatus of the present invention further includes an intermediate frequency signal detector that detects the detection intermediate frequency signal and outputs the analog voltage indicating the detection result, and the intermediate frequency signal detector is connected to an input terminal. The second filter circuit is connected, and the second filter circuit has a filter characteristic that attenuates power of a signal outside the reception frequency range by 30 dB or more.

  According to said structure, it becomes possible to detect a disturbance signal more precisely.

  The tuner of the present invention includes any one of the above-described receiving devices, and thereby has the same effect as the receiving device.

  A receiving device of the present invention is a receiving device including a PLL circuit for frequency-converting a received radio frequency signal into an intermediate frequency signal, and is obtained by detecting a detection radio frequency signal corresponding to the radio frequency signal. A first digital value obtained by converting the obtained analog voltage into a digital signal and an analog voltage obtained by detecting the detection intermediate frequency signal corresponding to the intermediate frequency signal into a digital signal; A storage unit that stores the obtained second digital value; a storage processing unit that stores the first and second digital values in the storage unit at regular intervals; and the storage unit that stores the first and second digital values. And an oscillation frequency change processing unit that increases the lock frequency of the PLL circuit at a constant frequency interval each time the second digital value is stored.

  A receiving device of the present invention is a receiving device including a PLL circuit for frequency-converting a received radio frequency signal into an intermediate frequency signal, and is obtained by detecting a detection radio frequency signal corresponding to the radio frequency signal. A first digital value obtained by converting the obtained analog voltage into a digital signal and an analog voltage obtained by detecting the detection intermediate frequency signal corresponding to the intermediate frequency signal into a digital signal; A storage unit that stores the obtained second digital value; a storage processing unit that stores the first and second digital values in the storage unit at regular intervals; and the storage unit that stores the first and second digital values. An oscillation frequency change processing unit that lowers the lock frequency of the PLL circuit at regular frequency intervals each time the second digital value is stored.

  Therefore, the receiving apparatus of the present invention can realize the high-speed operation of the tuner and can effectively optimize each performance of the receiving apparatus.

It is a block diagram which shows schematic structure of the receiver which concerns on one embodiment of this invention. It is a graph which shows an example of the frequency characteristic of the high frequency filter circuit concerning the present invention. It is a graph which shows an example of the characteristic of the input reflection coefficient of the amplifier which concerns on this invention. It is a figure which shows the circuit structure of the PLL circuit which concerns on this invention. It is a block diagram which shows schematic structure of the intermediate frequency signal detector based on this invention. It is a block diagram which shows schematic structure of a tuner. It is a block diagram which shows schematic structure of the receiver which concerns on another embodiment of this invention. It is a figure which shows an example of the table which shows the relationship between a frequency and a level of a radio frequency signal.

  The form for implementing this invention is demonstrated with reference to FIGS.

  In the present specification, an RF (Radio Frequency) signal is assumed as a radio frequency signal, and an IF (Intermediate Frequency) signal is assumed as an intermediate frequency signal.

  The receiver and the tuner of the present invention are receivers for receiving terrestrial television broadcasting (analog broadcasting and / or digital broadcasting) and performing video display and audio output.

  For the sake of specific and easy understanding, the following description assumes a receiving apparatus and a tuner that support UHF (Ultra High Frequency) band terrestrial television broadcasting. However, the receiving device and the tuner of the present invention are not limited to those corresponding to UHF band terrestrial television broadcasting, and can be adapted to terrestrial television broadcasting of any channel frequency band depending on the design. is there.

  The reception frequency range is 474 MHz to 858 MHz, and the channel frequency band is 6 MHz each.

[Embodiment 1]
FIG. 1 is a block diagram showing a schematic configuration of a receiving apparatus according to an embodiment of the present invention.

  The receiving apparatus shown in FIG. 1 converts the radio frequency signal received by the antenna 100 into an intermediate frequency signal and outputs it to a demodulating apparatus (see FIG. 6) at the subsequent stage.

  In the receiving apparatus, the high frequency filter circuit 101, the amplifier 123, the mixing circuit 124, the first filter circuit 107, and the intermediate frequency variable gain amplifier 110 are arranged in the order in which the member names are listed from the antenna 100 toward the demodulating apparatus. It is connected. The amplifier 123 and the mixing circuit 124 constitute the frequency conversion circuit 102.

  The radio frequency signal received by the antenna 100 is input to the frequency conversion circuit 102 after the interference signal is removed by the high frequency filter circuit 101.

  The frequency conversion circuit 102 amplifies the signal input from the high frequency filter circuit 101 by the amplifier 123 and mixes it with the LO (Local Oscillating) signal 105 from the PLL circuit 104 by the mixing circuit 124. Frequency conversion to the frequency signal 106 is performed.

  After the interference signal is removed by the first filter circuit 107, the intermediate frequency signal 106 is amplified to a level suitable for demodulation by the intermediate frequency variable gain amplifier 110, and is output to the demodulator.

  Here, the detection radio frequency signal 111 which is an output signal of the amplifier 123 is supplied to the radio frequency signal detector 112, and the detection intermediate frequency signal 109 which is an output signal of the first filter circuit 107 is supplied to the intermediate frequency signal detector 113. Each is entered.

  The radio frequency signal detector 112 detects the frequency and level of the input radio frequency signal 111 for detection, and inputs an analog voltage indicating the detection result to an AD (Analog-Digital) converter 114. To do.

  The intermediate frequency signal detector 113 detects the frequency and level of the input detection intermediate frequency signal 109 and inputs an analog voltage indicating the detection result to the AD converter 115.

  The AD converter 114 converts the analog voltage input from the radio frequency signal detector 112 into a digital signal by performing AD conversion, and the characteristics of the digital signal (included in the digital signal, The information is stored in the storage unit 119 as the first digital value 116 that is a numerical value indicating the frequency and level of the detection radio frequency signal 111.

  The AD converter 115 converts the analog voltage input from the intermediate frequency signal detector 113 into a digital signal by performing AD conversion, and features the digital signal (included in the digital signal. It is stored in the storage unit 119 as a second digital value 117 that is a numerical value indicating the frequency and level of the detection intermediate frequency signal 109.

  The control unit 120 controls the PLL circuit 104 and the storage unit 119, and includes a storage processing unit 121 and an oscillation frequency change processing unit 122.

  The storage processing unit 121 has a function of acquiring various types of information stored in the storage unit 119 and instructing control of the PLL circuit 104 and the storage unit 119 by the control unit 120 based on the acquired various types of information. Further, the storage processing unit 121 has a function of controlling the storage operation of the storage unit 119 so that the storage unit 119 performs the storage operation at an arbitrary timing.

  The oscillation frequency change processing unit 122 has a function of increasing or decreasing the lock frequency of the PLL circuit 104 (the frequency of the desired intermediate frequency signal 106) based on an instruction from the storage processing unit 121. The change in the lock frequency of the PLL circuit 104 corresponds to the change in the frequency of the intermediate frequency signal 106.

  From here, operations of the storage processing unit 121 and the oscillation frequency change processing unit 122 of the control unit 120 will be described in detail.

The receiving apparatus sequentially performs the operations shown in the following (Procedure 1) to (Procedure 4) using, for example, a channel scan request signal 605 (see FIG. 6) from the application processor 604 described later as a trigger. Note that before the operation shown in (Procedure 1) is performed, the lock frequency of the PLL circuit 104 is set to 474 MHz in advance.
(Procedure 1) The storage processing unit 121 causes the storage unit 119 to store the first digital value 116 and the second digital value 117. Thereby, the storage unit 119 stores the input first digital value 116 and second digital value 117.
(Procedure 2) The storage processing unit 121 acquires information indicating that the storage of the first digital value 116 and the second digital value 117 is completed from the storage unit 119. The storage processing unit 121 starts control of the oscillation frequency change processing unit 122 based on the acquired information.
(Procedure 3) The oscillation frequency change processing unit 122 increases the lock frequency of the PLL circuit 104 by an amount corresponding to one channel frequency band (that is, 6 MHz). As a result, the frequency of the intermediate frequency signal 106 increases by an amount corresponding to one channel frequency band.
(Procedure 4) The operations shown in (Procedure 1) to (Procedure 3) are repeated until the lock frequency of the PLL circuit 104 reaches 858 MHz.

  As a result of performing the operation shown in (Procedure 4), the storage unit 119 stores information indicated by the first digital value 116 and the second digital value 117 for all 78 channel frequency bands. In the receiving apparatus, the relationship between the level of the output signal of the high-frequency filter circuit 101 input to the frequency conversion circuit 102 and the first digital value 116 and the second digital value 117 is acquired in advance at the design stage. If so, a table showing the relationship between the frequency and the level of the radio frequency signal can be obtained.

  FIG. 8 shows an example of the table. As shown in FIG. 8, the table shows the level of radio waves (received signals) that exist for each broadcast channel frequency of the received signal (in Japan, the interval between adjacent broadcast channel frequencies is 6 MHz). One-to-one storage is assumed. Specifically, in the figure, each broadcast channel frequency of the received signal is listed in the item “frequency”, and the level of the existing radio wave is listed in the item “radio wave intensity”. In the table, these “frequency” and “ It shows the interrelationship with “radio wave intensity”. Of course, in the table, the frequency information indicated by the item “frequency” does not necessarily correspond to the frequency interval of the broadcast channel frequency. The frequency information can be set to a fine frequency interval (for example, every 1 MHz) by slightly complicating the circuit, and conversely, the frequency information can be set to a coarse frequency interval (for example, every 30 MHz) by simplifying the circuit. It is also possible.

  In the operation shown in (Procedure 3), the oscillation frequency change processing unit 122 may lower the lock frequency of the PLL circuit 104 by an amount corresponding to one channel frequency band. In this case, before the operation shown in (Procedure 1) is performed, the lock frequency of the PLL circuit 104 is set to 858 MHz in advance. In the operation shown in (Procedure 4), the operations shown in (Procedure 1) to (Procedure 3) are performed. Is repeated until the lock frequency of the PLL circuit 104 reaches 474 MHz.

From here, in order to make the description more specific, an example of the relationship between the level of the signal input to the frequency conversion circuit 102, the first digital value 116, and the second digital value 117 will be described. I do. In addition, since this relationship strongly depends on the performance of the receiving apparatus and the design procedure of the system, for the sake of convenience, ideal conditions shown in the following (A) to (E) are assumed.
(A) The frequency conversion circuit 102 performs AGC control in the receiving apparatus.
(B) By the AGC control performed in (A), the gain of the frequency conversion circuit 102 is automatically controlled so that the saturation of the amplifier 123 does not occur when the detection radio frequency signal 111 is output. .
(C) The first filter circuit 107 has a filter characteristic that can sufficiently attenuate only the interference signal.
(D) The first filter circuit 107 has a gain of α dB.
(E) The characteristics of the radio frequency signal detector 112 and the intermediate frequency signal detector 113 are linear.

  In the receiving apparatus that satisfies the above conditions (A) to (E), the gain β (unit dB) of the frequency conversion circuit 102 after the AGC control performed in (A) converges, the radio frequency signal detector If the level γ (unit dB) of the analog voltage output from 112 and the level δ (unit dB) of the analog voltage output from the intermediate frequency signal detector 113 can be known, the signal input to the frequency conversion circuit 102 The level ε (unit dB) is obtained by the following formula (1) or (2).

ε = γ−β [dB] (1) ε = γ−α−δ [dB] (2)
A known general RF signal detection circuit can be used as the radio frequency signal detector 112, and a known general IF signal detection circuit can be used as the intermediate frequency signal detector 113, respectively. The well-known general RF signal detection circuit and IF signal detection circuit each have a limited frequency range that can be detected, and each frequency range that can be detected can be known at the design stage. .

  That is, the level ε can be obtained using the level γ and the level δ. This means that the level ε is obtained as accurate information by performing an operation equivalent to the above formula (1) or (2) using the first digital value 116 and the second digital value 117. It means that you can do it.

  As a result, the table obtained from the relationship between the level ε of the signal input to the frequency conversion circuit 102 and the first digital value 116 and the second digital value 117 shows the relationship between the frequency and the level. .

  The above-described table obtained as a result of the operations shown in (Procedure 1) to (Procedure 4) can be interpreted as a result almost the same as the channel scan according to the prior art.

  That is, in the channel scan according to the prior art, the presence or absence of a received signal is determined by determining the presence or absence of information that can be demodulated by the demodulator. On the other hand, in this receiving apparatus, a function equivalent to the channel scan is realized according to information indicating the levels of the radio frequency signal and the intermediate frequency signal. In this receiving apparatus, since the information regarding the signal level can be acquired from the information regarding the received radio frequency signal and the first digital value 116 and the second digital value 117, each of the received signal and the interference signal can be obtained. Since the level can be detected, each performance of the receiving apparatus can be optimized appropriately according to the changing reception environment.

  In many cases, the performance of the receiving apparatus is determined largely depending on the characteristics of an RFIC (Radio Frequency Integrated Circuit). In this case, if the information about the analog degradation of the signal before being supplied to the demodulating device can be known, the performance of the receiving device can be sufficiently optimized, and information on the type of the signal (modulation method, etc.) Is unnecessary. Therefore, the channel scan using the table obtained as a result of the operations shown in (Procedure 1) to (Procedure 4) can be interpreted as necessary and sufficient.

  In the channel scan according to the prior art, the AGC control is performed according to the received signal so that the level of the signal supplied to the demodulating device is optimized, and the received signal is demodulated by the demodulating device. Therefore, it takes a long time to perform channel scanning for all channel frequency bands. The time required for the AGC control and demodulation processing is at least about several hundred ms per channel frequency band.

  On the other hand, in the function equivalent to the channel scan according to the present invention, the settling time (1 ms or less) of the lock frequency of the PLL circuit 104 and the analog signals output from the radio frequency signal detector 112 and the intermediate frequency signal detector 113 converge. It takes a long time to complete (1 ms or less). Considering this, it is usually difficult to think that a time of 10 ms or more per channel frequency band is required. Therefore, the function equivalent to the channel scan according to the present invention has an advantage that the receiving apparatus, and thus the tuner including the receiving apparatus, can operate at high speed.

  Needless to say, the information stored in the storage unit 119 can be freely read from an external system, and can be used for performance optimization in a receiving system including a receiving device.

  Further specific examples for realizing the receiving apparatus of the present invention are as follows.

  That is, the RF signal (radio frequency signal) from the antenna is removed from a certain amount of unnecessary interference wave (interference signal) by a high frequency filter circuit (LC filter, SAW filter, dielectric filter, etc.), and then the RF amplifier. (Frequency conversion circuit 102). The RF amplifier performs frequency conversion using the LO signal 105 output from the PLL circuit 104, and outputs an IF signal (intermediate frequency signal 106). With this IF signal as an input, the low-pass filter (first filter circuit 107) outputs a signal (intermediate frequency signal for detection 109) obtained by performing a desired signal band limitation on the IF signal. The output signal of the low-pass filter is amplified to an appropriate signal level by a PGA (Programmable Gain Amplifier) circuit (intermediate frequency variable gain amplifier 110). At this time, the output signal of the amplifier in the RF amplifier (detection radio frequency signal 111) and the output signal of the low-pass filter are an RF signal detection circuit (radio frequency signal detector 112) and an IF signal detection circuit (intermediate frequency signal). Each of the detection result voltages is converted into a first digital value 116 and a second digital value 117 by the AD converter 114 and the AD converter 115, respectively, and then stored. It is input to the medium (storage unit 119). The control unit 120 controls the PLL circuit 104 and acquires information stored in the storage medium as necessary.

  By the way, the PLL circuit 104 has a frequency sweep function. At this time, the oscillation frequency change processing unit 122 preferably changes the lock frequency of the PLL circuit 104 in association with the sweep frequency of the PLL circuit 104. Thereby, the PLL circuit 104 can raise or lower the frequency of the intermediate frequency signal 106 at a constant frequency interval associated with the sweep frequency.

[Embodiment 2]
FIG. 7 is a block diagram showing a schematic configuration of a receiving apparatus according to another embodiment of the present invention.

  7 further includes an interference signal level detection unit 125 and a reception performance adjustment unit 126 in the control unit 120 in addition to the reception device shown in FIG.

  The interference signal level detection unit 125 detects the level of an interference signal having substantially the same frequency as the radio frequency signal from the information indicating the frequency of the radio frequency signal and the first digital value 116 and the second digital value 117. To do. The reception performance adjustment unit 126 has a frequency conversion circuit 102, a first filter circuit 107, an intermediate frequency variable gain amplifier 110, and an optimization unit that optimizes the performance of the reception device according to the detection result of the interference signal level detection unit 125. It adjusts the performance of other components of the receiving apparatus. In other words, the reception performance adjustment unit 126 takes into account that a trade-off relationship is established between the performance related to the minimum signal receivable level (reception sensitivity) and the performance related to resistance to the interference signal. The performance of each component of the receiving apparatus is adjusted so that both performances of the receiver are maintained at or above the level regardless of changes in the reception environment.

  The reception performance adjustment unit 126 adjusts the performance of each component constituting the RFIC, but is a wireless signal obtained from the first digital value 116 and the second digital value 117 that are detection results of the interference signal level detection unit 125. If there is information indicating the relationship between the frequency and the level of the frequency signal, there are many specific methods for performing the performance adjustment based on the information.

Here, as specific examples of the performance adjustment of the receiving apparatus, the following 1. ~ 3. A method for optimizing the three performances listed below will be described.
1. "Noise Figure (NF) optimization"
The signal level (Desired, hereinafter referred to as “D”) of the desired channel frequency band desired to be received by the receiving apparatus, two bands adjacent to the desired channel frequency band, and two bands adjacent to the two bands (total If the difference between the total level of undesired signals (Undesired, hereinafter referred to as “U”) occurring in (four bands) is a predetermined value (for example, the D / U ratio is 0 dB) or more, For example, the gain of the amplifier 123 is increased by 6 dB. Thereby, the ratio of the gain of the entire receiving apparatus is increased in the circuit closer to the antenna 100 than the mixing circuit 124, which mainly processes the radio frequency signal, and NF can be improved. If the gain of the entire circuit on the antenna 100 side than the mixing circuit 124 is increased by 6 dB, the contribution degree of the interference signal generated in the circuit after the mixing circuit 124 (the demodulator side) that mainly processes the intermediate frequency signal 106 is , Half of the conventional. In the receiving apparatus, generally, in gain distribution when a medium level signal of −40 dBm to −70 dBm is received, an interference signal generated in a circuit after the frequency conversion circuit 102 is attenuated. It is suitable because the performance improvement effect is great. At this time, since the level of the interference signal is sufficiently small, the S / N (Signal Noise Ratio) deterioration due to the distortion of the signal waveform caused by increasing the gain of the amplifier 123 can be ignored. Small enough.
2. "Optimization of linearity"
Above 1. In contrast, in the case where the difference between D and U is equal to or less than a predetermined value (for example, the D / U ratio is −20 dB), the gain of the amplifier 123 is decreased by, for example, 6 dB. As a result, the ratio of the gain of the entire receiving apparatus increases in the circuits after the first filter circuit 107. In this case, distortion of the waveform of the signal output from the amplifier 123 can be reduced, so that the S / N ratio of the signal supplied to the demodulator can be improved. Specifically, when the gain of the amplifier 123 is reduced by 6 dB, the S / N due to the third order distortion is improved by about 12 dB, and the S / N due to the second order distortion is improved by about 6 dB.
3. "Minimization of power consumption"
2. above. Further, when the difference between D and U is smaller (for example, the D / U ratio is −40 dB or less), the first filter circuit 107 is bypassed, that is, the first filter circuit 107 is substantially bypassed. A configuration in which the intermediate frequency signal 106 is not supplied and the first filter circuit 107 does not function can be employed. In this case, since it can be determined that there is no interfering signal to be removed in the first place, the power corresponding to the power consumption of the first filter circuit 107 is reduced in the receiving apparatus by bypassing the first filter circuit 107. be able to.

  The above 1. ~ 3. The specific example of the performance adjustment of the receiving apparatus shown in FIG. 5 is merely an example, and the design performance of the circuits to be controlled (particularly, the frequency conversion circuit 102, the first filter circuit 107, and the intermediate frequency variable gain amplifier 110). It goes without saying that the reference value can be changed accordingly.

  According to the above configuration, the reception performance adjustment unit 126 can appropriately optimize each performance of the reception device itself according to a function equivalent to the channel scan according to the present invention. In addition, the reception performance adjustment unit 126 adjusts the performance of the reception device in consideration of the level of the interference signal detected by the interference signal level detection unit 125. The possibility of increasing the performance more than necessary can be reduced. As a result, this receiving apparatus can reduce power consumption.

[Embodiment 3]
Since the configuration of the receiving apparatus according to the present embodiment is as shown in FIG. 7 as described above, detailed description thereof is omitted.

  As the high-frequency filter circuit 101, an optimum filter is selected in advance according to various conditions required for a system including the receiving apparatus. Generally, an LC (inductance-capacitance) filter, Either a SAW (Surface Acoustic Wave) filter or a dielectric filter is selected.

  Here, the input reflection coefficient (S11 · return loss) of the amplifier 123 changes the frequency selection characteristic of the high-frequency filter circuit 101.

  Usually, a general high frequency filter circuit uses all the channel frequency bands as pass bands, and is 474 MHz to 858 MHz here.

  FIG. 2 is a graph showing an example of frequency characteristics of the high frequency filter circuit 101. The horizontal axis 206 indicates the frequency (unit: MHz), and the vertical axis 207 indicates the intensity (unit: dB) of the signal passing through the high frequency filter circuit 101.

  The characteristic indicated by the solid line is the filter characteristic 201 of the normal high frequency filter circuit 101 (before the filter characteristic adjustment). The characteristic indicated by the dotted line is the filter characteristic 202 of the high-frequency filter circuit 101 after the filter characteristic adjustment.

  The filter characteristic 201 of the normal high frequency filter circuit 101 usually has a constant passband ripple component 203.

  On the other hand, the frequency of the signal actually received by the receiving apparatus (or the tuner including the receiving apparatus) is within a certain channel frequency band. Therefore, the high frequency filter circuit 101 only needs to have a filter characteristic that allows a signal in the one channel frequency band to pass, and has a filter characteristic that allows a signal in the entire frequency band of the UHF band to pass. There is no need.

  Therefore, when certain conditions are met, the input reflection coefficient of the amplifier 123 is changed to change the filter characteristic 201 to the filter characteristic 202, and the signal is a signal outside the desired channel frequency band. It is important to attenuate the signal.

  Here, the certain condition under which the filter characteristics should be changed is a condition that the interference signal level detection unit 125 detects an interference signal having a large level outside the desired channel frequency band. Specifically, this condition is a signal obtained in advance that the signal level at the frequency 205 of the interference signal is extremely high when the frequency 204 of the desired reception signal is set to the frequency 205 of the interference signal. The condition is that it is known from the intensity table (see FIG. 8).

  FIG. 3 is a graph showing an example of the characteristics of the input reflection coefficient of the amplifier 123. The horizontal axis 305 indicates the frequency (unit: MHz), and the vertical axis 306 indicates the input reflection coefficient (unit: dB) of the amplifier 123. Further, the frequency 303 is the lowest frequency in the entire channel frequency band (474 MHz to 858 MHz in the present embodiment), and the frequency 304 is the highest frequency.

  In normal receiver design (before input reflection coefficient adjustment), as indicated by the solid input reflection coefficient characteristics 301, it is common to make the input reflection coefficient sufficiently small in the desired all-channel frequency band.

  On the other hand, in a situation where it is allowed to specialize the performance of the receiving apparatus so that signals within a specific channel frequency band can be received, the filter characteristics of the high-frequency filter circuit 101 shown in FIG. 2 and the amplifier 123 shown in FIG. In view of the input reflection coefficient, the frequency of the frequency corresponding to the interference signal can be reduced by sufficiently reducing the input reflection coefficient only in a narrower frequency band, as shown by the broken line input reflection coefficient characteristic 302. It is possible to intentionally attenuate the signal. In general, even if the adjustment of the input reflection coefficient of the amplifier 123 is a rough adjustment, the characteristics of the high-frequency filter circuit 101 shown in FIG. 2 can be significantly changed, so that the frequency selection characteristics can be improved. It becomes possible.

  In the present embodiment, for example, when a high-level interference signal is generated in a VHF (Very High Frequency) band or a WCDMA (Wideband Code Division Multiple Access) band, the interference signal is attenuated. Therefore, it is possible to design a system including the receiving apparatus so that an excessive performance requirement is not made. The system design has an effect that the design cost (power consumption and circuit scale) of the RFIC as the receiving apparatus can be reduced.

[Embodiment 4]
In the present embodiment, an example in which an interference signal outside the reception frequency range is detected will be described.

  Specifically, interference signals in VHF band, GSM (Global System for Mobile) band, and CDMA band other than UHF band are detected by a receiver adapted to receive signals in UHF band (especially 474 MHz to 858 MHz). This is effective for optimizing the performance of the receiving apparatus.

  The problem here is that in order to detect an interference signal, the lock frequency of the PLL circuit 104 is set even outside the desired channel frequency band, and the receiving apparatus normally performs frequency conversion even in this band. It is necessary to do. When performing frequency conversion, it is not a problem to expand the operating frequency range of the receiving apparatus. However, increasing the range of the lock frequency (sweep frequency) of the PLL circuit 104 causes an increase in cost in terms of circuit design. There is a problem.

  Therefore, in this embodiment, a configuration that can suppress an increase in cost and can expand the range of the lock frequency of the PLL circuit 104 will be described. Here, the purpose of expanding the range is simply to detect interference signals over a wide band, and may be ignored in the noise performance and spurious performance normally required as the performance of the PLL circuit 104.

  FIG. 4 is a diagram illustrating a circuit configuration of the PLL circuit 104, and particularly illustrates a configuration example of a VCO (Voltage Controlled Oscillator).

  The VCO shown in FIG. 4 has a configuration generally used, and includes a current source 401, n-channel MOS (Metal Oxide Semiconductor) transistors (hereinafter simply referred to as transistors) 402 and 403, capacitive elements 404 to 407, variable elements. A capacitive element (varactor) 408, an inductor 409, and switches 411 and 412 are provided. Transistors 402 and 403, whose source terminals are connected to the current source 401, constitute a negative resistance unit 410.

  One end of the current source 401 is grounded, and the other end is connected to the source terminals of the transistors 402 and 403. Each gate terminal of the transistors 402 and 403 is connected to one end of each of the capacitor elements 407 and 406. The drain terminals of the transistors 402 and 403 are connected to the other ends of the capacitive elements 406 and 407, respectively, and a parallel circuit of the variable capacitive element 408 and the inductor 409 is connected between the nodes accompanying this connection. Yes. Each node associated with this connection is connected to one end of each of the switches 411 and 412. The other ends of the switches 411 and 412 are connected to one ends of the capacitive elements 404 and 405, respectively. The other ends of the capacitive elements 404 and 405 are grounded.

  In the VCO, a load LC tank includes a variable capacitance element 408 and an inductor 409, and a switch additional capacitance element (capacitance element) for changing the capacitance value of the variable capacitance element 408 to change the oscillation frequency of the VCO. 404 and 405, and switches 411 and 412).

  When receiving a signal, the variable range of the capacitance value of the variable capacitance element 408 is set so that the phase noise generated in the VCO is minimized. Specifically, the VCO controls the capacitive elements 404 and 405 via the connected switches 411 and 412, respectively, and adjusts the resonance frequency of the variable capacitive element 408 and the inductor 409. The variable range of the capacitance value is set to a minimum variable range necessary for receiving signals in the entire reception frequency range. As a result, the oscillation frequency of the VCO becomes a range corresponding to the variable range of the capacitance value of the variable capacitance element 408.

  On the other hand, when performing the function equivalent to the channel scan according to the present invention, the performance such as phase noise may be ignored, so by intentionally shifting the resonance frequency of the LC tank with the switch additional capacitance element, It is possible to focus on expanding the frequency variable range of the VCO. Specifically, the VCO controls the capacitive elements 404 and 405 via the connected switches 411 and 412, respectively, and adjusts the resonance frequency of the variable capacitive element 408 and the inductor 409. The variable range of the capacitance value is set to a wider range than when the signal is received. Note that the variable range of the capacitance value of the variable capacitance element 408 at this time is preferably extended to twice or more that when receiving a signal.

  As described above, the PLL circuit 104 has the variable capacitance element 408 in the VCO, and the frequency of the intermediate frequency signal 106 (see FIGS. 1 and 7) is changed according to the lock frequency of the PLL circuit 104. It is set according to the capacity value of 408. The variable range of the capacitance value of the variable capacitance element 408 implements a function equivalent to the channel scan according to the present invention in accordance with the opening / closing of the switches 411 and 412 (whether or not the switch additional capacitance element functions). Sometimes it can be expanded. At this time, it is preferable that the variable range of the capacitance value of the variable capacitance element 408 is expanded to more than twice the minimum required variable range for receiving signals in the entire reception frequency range.

  According to the above configuration, the frequency range in which the VCO can be oscillated and the lockable range of the PLL circuit 104 can be expanded while suppressing an increase in the cost of the VCO. The range can be widened.

  Next, an example of a prescaler (not shown) having an important configuration for setting the lock frequency of the PLL circuit 104 outside the reception frequency range will be described. The prescaler is a well-known frequency dividing circuit capable of outputting a signal having a frequency that is 1 / integer of an input signal, and can obtain various frequency dividing ratios according to the PLL architecture. This prescaler is usually designed to be optimal in order to realize a desired lockable range, and it is very difficult in design to simply widen this lock variable range.

  Therefore, in this receiving apparatus, a prescaler whose own resonance frequency is higher than the maximum value or lower than the minimum value in the reception frequency range is prepared, and the function equivalent to the channel scan according to the present invention is performed. Only when the prescaler is used, the lock frequency range of the PLL circuit 104 can be widened.

  According to the above configuration, the frequency range that the PLL circuit 104 can handle can be expanded by increasing the capacitance value of the variable capacitance element 408 or by increasing the self-resonant frequency of the prescaler. Interference signals can be detected in the frequency range.

[Embodiment 5]
FIG. 5 is a block diagram showing a schematic configuration of the intermediate frequency signal detector 113.

  In the intermediate frequency signal detector 113 shown in FIG. 5, the second filter circuit 501 and the intermediate frequency signal detection filter circuit 502 are connected in series between the input terminal 504 and the output terminal 505 in the order in which the member names are listed. It is a configuration.

  Here, the second filter circuit 501 has a steep filter characteristic that attenuates the power of a signal outside the reception frequency range by 30 dB (30 dB) or more. The second filter circuit 501 can be designed at low cost because there is almost no need to consider variations in noise performance and filter characteristics.

  By further including the second filter circuit 501 having a steep filter characteristic, the intermediate frequency signal detector 113 detects the intermediate frequency signal 109 for detection more precisely than the interference signal and has a desired frequency. Only the signal level can be detected more precisely, and the reliability of the signal strength table can be improved.

[Embodiment 6]
FIG. 6 is a block diagram illustrating a schematic configuration of a tuner including the receiving apparatus.

  A radio frequency signal received by an antenna 601 (corresponding to the antenna 100 in FIGS. 1 and 7) is received by a receiving device (see FIGS. 1 and 7) 602, converted into an intermediate frequency signal, and demodulated by a demodulating device 603. Processing is performed, and the application processor 604 converts the information into information for performing video display and audio output. Up to this point, the configuration is the same as that of the tuner to which the technology for performing channel scanning according to the conventional technology is applied.

  However, this tuner is different from the tuner to which the technology for performing the channel scan according to the prior art is applied, with respect to the receiving device 602 itself and various operations on the receiving device 602.

  That is, the application processor 604 outputs a channel scan request signal 605 to the receiving device 602 at an arbitrary timing. When this channel scan request signal 605 is supplied, the receiving device 602 performs a function equivalent to the above-described channel scan performed by the control unit 120 (particularly, see Embodiment 1). In addition, the receiving apparatus 602 optimizes its own performance described above according to the function (see particularly Embodiment 2). The result of performing the function equivalent to the channel scan shows, for example, the relationship between the level and the frequency obtained from the relationship between the level of the output signal of the high frequency filter circuit 101 and the first digital value 116 and the second digital value 117. The result is stored as a table in the storage unit 119, and the result is supplied to the application processor 604 as a channel scan information signal 606.

  From here, the procedure of the function equivalent to the above-described channel scan by the tuner provided with the receiving apparatus will be described more specifically, and the effectiveness of the tuner will be described.

  The channel scan according to the prior art requires the following four steps per channel frequency band.

  (Step 1): The frequency of the intermediate frequency signal (the lock frequency of the PLL circuit 104) is set.

  (Step 2): AGC control of each circuit in the receiving apparatus is performed according to the received signal.

  (Step 3): Synchronize the demodulator.

  (Step 4): A bit error rate (BER) is calculated.

Here, the time required for (Step 1) to (Step 4) depends on the system equipped with the receiving device and cannot be generally stated. For example, reception of one-segment broadcasting in Japan is taken as an example. For example, 1 ms in (Step 1) and 100 ms in (Step 2) and (Step 3). Further, (step 4) takes about 1 s (1000 symbols) in order to detect the bit error rate on the order of 1e- ³ or less, although it depends on the accuracy of the required bit error rate. That is, the total time required for (Step 1) to (Step 4) is approximately 1.4 s per channel frequency band.

  On the other hand, in this tuner, the steps necessary for realizing the function equivalent to the channel scan are the following (Step 5) in addition to the above (Step 1) and (Step 2).

  (Step 5): The first digital value 116 and the second digital value 117 corresponding to the corresponding channel frequency band are stored in the storage unit 119.

  In (Step 2), since the AGC control can be performed by the receiving device 602 alone regardless of the demodulating device 603, the convergence speed of the AGC control is higher than that of the receiving device according to the related art.

  Here, in this tuner, the time required for (Step 2) and (Step 5) depends on the system provided with the receiving device and cannot be generally stated. For example, reception of one-segment broadcasting in Japan is taken as an example. For example, 1 ms in (Step 1), 10 ms in (Step 2), and 1 ms in (Step 5). In other words, in the present invention, “every fixed time” indicating the cycle of storing the first digital value 116 and the second digital value 117 in the storage unit 119 is (1 ms + 10 ms + 1 ms =) every 12 ms.

  In this tuner, the time required for (Step 2) and (Step 5) is approximately 12 ms per one channel frequency band, and therefore this tuner can realize a very high-speed operation.

  With this configuration, this tuner can achieve high-speed operation and can perform performance optimization that flexibly copes with changes in the reception environment due to movement or the like.

  Finally, each block of the control unit 120 may be configured by hardware logic, or may be realized by software using a CPU as follows.

  That is, the receiving apparatus including the control unit 120 includes a central processing unit (CPU) that executes instructions of a control program that realizes each function, a read only memory (ROM) that stores the program, and a RAM ( random access memory), a storage device (recording medium) such as a memory for storing the program and various data. An object of the present invention is to provide a recording medium in which a program code (execution format program, intermediate code program, source program) of a control program of the control unit 120, which is software that realizes the functions described above, is recorded in a computer-readable manner. This can also be achieved by supplying to the control unit 120 and reading and executing the program code recorded on the recording medium by the computer (or CPU or MPU).

  Examples of the recording medium include tapes such as magnetic tapes and cassette tapes, magnetic disks such as floppy (registered trademark) disks / hard disks, and disks including optical disks such as CD-ROM / MO / MD / DVD / CD-R. Card system such as IC card, IC card (including memory card) / optical card, or semiconductor memory system such as mask ROM / EPROM / EEPROM / flash ROM.

  The control unit 120 may be configured to be connectable to a communication network, and the program code may be supplied via the communication network. The communication network is not particularly limited. For example, the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication. A net or the like is available. Also, the transmission medium constituting the communication network is not particularly limited. For example, even in the case of wired such as IEEE 1394, USB, power line carrier, cable TV line, telephone line, ADSL line, etc., infrared rays such as IrDA and remote control, Bluetooth ( (Registered trademark), 802.11 wireless, HDR, mobile phone network, satellite line, terrestrial digital network, and the like can also be used. The present invention can also be realized in the form of a computer data signal embedded in a carrier wave in which the program code is embodied by electronic transmission.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can realize a high-speed operation of a tuner and accurately optimize each performance of the receiving apparatus in a receiving apparatus including a PLL circuit for converting a received radio frequency signal into an intermediate frequency signal. It is a possible invention. Therefore, the present invention can be suitably used for a receiver that mainly receives terrestrial television broadcasts and a tuner including the receiver.

100 antenna 101 high frequency filter circuit 102 frequency conversion circuit 104 PLL circuit 105 LO signal 106 intermediate frequency signal 107 first filter circuit 109 detection intermediate frequency signal 110 intermediate frequency variable gain amplifier 111 detection radio frequency signal 112 radio frequency signal detector 113 Intermediate frequency signal detectors 114 and 115 Analog-to-digital converter (AD converter)
116 First digital value 117 Second digital value 119 Storage unit 120 Control unit 121 Storage processing unit 122 Oscillation frequency change processing unit 123 Amplifier 124 Mixing circuit 125 Interference signal level detection unit 126 Reception performance adjustment unit 201 Normal high frequency filter circuit 101 Filter characteristic 202 Filter characteristic 203 of adjusted high-frequency filter circuit 101 Passband ripple component 204 Frequency 205 of desired received signal Frequency 206 of interference signal Horizontal axis (frequency)
207 vertical axis (intensity of signal passing through high-frequency filter circuit 101)
301 Characteristic of input reflection coefficient of normal amplifier 123 302 Characteristic of input reflection coefficient of adjusted amplifier 123 303 Minimum frequency in all channel frequency band 304 Maximum frequency in all channel frequency band 305 Horizontal axis (frequency)
306 Vertical axis (input reflection coefficient)
401 Current sources 402 and 403 n-channel MOS transistors 404 to 407 Capacitance element 408 Variable capacitance element 409 Inductor 410 Negative resistance part 411 and 412 Switch 501 Second filter circuit 502 Filter circuit 504 for detecting intermediate frequency signal Input terminal 505 Output terminal 601 Antenna 602 Receiver 603 Demodulator 604 Application processor 605 Channel scan request signal 606 Channel scan information signal

Claims (10)

A receiving device including a PLL circuit for frequency-converting a received radio frequency signal into an intermediate frequency signal,
A first digital value obtained by converting an analog voltage obtained by detecting a radio frequency signal for detection according to the radio frequency signal into a digital signal, and an intermediate frequency signal for detection according to the intermediate frequency signal A second digital value obtained by converting an analog voltage obtained by detecting the signal into a digital signal;
A storage processing unit for storing the first and second digital values in the storage unit at regular intervals;
An oscillation frequency change processing unit that increases the lock frequency of the PLL circuit at a constant frequency interval each time the first and second digital values are stored in the storage unit. . A receiving device including a PLL circuit for frequency-converting a received radio frequency signal into an intermediate frequency signal,
A first digital value obtained by converting an analog voltage obtained by detecting a radio frequency signal for detection according to the radio frequency signal into a digital signal, and an intermediate frequency signal for detection according to the intermediate frequency signal A second digital value obtained by converting an analog voltage obtained by detecting the signal into a digital signal;
A storage processing unit for storing the first and second digital values in the storage unit at regular intervals;
An oscillation frequency change processing unit that lowers the lock frequency of the PLL circuit at a constant frequency interval each time the first and second digital values are stored in the storage unit. . The PLL circuit has a frequency sweep function,
The receiving apparatus according to claim 1, wherein the oscillation frequency change processing unit changes a lock frequency of the PLL circuit in association with a sweep frequency of the PLL circuit. An interference signal level detector for detecting a level of an interference signal having substantially the same frequency as the radio frequency signal from the information indicating the frequency of the radio frequency signal and the first and second digital values;
4. A reception performance adjusting unit that adjusts the performance of the receiving device so as to optimize the performance of the receiving device according to the detection result of the interference signal level detecting unit. The receiving device according to any one of the above. An amplifier for amplifying the radio frequency signal;
The receiving apparatus according to claim 4, wherein the reception performance adjustment unit adjusts an input reflection coefficient of the amplifier according to a detection result of the interference signal level detection unit. A first filter circuit for limiting the frequency of the supplied intermediate frequency signal within a desired frequency band;
6. The reception performance adjusting unit according to claim 4 or 5, wherein the reception performance adjusting unit determines whether to supply the intermediate frequency signal to the first filter circuit according to a detection result of the interference signal level detection unit. The receiving device described. The PLL circuit has a variable capacitance element,
The lock frequency of the PLL circuit is set according to the capacitance value of the variable capacitance element,
The variable range of the capacitance value of the variable capacitance element can be extended to more than twice the minimum variable range necessary for properly receiving the radio frequency signals of all channel frequency bands. The receiving device according to any one of claims 1 to 6. The PLL circuit includes a prescaler,
The self-resonant frequency of the prescaler can be set to at least twice the minimum self-resonant frequency necessary for properly receiving the radio frequency signals in all channel frequency bands. Item 7. The receiving device according to any one of Items 1 to 6. An intermediate frequency signal detector for detecting the intermediate frequency signal for detection and outputting the analog voltage indicating the detection result;
The intermediate frequency signal detector includes a second filter circuit connected to an input terminal,
The receiving apparatus according to claim 1, wherein the second filter circuit has a filter characteristic that attenuates the power of a signal outside the reception frequency range by 30 decibels or more. .   A tuner comprising the receiving device according to claim 1.

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