JP4303409B2 - Method for depositing conductive plug and method for manufacturing semiconductor device - Google Patents

Method for depositing conductive plug and method for manufacturing semiconductor device Download PDF

Info

Publication number
JP4303409B2
JP4303409B2 JP2000284967A JP2000284967A JP4303409B2 JP 4303409 B2 JP4303409 B2 JP 4303409B2 JP 2000284967 A JP2000284967 A JP 2000284967A JP 2000284967 A JP2000284967 A JP 2000284967A JP 4303409 B2 JP4303409 B2 JP 4303409B2
Authority
JP
Japan
Prior art keywords
gas
processing chamber
contact hole
alternately
exhausting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000284967A
Other languages
Japanese (ja)
Other versions
JP2002093746A (en
Inventor
真一 中田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Priority to JP2000284967A priority Critical patent/JP4303409B2/en
Publication of JP2002093746A publication Critical patent/JP2002093746A/en
Application granted granted Critical
Publication of JP4303409B2 publication Critical patent/JP4303409B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、導電性プラグの堆積方法及び半導体装置の製造方法に関し、より詳細には、半導体装置のコンタクトホール又はビアホールにタングステンを埋め込む際のステップカバリッジを向上した導電性プラグの堆積方法及び半導体装置の製造方法に関するものである。
【0002】
【従来の技術】
半導体装置は、素子の電極と配線、又は、配線と配線とを導通するコンタクトホール又はビアホール(以下、総称してコンタクトホールと呼ぶ)を有する。このため、コンタクトホールに導電性プラグ(タングステン)を埋め込む技術が幾つか開発されている(例えば、特開平9−321137号公報)。また、微細化が進むに伴い、パターンサイズ程には薄膜化が進まず、コンタクトホール径に対するコンタクトホール深さの比であるアスペクト比が増大する傾向にある。
【0003】
図2は、従来の導電性プラグの堆積方法を示す。同図(a)に示すように、最初にCVD法により、半導体装置のコンタクトホールの側壁に、バリアメタル1を成膜する。同図(b)に示すように、次に所定の圧力の反応性ガスを連続して導き、バリアメタル1の上に、タングステン核形成膜4を成膜する。同図(c)に示すように、更に所定の圧力の反応性ガスを連続して導き、タングステン核形成膜4の上に、タングステン埋込み膜5を成膜して、コンタクトホールを埋め込む。
【0004】
【発明が解決しようとする課題】
上記従来の導電性プラグの堆積方法では、反応性ガスを連続して導くので、アスペクト比が高いコンタクトホール内で発生した副反応性生成ガスがコンタクトホール底部に溜り、反応性ガスをコンタクトホール底部まで充分に導くことができない。これに起因して、タングステン核形成膜4は、コンタクトホール底部で成長速度が遅くなり膜厚が薄くなるので、タングステン埋込み膜5がコンタクトホール底部で充分に成長できずボイド6が発生する。
【0005】
ボイド6が発生すると、後工程においてコンタクトホールの上部に配線を形成する際、ボイド6が露出しタングステン埋込み膜5と配線とが断線する可能性がある。また、コンタクトホールのコンタクト抵抗又はスルーホール抵抗を高くしステップカバリッジを悪化させるので、長期信頼性の低下や歩留まりの低下になる恐れがあった。
【0006】
本発明は、上記したような従来の技術が有する問題点を解決するためになされたものであり、高いアスペクト比を有するコンタクトホールのステップカバリッジを向上させる導電性プラグの堆積方法及び半導体装置の製造方法を提供することを目的とする。
【0007】
【課題を解決するための手段】
上記目的を達成するため、本発明の導電性プラグの堆積方法は、処理室内に反応性ガスを導入してスルーホール又はコンタクトホール内に導電性プラグを堆積する方法において、処理室内に反応性ガスを導入して堆積を進行させるガス導入ステップと、前記処理室内のガスを排気するガス排気ステップとを交互に繰り返すことを特徴とする。
【0008】
本発明の導電性プラグの堆積方法は、ガス導入ステップとガス排気ステップとを交互に複数回繰り返すことにより、成膜物の膜厚が全体で均一になり、導電性プラグがコンタクトホールをカバレッジ良く埋め込むので、ステップカバリッジが向上する。
【0009】
本発明の導電性プラグの堆積方法では、前記ガス排気ステップは、処理室内圧力が前記ガス導入ステップにおける処理室内圧力の1/2〜1/10となった時点で終了することが好ましい。この場合、ガス排気ステップの排気時間を適切に選択できるので、その次のガス導入ステップが効率良く行える。
【0010】
WF6、SiH4及びH2を導入するガス導入ステップとこれに交互するガス排気ステップとを有する第1段階と、WF6及びH2を導入するガス導入ステップとこれに交互するガス排気ステップとを有する第2段階とを順次有することも本発明の好ましい態様である。この場合、第1段階ではタングステン核形成膜群が形成され、第2段階ではタングステン埋込み膜群が形成されるので、ステップカバリッジが好に向上する。
【0011】
また、本発明の導電性プラグの堆積方法では、前記ガス排気ステップは、反応性ガスから生成された副反応性生成ガスを排気するステップであることもできる。
【0012】
【発明の実施の形態】
以下、本発明の実施形態例に基づいて、本発明の導電性プラグの堆積方法について図面を参照して説明する。図1は、本発明の一実施形態例の導電性プラグの堆積方法を示す。半導体装置は、アスペクト比が高いコンタクトホールを有する。本実施形態例の導電性プラグの堆積方法は、バリアメタル工程、核形成膜工程、及び、埋込み膜工程を有し、この順に処理室内で実施する。処理室内は、100枚程度のウェハを一度に処理する炉内と異なり、ウェハ1枚を処理するものである。
【0013】
同図(a)は、バリアメタル工程を示す。最初に、CVD法によりWN、TiN、TaN等から成るバリアメタル1を半導体装置のコンタクトホールの側壁に成膜するが、アスペクト比によっては指向性スパッタ法等も使用できる。高いアスペクト比を有するコンタクトホールでは、バリアメタル1がカバレッジ良く成膜されると、良好なコンタクトが得られタングステンのステップカバリッジが向上する。
【0014】
同図(b)は、核形成膜工程(第1段階)を示す。核形成膜工程は、バリアメタル工程の次に実施され、ガス導入ステップ及びガス排気ステップを有する。ガス導入ステップでは、圧力を133〜13300[Pa]に設定したWF6、Si4、及び、H2の反応性ガスを供給し、タングステン核形成膜群2をバリアメタル1の上に成膜する。WF6は10〜100[sccm]に設定され、Si4は4〜50[sccm] に設定される。この過程で、副反応性生成ガスが発生し、コンタクトホール底部に溜まる。
【0015】
ガス排気ステップでは、反応性ガス及び副反応性生成ガスを含むコンタクトホール内のガスを排気する。処理室内圧力がガス導入ステップの1/2〜1/10になった時点で終了するように、排気時間は、選択する。
【0016】
ガス導入ステップ及びガス排気ステップは、交互に複数回繰り返して実施される。タングステン核形成膜群2のガス排気ステップの次に実施されるガス導入ステップでは、反応性ガスがコンタクトホール底部まで充分に導かれるので、膜厚が均一になる。双方のステップを複数回繰り返すので、タングステン核形成膜群2がカバレッジ良く成膜され、膜厚が10〜50[nm]になる。
【0017】
同図(c)は、埋込み膜工程(第2段階)を示す。埋込み膜工程は、核形成膜工程の次に実施され、核形成膜工程と同様にガス導入ステップ及びガス排気ステップを有する。ガス導入ステップでは、圧力を6650〜53200[Pa]に設定したWF6及びH2の反応性ガスを供給し、タングステン埋込み膜群3をタングステン核形成膜群2の上に成膜する。WF6は50〜500[sccm]に設定され、H2は500〜5000[sccm]に設定される。
【0018】
ガス排気ステップでは、核形成膜工程と同様に、コンタクトホール内のガスを排気する。所定の時点で終了するように、排気時間は、選択する。ガス導入ステップ及びガス排気ステップは、交互に複数回繰り返して実施される。核形成膜工程と同様に、タングステン埋込み膜群3がカバレッジ良く成膜され、膜厚が50〜500[nm]になる。
【0019】
タングステン埋込み膜群3がカバレッジ良くコンタクトホールを埋め込み、ボイドが発生しないので、導電性プラグのステップカバリッジが向上する。
【0020】
反応性ガスは、WF6から成る材料ガス、及び、Si4やH2等から成る還元ガスで構成される。予め反応性ガスを材料ガスと還元ガスとに分離して、導入することが好ましい。核形成膜工程及び埋込み膜工程のガス導入ステップでは、材料ガスをコンタクトホール底部に予め拡散し、その後還元ガスを導入する。還元ガスが材料ガスに比して拡散速度が速く、双方のガスがコンタクトホール底部まで均一に拡散するので、カバレッジの良いタングステン核形成膜群2及びタングステン埋込み膜群3が成膜する。核形成膜工程及び埋込み膜工程のガス導入ステップ以外は、上記と同様にする。
【0021】
また、半導体装置の他の部分の形成にも本発明の導電性プラグの堆積方法が適用できる。アスペクト比が高い微細配線の場合、ガス導入ステップ及びガス排気ステップを複数回繰り返し、ある程度の膜厚を成膜する。層間膜間に対する埋込みの場合、ガス導入ステップ及びガス排気ステップを1ステップで実施し、所望の膜厚を成膜する。
【0022】
上記実施形態例によれば、ガス導入ステップとガス排気ステップとを交互に複数回繰り返すことにより、成膜物の膜厚が全体で均一になり、導電性プラグがコンタクトホールをカバレッジ良く埋め込むので、ステップカバリッジが向上する。
【0023】
以上、本発明をその好適な実施形態例に基づいて説明したが、本発明の導電性プラグの堆積方法は、上記実施形態例の構成にのみ限定されるものでなく、上記実施形態例の構成から種々の修正及び変更を施した導電性プラグの堆積方法も、本発明の範囲に含まれる。
【0024】
【発明の効果】
以上説明したように、本発明の導電性プラグの堆積方法では、ガス導入ステップとガス排気ステップとを交互に複数回繰り返すことにより、成膜物の膜厚が全体で均一になり、導電性プラグがコンタクトホールをカバレッジ良く埋め込むので、ステップカバリッジが向上する。このため、コンタクトホールと配線との断線や抵抗の増加を防ぐので、半導体装置の長期信頼性低下及び歩留まり低下を防止できる。
【図面の簡単な説明】
【図1】本発明の一実施形態例の導電性プラグの堆積方法を示す。
【図2】従来の導電性プラグの堆積方法を示す。
【符号の説明】
1 バリアメタル
2 タングステン核形成膜群
3 タングステン埋込み膜群
4 タングステン核形成膜
5 タングステン埋込み膜
6 ボイド
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for depositing a conductive plug and a method for manufacturing a semiconductor device , and more particularly, to a method for depositing a conductive plug and a semiconductor with improved step coverage when tungsten is buried in a contact hole or a via hole of the semiconductor device. The present invention relates to a device manufacturing method .
[0002]
[Prior art]
The semiconductor device has a contact hole or a via hole (hereinafter, collectively referred to as a contact hole) that conducts the electrode and the wiring of the element or the wiring and the wiring. For this reason, several techniques for embedding a conductive plug (tungsten) in a contact hole have been developed (for example, JP-A-9-32137). Further, as the miniaturization progresses, the film thickness does not progress as much as the pattern size, and the aspect ratio, which is the ratio of the contact hole depth to the contact hole diameter, tends to increase.
[0003]
FIG. 2 shows a conventional method for depositing a conductive plug. As shown in FIG. 2A, first, a barrier metal 1 is formed on the side wall of a contact hole of a semiconductor device by a CVD method. Next, as shown in FIG. 4B, a reactive gas having a predetermined pressure is continuously guided to form a tungsten nucleation film 4 on the barrier metal 1. As shown in FIG. 6C, a reactive gas having a predetermined pressure is continuously guided to form a tungsten buried film 5 on the tungsten nucleation film 4 so as to bury a contact hole.
[0004]
[Problems to be solved by the invention]
In the above conventional conductive plug deposition method, the reactive gas is continuously guided, so that the side reactive product gas generated in the contact hole having a high aspect ratio is accumulated at the bottom of the contact hole, and the reactive gas is collected at the bottom of the contact hole. Can not lead to enough. As a result, the growth speed of the tungsten nucleation film 4 is slow and the film thickness is reduced at the bottom of the contact hole, so that the tungsten buried film 5 cannot be sufficiently grown at the bottom of the contact hole and a void 6 is generated.
[0005]
When the void 6 is generated, when the wiring is formed in the upper part of the contact hole in a later process, the void 6 may be exposed and the tungsten buried film 5 and the wiring may be disconnected. In addition, since the contact resistance or the through-hole resistance of the contact hole is increased and the step coverage is deteriorated, there is a risk that the long-term reliability is lowered and the yield is lowered.
[0006]
The present invention has been made in order to solve the above-described problems of the prior art, and a conductive plug deposition method and semiconductor device for improving step coverage of a contact hole having a high aspect ratio . An object is to provide a manufacturing method .
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the conductive plug deposition method of the present invention is a method of introducing a reactive gas into a processing chamber and depositing the conductive plug in a through hole or a contact hole. It is characterized in that a gas introduction step for introducing a gas and advancing deposition and a gas exhaust step for exhausting the gas in the processing chamber are alternately repeated.
[0008]
In the conductive plug deposition method of the present invention, the gas introduction step and the gas exhaust step are alternately repeated a plurality of times, so that the film thickness of the film is uniform throughout, and the conductive plug covers the contact hole with good coverage. Since it is embedded, step coverage is improved.
[0009]
In the conductive plug deposition method of the present invention, it is preferable that the gas exhausting step is terminated when the processing chamber pressure becomes 1/2 to 1/10 of the processing chamber pressure in the gas introduction step. In this case, since the exhaust time of the gas exhaust step can be appropriately selected, the next gas introduction step can be performed efficiently.
[0010]
A first stage having a gas introduction step for introducing WF 6 , SiH 4 and H 2 and an alternate gas exhaust step, a gas introduction step for introducing WF 6 and H 2 , and an alternate gas exhaust step; It is also a preferred embodiment of the present invention to sequentially have a second stage having In this case, since the tungsten nucleation film group is formed in the first stage and the tungsten buried film group is formed in the second stage, the step coverage is favorably improved.
[0011]
In the conductive plug deposition method of the present invention, the gas exhausting step may be a step of exhausting a side reactive product gas generated from the reactive gas.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a method for depositing a conductive plug of the present invention will be described with reference to the drawings based on an embodiment of the present invention. FIG. 1 shows a method for depositing a conductive plug according to an embodiment of the present invention. A semiconductor device has a contact hole with a high aspect ratio. The method for depositing the conductive plug according to the present embodiment includes a barrier metal process, a nucleation film process, and a buried film process, which are performed in this order in the processing chamber. Unlike the inside of the furnace that processes about 100 wafers at a time, the processing chamber processes one wafer.
[0013]
FIG. 4A shows a barrier metal process. First, a barrier metal 1 made of WN, T i N, T a N, or the like is formed on the sidewall of a contact hole of a semiconductor device by a CVD method, but a directional sputtering method or the like can also be used depending on the aspect ratio. In a contact hole having a high aspect ratio, when the barrier metal 1 is formed with good coverage, a good contact is obtained and the step coverage of tungsten is improved.
[0014]
FIG. 5B shows the nucleation film process (first stage). The nucleation film process is performed after the barrier metal process and includes a gas introduction step and a gas exhaust step. The gas introducing step, WF 6, S i H 4 where the pressure was set to 133-13300 [Pa], and supplies a reactive gas H 2, forming a tungsten nucleation layer group 2 on the barrier metal 1 Film. WF 6 is set to 10 to 100 [sccm], and S i H 4 is set to 4 to 50 [sccm]. In this process, by-reactive product gas is generated and collected at the bottom of the contact hole.
[0015]
In the gas exhausting step, the gas in the contact hole including the reactive gas and the side reactive product gas is exhausted. The exhaust time is selected so as to end when the processing chamber pressure becomes 1/2 to 1/10 of the gas introduction step.
[0016]
The gas introduction step and the gas exhaust step are alternately repeated a plurality of times. In the gas introduction step performed after the gas evacuation step of the tungsten nucleation film group 2, the reactive gas is sufficiently guided to the bottom of the contact hole, so that the film thickness becomes uniform. Since both steps are repeated a plurality of times, the tungsten nucleation film group 2 is formed with good coverage and the film thickness becomes 10 to 50 [nm].
[0017]
FIG. 5C shows the buried film process (second stage). The buried film process is performed after the nucleation film process, and includes a gas introduction step and a gas exhaust step as in the nucleation film process. In the gas introduction step, a reactive gas of WF 6 and H 2 having a pressure set to 6650 to 53200 [Pa] is supplied, and the tungsten buried film group 3 is formed on the tungsten nucleation film group 2. WF 6 is set to 50 to 500 [sccm], and H 2 is set to 500 to 5000 [sccm].
[0018]
In the gas exhaust step, the gas in the contact hole is exhausted as in the nucleation film process. The exhaust time is selected so as to end at a predetermined time. The gas introduction step and the gas exhaust step are alternately repeated a plurality of times. Similar to the nucleation film process, the tungsten buried film group 3 is formed with good coverage, and the film thickness becomes 50 to 500 [nm].
[0019]
Since the tungsten buried film group 3 fills the contact hole with good coverage and no void is generated, the step coverage of the conductive plug is improved.
[0020]
Reactive gas, material gas consisting of WF 6, and consists of a reducing gas consisting of S i H 4 or H 2 and the like. It is preferable to introduce the reactive gas separately into the material gas and the reducing gas in advance. In the gas introduction step of the nucleation film process and the buried film process, the material gas is diffused in advance to the bottom of the contact hole, and then the reducing gas is introduced. Since the reducing gas has a higher diffusion rate than the material gas and both gases diffuse uniformly to the bottom of the contact hole, the tungsten nucleation film group 2 and the tungsten buried film group 3 with good coverage are formed. Except for the gas introduction step of the nucleation film process and the buried film process, the process is the same as described above.
[0021]
The conductive plug deposition method of the present invention can also be applied to the formation of other portions of the semiconductor device. In the case of fine wiring with a high aspect ratio, the gas introduction step and the gas exhaust step are repeated a plurality of times to form a film having a certain thickness. In the case of embedding between interlayer films, a gas introduction step and a gas exhaust step are performed in one step to form a desired film thickness.
[0022]
According to the above embodiment example, by repeating the gas introduction step and the gas exhaust step alternately a plurality of times, the film thickness of the film becomes uniform as a whole, and the conductive plug fills the contact hole with good coverage. Step coverage is improved.
[0023]
Although the present invention has been described based on the preferred embodiment, the method for depositing the conductive plug of the present invention is not limited to the configuration of the above embodiment, and the configuration of the above embodiment. The method for depositing the conductive plug with various modifications and alterations is also included in the scope of the present invention.
[0024]
【The invention's effect】
As described above, in the conductive plug deposition method of the present invention, the film introduction film thickness becomes uniform as a whole by alternately repeating the gas introduction step and the gas exhaust step a plurality of times. Since the contact hole is embedded with good coverage, step coverage is improved. For this reason, the disconnection between the contact hole and the wiring and the increase in resistance are prevented, so that the long-term reliability and yield of the semiconductor device can be prevented from decreasing.
[Brief description of the drawings]
FIG. 1 illustrates a method for depositing a conductive plug according to an embodiment of the present invention.
FIG. 2 shows a conventional method for depositing a conductive plug.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Barrier metal 2 Tungsten nucleation film group 3 Tungsten embedding film group 4 Tungsten nucleation film 5 Tungsten embedding film 6 Void

Claims (5)

処理室内に反応性ガスを導入してスルーホール又はコンタクトホール内に導電性プラグを堆積する方法において、
処理室内にWF ガスからなる材料ガスを予め拡散した後、SiH からなる還元ガスを導入るガス導入ステップと、これに交互する前記処理室内のガスを排気するガス排気ステップとを交互に繰り返す第1段階と、
前記処理室内にWF ガスからなる材料ガスを予め拡散した後、H からなる還元ガスを導入するガス導入ステップと、これに交互する前記処理室内のガスを排気するガス排気ステップとを交互に繰り返す第2段階とを順次有することを特徴とする導電性プラグの堆積方法。
In a method of depositing a conductive plug in a through hole or a contact hole by introducing a reactive gas into a processing chamber,
After pre-diffused material gas of WF 6 gas into the process chamber, a gas introduction step you introducing a reducing gas comprising SiH 4, and a gas exhaust step for exhausting the processing chamber of the gas alternately to alternately The first stage to repeat ;
A gas introducing step for introducing a reducing gas consisting of H 2 after a material gas consisting of WF 6 gas is diffused in advance into the processing chamber, and a gas exhausting step for exhausting the gas in the processing chamber alternately are alternately performed. A method for depositing conductive plugs comprising sequentially repeating second steps .
前記ガス排気ステップは、処理室内圧力が前記ガス導入ステップにおける処理室内圧力の1/2〜1/10となった時点で終了する、請求項1に記載の導電性プラグの堆積方法。  2. The conductive plug deposition method according to claim 1, wherein the gas exhausting step is ended when the processing chamber pressure becomes ½ to 1/10 of the processing chamber pressure in the gas introduction step. 半導体装置のコンタクトホールにバリアメタルを形成する工程と、Forming a barrier metal in a contact hole of a semiconductor device;
処理室内にWFWF in the processing chamber 6 ガスからなる材料ガスを予め拡散した後、SiHAfter pre-diffusing a material gas consisting of gas, SiH 4 からなる還元ガスを導入するガス導入ステップと、これに交互する前記処理室内のガスを排気するガス排気ステップとを交互に繰り返して、核形成膜を前記バリアメタル上に形成する工程と、A step of forming a nucleation film on the barrier metal by alternately repeating a gas introduction step of introducing a reducing gas and a gas exhaust step of exhausting the gas in the processing chamber alternately with the gas,
前記処理室内にWFWF in the processing chamber 6 ガスからなる材料ガスを予め拡散した後、HAfter pre-diffusing the material gas consisting of gas, H 2 からなる還元ガスを導入するガス導入ステップと、これに交互する前記処理室内のガスを排気するガス排気ステップとを交互に繰り返して、埋め込み膜を前記核形成膜上に形成する工程とを、有することを特徴とする半導体装置の製造方法。A step of forming a buried film on the nucleation film by alternately repeating a gas introduction step for introducing a reducing gas and a gas exhaust step for exhausting the gas in the processing chamber alternately. A method for manufacturing a semiconductor device.
前記ガス排気ステップは、処理室内圧力が前記ガス導入ステップにおける処理室内圧力の1/2〜1/10となった時点で終了する、請求項3に記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3, wherein the gas exhausting step ends when the processing chamber pressure becomes ½ to 1/10 of the processing chamber pressure in the gas introduction step. 前記コンタクトホールにバリアメタルを形成する工程をCVD法により行う、請求項3又は4に記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 3, wherein the step of forming a barrier metal in the contact hole is performed by a CVD method.
JP2000284967A 2000-09-20 2000-09-20 Method for depositing conductive plug and method for manufacturing semiconductor device Expired - Fee Related JP4303409B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000284967A JP4303409B2 (en) 2000-09-20 2000-09-20 Method for depositing conductive plug and method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000284967A JP4303409B2 (en) 2000-09-20 2000-09-20 Method for depositing conductive plug and method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JP2002093746A JP2002093746A (en) 2002-03-29
JP4303409B2 true JP4303409B2 (en) 2009-07-29

Family

ID=18769110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000284967A Expired - Fee Related JP4303409B2 (en) 2000-09-20 2000-09-20 Method for depositing conductive plug and method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP4303409B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4115849B2 (en) * 2003-01-28 2008-07-09 東京エレクトロン株式会社 Method for forming W-based film and W-based film
JP4798688B2 (en) 2004-08-26 2011-10-19 エルピーダメモリ株式会社 Manufacturing method of semiconductor device
KR100745066B1 (en) 2005-03-24 2007-08-01 주식회사 하이닉스반도체 Method for fabricating metal plug of semiconductor device
US7273811B2 (en) * 2005-06-27 2007-09-25 The Regents Of The University Of California Method for chemical vapor deposition in high aspect ratio spaces
JP4864368B2 (en) * 2005-07-21 2012-02-01 シャープ株式会社 Vapor deposition method
US7235485B2 (en) * 2005-10-14 2007-06-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device
JP2008169487A (en) * 2008-01-25 2008-07-24 Tokyo Electron Ltd Method for depositing w-based film
US20230317458A1 (en) * 2022-04-05 2023-10-05 Applied Materials, Inc. Gap fill enhancement with thermal etch

Also Published As

Publication number Publication date
JP2002093746A (en) 2002-03-29

Similar Documents

Publication Publication Date Title
US5637533A (en) Method for fabricating a diffusion barrier metal layer in a semiconductor device
TWI571524B (en) Systems and methods for selective tungsten deposition in vias
JP4191900B2 (en) Method for forming tungsten contact plug of semiconductor device
US5960320A (en) Metal wiring layer forming method for semiconductor device
CN1397993A (en) Method for generating blocking metal layer
JPH09148268A (en) Method for manufacturing semiconductor device
JP2005340816A (en) POLYCRYSTALLINE SiGe JUNCTION FOR ADVANCED DEVICE
JP4303409B2 (en) Method for depositing conductive plug and method for manufacturing semiconductor device
KR100511913B1 (en) The method for forming bitline in semiconductor device
US5183781A (en) Method of manufacturing semiconductor device
JP2005322882A (en) Method of manufacturing metal wiring of semiconductor element using low-temperature barrier metal layer
US5360766A (en) Method for growing a high-melting-point metal film
KR20040059842A (en) Method for forming a contact hole in a semiconductor device
KR100745066B1 (en) Method for fabricating metal plug of semiconductor device
JPH03248534A (en) Manufacture of semiconductor element
US7022601B2 (en) Method of manufacturing a semiconductor device
JPH08288390A (en) Semiconductor device and manufacture thereof
JPH02162722A (en) Manufacture of semiconductor device
KR100357224B1 (en) Fabrication method of contact plug
KR100440260B1 (en) Method of forming a bitline in a semiconductor device
JPH0729850A (en) Fabrication of semiconductor device
KR20020033851A (en) Method of making gete electrode in semiconductor device
JP2617090B2 (en) Semiconductor device contact manufacturing method
KR100376258B1 (en) Method for forming a plug of a semiconductor device
JPH01298717A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070813

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081217

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081222

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090220

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090406

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090424

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120501

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120501

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120501

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120501

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130501

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140501

Year of fee payment: 5

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees