JP4302663B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming a low-resistance metal film on a base film via a barrier metal film.

  With the recent demand for higher speed and larger capacity of semiconductor devices, reduction of wiring resistance and wiring capacity of metal wiring portions is required. For this reason, metal wiring and connection holes having copper or copper alloy as the main conductive layer have been developed, but further improvements are required.

  A so-called damascene method is known as one of conventional methods for forming a metal wiring having copper or a copper alloy as a main conductive layer. Such a technique is described in, for example, C.W.Kaanta et.al, VMIC Conf. Proc. 8, P. 144 (1991).

  In the damascene method, an insulating film is grown on a substrate, a wiring groove or connection hole is formed in the insulating film, a metal film is then formed on the upper surface of the insulating film and in the wiring groove or connection hole, and then chemical mechanical In this method, a metal wiring or a plug is formed in the wiring groove or the connection hole through a process of removing the metal film from the upper surface of the insulating film by polishing (CMP (chemical mechanical polishing) method).

  Next, the conventional damascene method will be described more specifically with reference to FIG.

  First, as shown in FIG. 1A, a silicon oxide film 102 having a thickness of 400 nm is grown on the lower wiring 101 by a CVD method, and a silicon nitride film 103 having a thickness of 50 nm is formed thereon as an antireflection film. Form. Thereafter, as shown in FIG. 1B, wiring grooves 104a or connection holes 104b are formed by ordinary photolithography and etching.

  Subsequently, as shown in FIG. 1C, a barrier metal film 105 is formed on the inner surface of the wiring groove 104a or the connection hole 104b and the upper surface of the silicon oxide film 102. As the barrier metal film 105, for example, a titanium nitride (TiN) film having a thickness of 50 nm or a β-phase tantalum film having a thickness of 50 nm is formed by sputtering. Further, a copper film 106 having a thickness of 800 nm is formed on the barrier metal film 105 by sputtering. Then, vacuum annealing is performed at 400 ° C. for 3 minutes to completely embed the copper film 106 in the wiring groove 104a or the connection hole 104b.

  Finally, as shown in FIG. 1D, the copper film 106 and the barrier metal film 105 are removed from the upper surface of the silicon nitride film 103 by CMP. Then, the copper film 105 remaining in the wiring groove 104a is used as a wiring, or the copper film 106 remaining in the connection hole 104b is used as a plug. In the chemical mechanical polishing, an abrasive containing a powder such as alumina and a chemical solvent such as an acid that dissolves metal is used.

  The antireflection film made of the silicon nitride film 103 described above is necessary to prevent reflection of exposure light and improve the exposure accuracy of the resist when the resist formed on the silicon oxide film 102 is exposed.

  As described above, a silicon nitride film is generally used as the antireflection film. However, the silicon nitride film has a high relative dielectric constant, and there is a problem in that the parasitic capacitance generated by the upper and lower wirings is increased to increase the signal delay time.

  Copper is known to diffuse quickly in silicon substrates and silicon oxide films, and this is described in E. R. Weber, Appl. Phys. A30, 1 (1983). The barrier metal film 105 described above is used to prevent such copper diffusion. The necessity of barrier metal is described in, for example, T. Kouno et.al, J. Electrochem. Soc, 145, 2164 (1998).

  The main characteristics required for the barrier metal film are the following three.

  First, the specific resistance is low, second, the diffusion barrier performance is excellent, and third, the polishing rate is fast.

  That is, if a barrier metal having a high specific resistance is used, the wiring resistance increases and the signal delay time in the wiring increases. Further, when the diffusion barrier performance of the barrier metal is inferior, copper diffuses into the silicon oxide film and the semiconductor element performance is deteriorated. Further, when the polishing rate is slow, as shown in FIG. 2, the barrier metal film 105 may remain on the insulating film 103 without being completely removed, and the wiring may be short-circuited on the insulating film. .

  Titanium nitride film (TiN), β-phase tantalum film (βTa), α-phase tantalum film (αTa), tantalum nitride film with high tantalum content (Ta-rich TaN), and nitridation with high nitrogen content Table 1 shows the specific resistance, diffusion barrier performance, and CMP rate for each of tantalum (N-rich TaN).

  In Table 1, the superiority or inferiority of the diffusion barrier performance is a value summarized based on “Latest Development of Cu Wiring Technology”, page 172 of Realize (1998).

  According to Table 1, TiN has a low resistance and a high CMP rate, but the diffusion barrier performance is not sufficient. βTa, αTa, and Ta-rich TaN all have low resistance and relatively good diffusion barrier performance, but have a slow CMP rate and are not easily corroded by acid. N-rich TaN has a high CMP rate and good diffusion barrier performance, but high specific resistance.

  In addition, when the barrier metal film having a low polishing rate is excessively polished on the insulating film, if the polishing rate of the barrier metal film is lower than the polishing rate of the copper film, as shown in FIG. There arises a problem called a recess in which the copper film 106 in the hole 104b sinks. For example, if the tantalum polishing rate is 1/5 of the copper polishing rate, the removal of the 250 nm copper film cannot be avoided when removing the 50 nm thick tantalum film.

  From these facts, it can be seen that it is not easy to develop a single-layer barrier metal having all three conditions which are necessary characteristics as a barrier metal film.

  Japanese Patent Application Laid-Open No. 7-283219 discloses that a barrier metal is composed of a three-layer structure of titanium, titanium nitride, and tantalum. However, when the ratio of the thickness of the barrier metal film in the wiring groove or the connection hole is increased, the ratio of the copper film in the wiring groove or the connection hole is relatively decreased and the specific resistance value is increased. .

  It is an object of the present invention to have a low specific resistance in a wiring groove or connection hole, excellent diffusion barrier performance for copper embedded therein, and prevent polishing residue on an insulating film in which the wiring groove or connection hole is formed. Another object of the present invention is to provide a method of manufacturing a semiconductor device that can prevent a conductive film from being recessed in a wiring groove or a connection hole when polishing a barrier metal on an insulating film.

The above-described problem is, as illustrated in FIGS. 9 to 11, the step of forming the first film 26 made of the first refractory metal or the first refractory metal nitride on the insulating film 25, Forming a wiring groove or connection hole 28 in the first film 26 and the insulating film 25, and forming the first height on the inner surface of the wiring groove or connection hole 28 and on the upper surface of the first film 26. forming a second film 29 polishing rate by CMP than the melting point metal or the first refractory metal nitride comprising slower second refractory metal or second refractory metal nitride A step of forming a copper film 30 or a copper-containing alloy film on the second film 29, the copper film 30 or the copper-containing alloy film, the first film 26, and the second film 29, dividing by the chemical mechanical polishing from the top surface of the insulating film 25 other than the wiring grooves or the connection hole 28 Possess a step of the second tantalum refractory metal β phase, a tantalum α phase, the second refractory metal nitride is tantalum nitride having a low composition ratio than that of nitrogen tantalum The present invention is solved by a method for manufacturing a semiconductor device.

  In addition, the above-mentioned figure number and code | symbol were quoted in order to make an understanding of invention easy, and this invention is not limited to them.

  Next, the operation of the present invention will be described.

  According to the present invention, the first film made of the first refractory metal or the first refractory metal nitride is formed on the insulating film, and then the wiring groove or the connection hole is formed in the first film and the insulating film. After that, a second film made of the second refractory metal or the second refractory metal nitride is formed on the inner surface of the wiring groove or the connection hole and the upper surface of the first film, and the second film A main conductor film made of a copper film or a copper-containing alloy is formed on the film, and then the main conductor film, the first film, and the second film are removed from the upper surface of the insulating film other than the wiring groove or the connection hole. I have to.

  In this case, it is desirable that the first film has a higher polishing rate than the second film. If the polishing rate is high, the metal or metal nitride is prevented from remaining on the insulating film without being completely removed. In addition, since the first film does not remain in the wiring groove or the connection hole but the second film of the single layer remains as a barrier metal in the wiring groove or the connection hole, the barrier metal remains in the wiring groove or the connection hole. The occupation ratio of the main conductive film is not reduced.

  In this case, the first film is preferably made of a material that functions as an antireflection film in the photolithography method for forming the wiring groove or the connection hole. This eliminates the need to form a silicon nitride film on the insulating film as an antireflection film, thereby preventing an increase in inter-wiring capacitance.

  Note that the second film made of a refractory metal or a refractory metal nitride is preferably made of a material having a low resistance and a high diffusion barrier performance, and it does not matter if the polishing rate is high.

  As described above, according to the present invention, after the first film made of the first refractory metal or the first refractory metal nitride is formed on the insulating film, the first film and the insulating film are formed. A wiring groove or a connection hole is formed, and then a second film made of a second refractory metal or a second refractory metal nitride is formed on the inner surface of the wiring groove or the connection hole and the upper surface of the first film. Then, a main conductive film made of a copper film or a copper-containing alloy is formed on the second film, and then the main conductive film, the first film, and the second film are formed on an insulating film other than a wiring groove or a connection hole. Since the first film includes the step of removing from the upper surface and the polishing rate is higher than that of the second film, the metal or metal nitride is not completely removed on the insulating film. It can be prevented from remaining.

  In addition, since the first film does not remain in the wiring groove or the connection hole but the single-layer second film remains in the wiring groove or the connection hole as a barrier metal, the barrier metal is connected to the wiring groove or the connection hole. It is possible to prevent a decrease in the occupation ratio of the main conductive film in the hole.

  In this case, since the first film is made of a material that functions as an antireflection film in the photolithography method for forming the wiring groove or the connection hole, silicon nitride is formed on the insulating film as the antireflection film. It is not necessary to form a film, and an increase in capacitance between wirings can be prevented.

  Embodiments of the present invention will be described below with reference to the drawings.

(Description of First Embodiment)
4 to 7 are cross-sectional views showing the manufacturing steps of the semiconductor device showing the first embodiment of the present invention.

  First, steps required until a state as shown in FIG.

4A, a MOS transistor 3 is formed in a region surrounded by a field oxide film 2 in a silicon substrate (semiconductor substrate) 1. The MOS transistor 3 includes a gate electrode 3b formed on the silicon substrate 1 via a gate oxide film 3a, and first and second impurity diffusion layers formed in the silicon substrate 1 on both sides of the gate electrode 3b. 3d, 3s. Also, MOS transistor 3 is covered with the first interlayer insulating film 4 made of SiO _2.

  A contact hole 5 is formed in a region of the first interlayer insulating film 4 above the first impurity diffusion layer 3d, and tungsten (W) is formed in the contact hole 5 via a titanium nitride (TiN) film 6. ) The membrane 7 is filled.

Next, after forming a second interlayer insulating film 8 made of a SiO ₂ -containing insulating material or SiO ₂ on the first interlayer insulating film 4 and the tungsten film 7, as shown in FIG. The second interlayer insulating film 8 is patterned by photolithography to form a first wiring groove 9 having a width of 0.2 to 0.3 μm. A part of the wiring groove 9 is located on the contact hole 5.

Subsequently, as shown in FIG. 5, tantalum carbonate (Ta ₂ (CO ₃ ) ₅ ) bonded in the form of fine particles in the first wiring trench 9 and along the upper surface of the second interlayer insulating film 8. A first tantalum (Ta) film 11 containing molecules 10 is formed to a thickness of 20 to 50 nm by plasma sputtering. The first tantalum film 11 functions as a barrier metal film.

  The first tantalum film 11 is formed under the condition that carbon dioxide gas is introduced into a chamber (not shown) at 10 sccm, argon (Ar) gas is introduced at a flow rate of 50 sccm, and the pressure in the atmosphere is set to 5 mTorr. Is done. Then, the molecules 10 generated by reacting the carbon dioxide plasma with the tantalum jumping out of the target T are mixed into the first tantalum film 11. At the time of sputtering, the target T made of tantalum is disposed so as to face the second insulating film 8.

  Next, as shown in FIG. 6A, a first copper (Cu) film 12 is formed on the first tantalum film 11 to a thickness of nm by MOCVD, sputtering, or plating. The first copper film 12 is completely filled in the first wiring trench 9 by vacuum annealing at 400 ° C.

  Thereafter, the first copper film 12 is polished by a CMP (Chemical Mechanical Polishing) method using a polishing agent containing powder such as alumina and an inorganic acid.

  Then, when the first copper film 12 on the second interlayer insulating film 8 is removed as shown in FIG. 6B and the first tantalum film 11 is exposed, an abrasive containing glucose is used. Is used to polish the first tantalum film 11 by a chemical mechanical polishing method.

The (Ta ₂ (CO ₃ ) ₅ ) molecules 10 contained in the first tantalum film 11 react with glucose ions, which are organic complex ions, and dissolve. After the (Ta ₂ (CO ₃ ) ₅ ) molecules 10 are dissolved, the first tantalum film 11 is formed with a microcavity 10a as shown in FIG. It becomes mechanically brittle and the cutting speed by polishing the first tantalum film 11 increases.

  Further, if an oxidizing agent is not included in the polishing agent (chemical solution), the atomic bond structure is not easily broken by oxidation of copper, so that the speed at which the first copper film 12 is dissolved by complex ions is made relatively slow. Is possible. In this case, the polishing rate of the first copper film 12 can be made equal to or less than the polishing rate of the first tantalum film 11, and the first copper film 12 in the first wiring trench 9 is made. The occurrence of recession is prevented.

  In the polishing of the first tantalum film 11, the polishing pressure was 3.5 PSI, and the rotation speed of the turntable on which the silicon substrate 1 was mounted and the carrier head that supports the silicon substrate 1 were both 60 rpm.

After removing the first tantalum film 11 from the second interlayer insulating film 8 by the above polishing and (Ta ₂ (CO ₃ ) ₅ ) molecule 10 dissolution cycle, the polishing is stopped, and FIG. As shown in a), the first tantalum film 11 and the first copper film 12 remaining in the first wiring trench 9 are used as the first wiring 13.

  Thereafter, as shown in FIG. 7B, a third interlayer insulating film 14 is formed on the second interlayer insulating film 8 and the first wiring 13. Then, a connection hole 15 a and a second wiring groove 15 b are formed in the third interlayer insulating film 14, and a second tantalum film 16 and a second copper film are formed therein by a method similar to that for the first wiring 13. 17 is filled, whereby the plug and the second wiring 17 are formed.

  Note that tartaric acid, phthalic acid, other organic acids, or a solvent containing carbon may be used in place of glucose used as a chemical component in chemical mechanical polishing. In addition to tantalum, tantalum nitride containing carbon alloy molecules may be used as the barrier metal film. Further, as the metal film filled in the wiring groove or the connection hole, a copper alloy, aluminum, aluminum alloy, tungsten, or tungsten alloy may be used in addition to the copper film.

  Next, the conventional polishing rate of each of the tantalum film and the copper film by a conventional method using a polishing agent containing no organic acid, and the respective book of the tantalum film and the copper film using a polishing agent containing an organic acid A difference in polishing rate according to the embodiment is shown in FIG. According to FIG. 8, the polishing rate of the copper film was about 6 times that of the conventional tantalum film. However, when the copper film and the carbon alloy molecule-containing tantalum film were polished using an organic acid as in this embodiment, the polishing rate of the tantalum film was faster than the polishing rate of the copper film.

  Further, according to FIG. 8, the polishing rate of copper is faster when a chemical solution not containing an organic acid is used. The copper film and the tantalum film may be continuously polished by using them.

  As described above, even when carbon alloy molecules were included in the barrier metal film, the barrier performance against copper did not deteriorate and the specific resistance did not increase.

By the way, although the above-described barrier metal film 11 has been described as being formed by a plasma sputtering method, it may be formed by a CVD method. For example, when the tantalum film 11 is formed using an organic material containing carbon such as pentaethoxytantalum (Ta (OC ₂ H ₅ ) ₅ ), the tantalum film contains carbon. Since carbon in the tantalum film reacts and dissolves with the organic complex ions contained in the polishing solution, the tantalum film becomes mechanically brittle and the polishing rate is increased.

(Second Embodiment)
9 to 11 are cross-sectional views showing the manufacturing steps of the semiconductor device showing the second embodiment of the present invention. 9 to 11, the same reference numerals as those in FIG. 4A indicate the same elements.

  First, steps required until a state as shown in FIG.

  In FIG. 9A, a MOS transistor 3 is formed in a region surrounded by a field oxide film 2 in a silicon substrate (semiconductor substrate) 1. The MOS transistor 3 has the same structure as that of the first embodiment.

The MOS transistor 3 and the field oxide film 2 are covered with a first interlayer insulating film 4 made of SiO ₂ . A contact hole 5 is formed on the first impurity diffusion layer 3b in the first interlayer insulating film 4, and a tungsten (W) film is interposed in the contact hole 5 via a first titanium nitride (TiN) film 6. 7 is filled.

Next, after forming a second interlayer insulating film 8 made of a SiO ₂ -containing insulating material or SiO _2, the second interlayer insulating film 8 is patterned by photolithography to pass through the contact hole 5. A wiring groove 20 is formed. Then, after forming the second titanium nitride film 21 in the first wiring trench 20 and along the upper surface of the second interlayer insulating film 8, the first copper ( Cu) film 22 is formed.

  The second titanium nitride film 21 is formed in order to prevent the copper element constituting the first copper film 22 from diffusing into the second interlayer insulating film 8.

  Thereafter, the first copper film 22 and the second titanium nitride film 21 are polished and removed from the upper surface of the second interlayer insulating film 8, and the first copper film 22 remaining in the first wiring trench 20 is removed. The second titanium nitride film 21 is used as the first wiring 23.

Further, a first silicon nitride (SiN) film 24 is formed on the second interlayer insulating film 8 and the first wiring 23 to a thickness of about 50 nm by a CVD method, and this is used as a barrier film for preventing copper diffusion. use. Subsequently, a third interlayer insulating film 25 made of a silicon oxide film (SiO ₂ ) is grown on the silicon nitride film 24 to a thickness of 400 nm by the CVD method, and a third titanium nitride (TiN) film is formed thereon. 26 is grown to a thickness of 50 nm by sputtering.

  As sputtering conditions for the growth of the third titanium nitride film 26, sputtering power is 12 kW, argon gas and nitrogen gas are introduced into the chamber at a flow ratio of 1: 4, and the atmospheric gas pressure in the chamber is increased. Set to 3 mTorr.

  Thereafter, a photoresist 27 is applied on the third titanium nitride film 26, and this is exposed and developed to form a window 27a. The window 27 a is formed at a position overlapping at least a part of the first wiring 23.

  Then, when the third titanium nitride film 26, the third interlayer insulating film 25, and the first silicon nitride film 24 are sequentially etched through the window 27a, a connection hole 28 having a depth of about 500 nm is formed in these films. . Thereafter, when the photoresist 27 is removed, a cross-sectional shape as shown in FIG. 9B is obtained.

  Next, as shown in FIG. 10A, a first βTa film (barrier metal film) 29 having a film thickness of 20 nm and a film thickness of 100 nm are formed on the upper surface of the third titanium nitride film 26 and the inner surface of the connection hole 28. The second copper (Cu) film 30 was sequentially formed by sputtering, and the film thickness of the second copper film 30 was increased by 700 nm by electrolytic plating to a total of 800 nm.

  As sputtering conditions for the growth of the first βTa film 29, the sputtering power was set to 6 kW, argon gas was introduced into the chamber, and the internal pressure was set to 3 mTorr. Further, as sputtering conditions for the growth of the second copper film 30, the sputtering power was set to 12 kW, argon gas was introduced into the chamber, and the argon gas pressure was set to 3 mTorr.

  Note that a multi-chamber system that performs vacuum transfer was used as the sputtering apparatus.

  Thereafter, the second copper film 30, the βTa film 29, and the third TiN film 26 grown outside the connection hole 28 are removed by a normal CMP method, whereby a copper film as shown in FIG. A plug 31 having a main conductive layer 30 is formed in the connection hole 28.

  Next, as shown in FIG. 11A, a second silicon nitride film 32 having a thickness of 50 nm and a fourth interlayer insulating film having a thickness of 400 nm are formed on the third interlayer insulating film 25 and the plug 31. 33 and a fourth TiN film 34 having a thickness of 50 nm are formed in this order, and then the films 32 to 34 are patterned by a photolithography method to form the second wiring groove 35. The second wiring groove 35 has a planar shape such that a part thereof passes over the plug 31.

  Subsequently, a second βTa film 36 having a thickness of 20 nm and a third copper film 37 having a thickness of 800 nm are sequentially formed on the inner surface of the second wiring trench 35 and the upper surface of the second silicon nitride film 32. Thereafter, the third copper film 37 and the second βTa film 36 are removed from the outside of the second wiring trench 35 by CMP, thereby making the copper film 37 the main conductive layer as shown in FIG. A second wiring 38 serving as a layer is formed in the second wiring groove 35.

  As described above, in this embodiment, a TiN film that is easily polished is formed on the interlayer insulating film, and the TiN film and the interlayer insulating film are continuously patterned to form wiring grooves or connection holes. Thereafter, a barrier meta film made of βTa having excellent copper diffusion resistance and low resistance was formed, and a copper film was formed on the barrier metal film.

  According to this, since there is a TiN film having a high polishing rate by the CMP method and having a light reflection preventing function on the interlayer insulating film, resist exposure can be accurately performed when forming a wiring groove and a connection hole, In addition, the TiN film is easily removed by polishing performed subsequent to the copper film and the barrier metal film, thereby preventing the βTa and TiN conductive films from remaining on the interlayer insulating film. In addition, a single-layer barrier metal film made of βTa, which has excellent resistance to copper diffusion and remains low, remains in the connection hole or wiring groove, reducing the occupation ratio of the main conductive layer in the wiring groove or connection hole. I will not let you.

  In addition, when a TiN film is used as an antireflection film, the end point of polishing can be detected more easily than when a silicon nitride film is used, and the interlayer insulating film can be prevented from being thinned.

  Instead of the βTa (β phase tantalum) film described above, a high melting point metal film such as αTa (α phase tantalum) film, or a high melting point such as tantalum nitride (Ta-rich Ta) having a high tantalum content. A metal nitride film may be used. The tantalum nitride having a high tantalum content is tantalum nitride having a composition ratio of tantalum to nitrogen of 1 or more.

  In addition to titanium nitride, high melting point metal nitride films such as tantalum nitride (N-rich Ta) with a high nitrogen content and high polishing rate There is a melting point metal film. Tantalum nitride having a high nitrogen content is tantalum nitride in which the composition ratio of tantalum to nitrogen is less than 1. The refractory metal film or refractory metal nitride formed directly on the interlayer insulating film is preferably a material whose polishing rate is at least twice that of the silicon oxide film, and has a specific resistance of 1000 μΩcm or less. Is preferred.

  Further, the material for the main conductive film of the wiring or plug may be an alloy containing copper in addition to copper.

(Third embodiment)
12 and 13 are cross-sectional views showing the manufacturing steps of the semiconductor device showing the third embodiment of the present invention. 12 and 13, the same reference numerals as those in FIG. 4A indicate the same elements.

  First, steps required until a state as shown in FIG.

  In FIG. 12A, a MOS transistor 3 is formed in a region surrounded by a field oxide film 2 in a silicon substrate (semiconductor substrate) 1. The MOS transistor 3 has the same structure as that of the first embodiment.

The MOS transistor 3 and the field oxide film 2 are covered with a first interlayer insulating film 4 made of SiO ₂ . A contact hole 5 is formed on the first impurity diffusion layer 3b in the first interlayer insulating film 4, and a tungsten (W) film is interposed in the contact hole 5 via a first titanium nitride (TiN) film 6. 7 is filled.

Next, after forming a second interlayer insulating film 8 made of a SiO ₂ -containing insulating material or SiO _2, the second interlayer insulating film 8 is patterned by photolithography to pass through the contact hole 5. A wiring groove 20 is formed. Then, after forming the second titanium nitride film 21 in the first wiring trench 20 and along the upper surface of the second interlayer insulating film 8, the first copper ( Cu) film 22 is formed.

  Thereafter, the first copper film 22 and the second titanium nitride film 21 are polished and removed from the upper surface of the second interlayer insulating film 8, and the first copper film 22 remaining in the first wiring trench 20 is removed. The second titanium nitride film 21 is used as the first wiring 23.

  Further, a first silicon nitride (SiN) film 41 having a thickness of 50 nm and a third interlayer insulating film 42 having a thickness of 750 nm are sequentially formed on the second interlayer insulating film 8 and the first wiring 23 by a CVD method. Thereafter, an N-rich TaN film 43 having a thickness of 50 nm is grown on the third interlayer insulating film 42 by sputtering.

  As sputtering conditions for growing the N-rich TaN film 43, the sputtering power is 6 kW, argon gas and nitrogen gas are introduced into the chamber at a flow rate ratio of 1: 4, and the atmospheric gas pressure in the chamber is adjusted. Set to 3 mTorr.

  Thereafter, as shown in FIG. 12B, a connection hole 44 having a depth of 100 nm is formed from the lower part of the third interlayer insulating film 42 to the first silicon nitride film 41 by a photolithography method using two resists. Then, a second wiring trench 45 is formed from the N-rich TaN film 43 to the upper portion of the third interlayer insulating film 43.

  The connection hole 44 is formed so as to overlap a part of the first wiring 23, and the second wiring groove 45 is formed so that a part thereof overlaps the connection hole 44. The order of forming the connection holes 44 and the second wiring grooves 45 is not limited.

  Next, a 20-nm-thick Ta-rich TaN film 46 and a 100-nm-thick second copper film 47 are sputtered on the inner surface of the connection hole 44 and the second wiring groove 45 and the upper surface of the N-rich TaN film 43. Are formed in order. Thereafter, the film thickness of the second copper film 47 is grown by 1400 nm by electrolytic plating so that the total becomes 1500 nm.

  As sputtering conditions for the growth of the Ta-rich TaN film 46, the sputtering power is 6 kW, argon gas and nitrogen gas are introduced into the chamber at a flow ratio of 4: 1, and the atmospheric gas pressure in the chamber is 3 mTorr. Set to. Further, as sputtering conditions for growing the second copper film 47, the sputtering power was set to 12 kW, argon gas was introduced into the chamber, and the argon gas pressure was set to 3 mTorr.

  Note that a multi-chamber system that performs vacuum transfer is used as the sputtering apparatus.

  Thereafter, when the second copper film 47, the Ta-rich TaN film 46, and the third TiN film 43 grown outside the connection hole 44 and the second wiring groove 45 are removed by a normal CMP method, FIG. As shown in b), a plug 48 having a copper film 47 as a main conductive layer is formed in the connection hole 44, and a second wiring 49 having the copper film 47 as a main conductive layer is formed in the second wiring groove 45. Is formed.

  According to the above method, since the N-rich TaN film having a high polishing rate by the CMP method and having the light reflection preventing function is formed in advance on the interlayer insulating film, the resist for forming the wiring trench and the connection hole is formed. The exposure can be performed with high accuracy, and the N-rich TaN film can be easily removed by polishing performed after the copper film and the barrier metal film, so that the conductive film of the TaN film remains on the interlayer insulating film. Is prevented. Moreover, since a single-layer barrier metal film made of Ta-rich TaN, which has excellent copper diffusion resistance and low resistance, remains in the connection hole or wiring groove, the main conductive layer is occupied in the wiring groove or connection hole. It does not reduce the rate.

  Further, when an N-rich TaN film is used as an antireflection film, the end point of polishing can be detected more easily than when a silicon nitride film is used, and the interlayer insulating film can be prevented from being thinned.

  Note that a refractory metal film such as a βTa film or an αTa film may be used instead of the refractory metal nitride film such as the Ta-rich TaN film.

  In addition, as a film formed directly on the interlayer insulating film, there is a refractory metal nitride film such as a titanium nitride film or a refractory metal film having a high polishing rate instead of N-rich TaN. The refractory metal film or refractory metal nitride formed directly on the interlayer insulating film is preferably a material whose polishing rate is at least twice that of the silicon oxide film, and has a specific resistance of 1000 μΩcm or less. Is preferred.

  Further, the material for the main conductive film of the wiring or plug may be an alloy containing copper in addition to copper.

1A to 1D are cross-sectional views showing a conventional method for forming a wiring or a plug in an insulating film. FIG. 2 is a cross-sectional view showing a state in which a barrier metal remains on an insulating film in a process of forming a wiring or a plug formed by a conventional technique. FIG. 3 is a cross-sectional view showing a state in which a recess is generated in a copper film remaining in a groove or a hole in a process of forming a wiring or a plug formed by a conventional technique. 4A and 4B are cross-sectional views (part 1) showing a process of forming a wiring or a plug in the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a sectional view (No. 2) showing a step of forming a wiring or a plug in the manufacturing process of the semiconductor device of the first embodiment of the present invention. 6A and 6B are cross-sectional views (part 3) showing the step of forming the wiring or plug in the manufacturing process of the semiconductor device of the first embodiment of the present invention. FIGS. 7A and 7B are cross-sectional views (part 4) showing the step of forming wirings or plugs in the manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 8 shows polishing rates of copper constituting the wiring or plug and tantalum constituting the barrier metal in the manufacturing process of the semiconductor device of the first embodiment of the present invention, and copper constituting the wiring or plug according to the conventional method. It is a figure which compares each polishing rate of the tantalum which comprises a barrier metal. FIGS. 9A and 9B are sectional views (No. 1) showing a process of forming wirings and plugs in the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIGS. 10A and 10B are cross-sectional views (part 2) showing a step of forming wirings and plugs in the manufacturing process of the semiconductor device of the second embodiment of the present invention. FIGS. 11A and 11B are sectional views (No. 3) showing a step of forming wirings and plugs in the manufacturing process of the semiconductor device of the second embodiment of the present invention. 12A and 12B are cross-sectional views (part 1) showing a process of forming wirings and plugs in the manufacturing process of the semiconductor device according to the third embodiment of the present invention. FIGS. 13A and 13B are cross-sectional views (part 2) showing the step of forming wirings and plugs in the manufacturing process of the semiconductor device of the third embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate (semiconductor substrate), 2 ... Field oxide film, 3 ... MOS transistor, 4 ... 1st interlayer insulation film, 5 ... Contact hole, 6 ... 1st titanium nitride (TiN)
Film, 7 ... tungsten film, 8 ... second interlayer insulating film, 9 ... wiring _{groove, 10 ... (Ta 2 (CO} 3) 5) Molecular, 11 ... barrier metal film, 12 ... copper film, 13 ... first Wiring, 14 ... third interlayer insulating film, 15a, 15b ... wiring groove, 16 ... tantalum film, 17 ... copper film, 20 ... wiring groove, 21 ... titanium nitride film, 22 ... copper film, 23 ... wiring, 24 ... Silicon nitride film, 25 ... interlayer insulating film, 26 ... titanium nitride, 27 ... resist, 28 ... connection hole, 29 ... beta phase tantalum film, 30 ... copper film, 31 ... plug, 32 ... silicon nitride film, 33 ... interlayer insulation 34: Titanium nitride film, 35: Wiring trench, 36 ... β phase tantalum, 37 ... Copper film, 38 ... Wiring, 41 ... Silicon nitride film, 42 ... Interlayer insulating film, 43 ... Nitrogen-rich tantalum nitride film, 44 ... Connection hole, 45 ... wiring groove, 46 ... tantalum-rich tantalum nitride film, 47 ... Film, 48 ... plug, 49 ... wiring.

Claims (4)

Forming a first film made of a first refractory metal or a first refractory metal nitride on the insulating film;
Forming a wiring groove or a connection hole in the first film and the insulating film;
A second polishing rate by chemical mechanical polishing is lower than that of the first refractory metal or the first refractory metal nitride on the inner surface of the wiring groove or the connection hole and the upper surface of the first film. Forming a second film made of a refractory metal or a second refractory metal nitride ;
Forming a copper film or a copper-containing alloy film on the second film;
The copper film or a copper-containing alloy film and said first film and said second film is perforated and removing by said chemical mechanical polishing from the top surface of the insulating film other than the wiring grooves or the connection holes ,
The second refractory metal is β-phase tantalum and α-phase tantalum, and the second refractory metal nitride is tantalum nitride having a composition ratio of nitrogen smaller than that of tantalum. Device manufacturing method. The combination of the first film and the second film includes the first refractory metal and the second refractory metal, the first refractory metal and the second refractory metal nitride, The first refractory metal nitride and the second refractory metal, or the first refractory metal nitride and the second refractory metal nitride, respectively. The manufacturing method of the semiconductor device of description.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first refractory metal nitride is titanium nitride or tantalum nitride having a composition ratio in which nitrogen is higher than tantalum.   2. The semiconductor according to claim 1, wherein the first film is made of a material that functions as an antireflection film for electromagnetic radiation that exposes a resist formed on the first film. Device manufacturing method.

Images