JP4300910B2 - Self-scanning light emitting device array driving apparatus and print head - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a light emitting element array driving device and the like, and more particularly to a light emitting element array driving device for driving a self-scanning light emitting element array used in a print head of an image forming apparatus such as a copying machine or a printer.
[0002]
[Prior art]
In a color image forming apparatus such as a color copying machine or a color printer, four photosensitive drums 1A, 1B, 1C, and 1D are arranged around an intermediate transfer belt 7 as shown in FIG. Yes. In each of the photosensitive drums 1A, 1B, 1C, and 1D, for example, a charger 2A, a print head 3A, a developing unit 4A, a cleaner 5A, and a static eliminator 6A are arranged around the photosensitive drum 1A. A toner image is formed with a yellow (Y) developer. Similarly, magenta (M), cyan (C), and black (K) toner images are formed on the photosensitive drums 1B, 1C, and 1D, respectively. This toner image is transferred to the intermediate transfer belt 7 while being aligned by the registration sensor 8 and synthesized, and the toner image is transferred to the recording paper 9 at a time. Then, the toner is conveyed to the fixing device 11 by the paper conveying belt 10 and the toner image is fixed on the recording paper 9 to form a color image. Such a color image forming apparatus is called a tandem system, and is capable of increasing the speed, and has become a mainstream color image forming apparatus.
[0003]
In such a tandem color image forming apparatus, since image forming units for forming toner images of Y, M, C, and K colors are independently arranged, it is necessary to reduce the size of each unit. Therefore, a print head that is as small as possible is required. In this respect, an LED print head (LPH) using an LED array in which a large number of LEDs are arranged does not require a mechanical drive mechanism and does not require a backlight unlike a liquid crystal element. This is one of the most suitable for downsizing the print head used in the printer. Further, since the response speed is high, it has an advantage that it is suitable for speeding up the image forming apparatus.
[0004]
Particularly, in recent years, an LPH using a self-scanning LED (SLED) has been proposed. The SLED employs a thyristor structure as a portion corresponding to a switch for selectively turning on / off the light emitting point. By adopting this thyristor structure, the switch section can be arranged on the same chip as the light emitting point, and the on / off timing of the switch can be selectively emitted by two signal lines. There is an advantage that lines can be shared and wiring can be simplified.
[0005]
The configuration of the SLED using such a thyristor and the driving device for driving the SLED will be described with reference to FIG.
As shown in FIG. 14, the SLED 20 includes n thyristors S <b> 1 to Sn, and the anode terminals A <b> 1 to An of each thyristor are connected to the power supply line 12. A power supply voltage VDD (VDD = 5 V) is supplied to the power supply line 12. Further, the cathode terminals K1, K3,... Of the odd-numbered thyristors S1, S3,... Are output terminals of an output circuit 21 constituted by a P-channel MOS transistor P1 and an N-channel MOS transistor N1 through a resistor R1A. That is, it is connected to the drains of the P-channel type MOS transistor P1 and the N-channel type MOS transistor N1.
[0006]
The cathode terminals K2, K4,... Of the even-numbered thyristors are the output terminals of the output circuit 22 constituted by the P-channel type MOS transistor P2 and the N-channel type MOS transistor N2 via the resistor R2A, that is, the P-channel type thyristor. The drains of the MOS transistor P2 and the N channel type MOS transistor N2 are connected.
[0007]
A transfer clock CK1 ′ is input from a signal generation circuit (not shown) to the input terminal of the output circuit 21, that is, the gates of the P-channel MOS transistor P1 and the N-channel MOS transistor N1. The output circuit 21 inverts the input transfer clock CK1 ′ and outputs the transfer clock CK1.
Similarly, a transfer clock CK2 ′ is input from a signal generation circuit (not shown) to the input terminal of the output circuit 22, that is, the gates of the P-channel MOS transistor P2 and the N-channel MOS transistor N2. The output circuit 22 inverts the input transfer clock CK2 ′ and outputs the transfer clock CK2.
[0008]
On the other hand, the gate terminals G1 to Gn of each thyristor are connected to the power supply line 16 via resistors 14 provided corresponding to the respective thyristors. A power supply voltage VGA is supplied to the power supply line 16.
The gate terminals G1 to Gn of the thyristors are connected to the anode terminals of the light emitting diodes L1 to Ln provided corresponding to the thyristors, respectively, and the gate terminals G1 to Gn-1 of the thyristors are The anode terminals of the diodes CR1 to CRn-1 are connected. The cathode terminals of the diodes CR1 to CRn-1 are connected to the gate terminals of the next stage. That is, the diodes CR1 to CRn-1 are connected in series.
[0009]
The anode terminal of the diode CR1 is connected to a signal generation circuit (not shown) through a resistor 18. A signal generation circuit (not shown) outputs a start signal CKS for instructing the start of transfer.
The cathode terminals of the light emitting diodes L1 to Ln are connected to the output terminal of the output circuit 23 via the resistor R3, that is, the drains of the P-channel MOS transistor P3 and the N-channel MOS transistor N3. A lighting signal ID ′ is input from a signal generation circuit (not shown) to the input terminal of the output circuit 23, that is, the gates of the P-channel MOS transistor P3 and the N-channel MOS transistor N3. The output circuit 23 inverts the input lighting signal ID ′ and outputs the lighting signal ID.
The light emitting diodes L1 to Ln are made of AlGaAsP or GaAsP as an example, and the band gap is about 1.5V.
[0010]
Next, the operation of the SLED 20 will be described with reference to the timing chart shown in FIG. In the following, a case where there are four thyristors (n = 4) will be described as an example.
First, when instructing the start of the operation, the start signal CKS is set to a high level as shown in FIG. 15A from a signal generation circuit (not shown). That is, a high level is input to the gate terminal G1 of the thyristor S1. As described above, when the transfer signal CK1 output from the output circuit 21 becomes low level as shown in FIG. 15B when the start signal CKS is high level, the thyristor S1 is turned on.
[0011]
That is, when the start signal CKS becomes high level, when the band gap of the diodes CR1 to CR3 is set to about 1.5 V as an example, the potentials of the gate terminals G1 to G4 (potentials with respect to the cathode terminal) as shown in FIG. ) Is about 5V, about 3.5V, about 2V, and about 0.5V, and among the odd-numbered thyristors S1 and S3 to which the transfer clock CK1 is supplied, the potential of the gate terminal is the highest, that is, the threshold voltage of the thyristor or higher. The thyristor S1 having the gate voltage of is turned on. At this time, since the transfer clock CK2 is at the high level as shown in FIG. 15C, the potential Φ2 of the cathode terminals K2 and K4 of the even-numbered thyristors S2 and S4 is about 5 V as shown in FIG. Since it remains high, thyristors S2 and S4 remain off. Further, since the lighting signal ID is at a high level as shown in FIG. 15D, the cathode terminals of the light emitting diodes L1 to L4 are high and the light emitting diodes L1 to L4 are not lit.
Then, when the lighting signal ID changes from the high level to the low level as shown in FIG. 15D, the potential of the cathode terminal of the light emitting diode L1 becomes low, and the light emitting diode L1 is turned on.
[0012]
Next, when the thyristor S1 is turned on, as shown in FIG. 15C, the transfer clock CK2 goes to a low level, and when the lighting signal ID goes to a high level, the even-numbered thyristor S2, to which the transfer clock CK2 is supplied, Among S4, S2 having the highest potential at the gate terminal, that is, the gate voltage equal to or higher than the threshold voltage of the thyristor is turned on, and the light emitting diode L1 is turned off.
Then, when the transfer clock CK1 becomes high level as shown in FIG. 15B, the thyristor S1 is turned off as shown in FIG. 15G, and the potential of the gate terminal G1 is gradually lowered by the resistor R1. The potential of the gate terminal G2 rises by about 1.5V to about 5V. Along with this, the potentials of the gate terminals G3 and G4 also rise by about 1.5V.
[0013]
Next, when the lighting signal ID changes from the high level to the low level as shown in FIG. 15D, the light emitting diode L2 is turned on.
Similarly, when the thyristor S2 is turned on, as shown in FIG. 15B, when the transfer clock CK1 becomes low level again and the lighting signal ID becomes high level, the thyristor S3 is turned on and the light emitting diode L2 is turned off. Lights up.
Then, as shown in FIG. 15C, when the transfer clock CK2 becomes high level, the thyristor S2 is turned off.
[0014]
Thus, the overlapping period (t shown in FIG. 12) in which the transfer clocks CK1 and CK2 are both low. _L The thyristors S1 to S4 are sequentially turned on by alternately switching between the high level and the low level while providing the light-emitting diodes L1 to L4. Are lit in sequence.
[0015]
Here, as a conventional technique, there is a technique relating to a self-scanning LED array and its drive circuit (see, for example, Patent Document 1).
[0016]
[Patent Document 1]
JP-A-2-263668 (page 8-11, FIG. 10)
[0017]
[Problems to be solved by the invention]
By the way, in recent years, silicon chips have been miniaturized, so that many functions can be mounted with a smaller chip area, and miniaturization and cost reduction have progressed. On the other hand, for example, when a fine design rule such as 0.25 μm is used, the power supply voltage of the I / O (input / output terminal) needs to be 3.3 V in relation to the breakdown voltage of the transistor. Therefore, it is required that the LED drive circuit can also be driven at 3.3V.
However, when the power supply voltage VDD is set to about 5V as in the above-described prior art, for example, to reduce the voltage to about 3.3V, it becomes difficult to sequentially turn on the thyristor due to the band gap of the thyristor. . That is, when the power supply voltage VDD is about 3.3V, for example, when the thyristor S1 is on, the potential of the gate terminal G2 is about 1.8V (power supply voltage 3.3V−band gap 1.5V). If the transfer clock CK2 is set to a low level in this state, the potential of the signal line Φ2 of the cathode terminal of the even-numbered thyristor becomes about 0.3V (the potential of the gate terminal G2 of 1.8V−the band gap of 1.5V). Therefore, no current can flow to the output circuit 22 side. As a result, no current can flow through the thyristor, making it difficult to turn on the thyristor. Since the turn-on time of the thyristor is proportional to the current flowing through the thyristor, in this state, the overlap period t _L Therefore, there is a problem that it is difficult to operate the thyristor stably.
[0018]
In addition, in the LPH used in the tandem color image forming apparatus, when the LED substrate generates heat due to the power consumed by the LPH LED substrate, the LED array thermally expands and causes Y, M, C, K. There has been a problem that an image shift (color shift) occurs between the color images.
[0019]
Furthermore, in order to arrange the LPH in a small space around the circumference of the photosensitive drum, it is necessary to configure the LPH to be small. For this purpose, the LED and the drive circuit can be mounted on a substrate having a small width area. There is also a need to do.
[0020]
Note that the technique described in Patent Document 1 does not disclose an effective technique for driving a thyristor with a low-voltage power supply.
[0021]
Accordingly, the present invention has been made based on such a technical problem, and an object of the present invention is to provide a light emitting element array driving apparatus capable of sequentially turning on light emitting elements at high speed and stably even with low voltage driving. Is to provide.
Another object of the present invention is to provide a light-emitting element array driving device with low power consumption in order to suppress the heat generation of LPH.
Still another object is to mount the light emitting element array driving device in a small space.
[0022]
[Means for Solving the Problems]
For this purpose, the light-emitting element array driving apparatus of the present invention includes a plurality of light-emitting elements, a power source that supplies power, and an input terminal that is provided corresponding to the plurality of light-emitting elements and inputs power from the power source. It has an output terminal that outputs the input power and a control terminal that inputs a control signal for outputting the input power from the output terminal. When the control signal is input to the control terminal, the on state is maintained and light is emitted. A plurality of switch elements each for enabling the elements to be lit, and when the drive signal generating means generates a drive signal for sequentially turning on the switch elements and outputs the drive signal to the output terminal of the switch element, In the turn-on period, the drive signal from the drive signal generating means is changed to a level shift voltage that is lower or higher than the power supply voltage by the level shift means. It is characterized in that to change the voltage value of the level shift voltage output level shift voltage changing means by further level shift means.
[0023]
Here, the level shift means has one end connected to the output end of the switch element, and the other end branched in parallel to the signal line connected to the capacitor and the signal line connected to the resistor, and connected to the drive signal generating means. It can be characterized by that. At this time, the level shift voltage changing means can change the voltage value of the level shift voltage by changing the charging time or discharging time of the capacitor disposed in the level shifting means.
Further, the drive signal generating means can output the drive signal to the output terminal of the switch element via the transfer current limiting resistor. At this time, the level shift voltage changing means may change the voltage value of the level shift voltage based on the resistance value of the transfer current limiting resistor.
[0024]
Further, when the present invention is regarded as a print head, the print head of the present invention includes an exposure unit that exposes the photosensitive member, and an optical unit that forms an image of light emitted from the exposure unit on the photosensitive member. Is provided corresponding to a plurality of light emitting elements, a power source for supplying power, and a plurality of light emitting elements, and has an input terminal for inputting power from the power source, an output terminal for outputting input power, and input power. A plurality of switch elements that have a control terminal for inputting a control signal for output from the output terminal, hold the ON state by inputting the control signal to the control terminal, and turn on the light emitting elements each; The drive signal generator generates a drive signal during a period when the switch element is turned on when the drive signal generator generates a drive signal for sequentially turning on the switch element and outputs the drive signal to the output terminal of the switch element. The level shift unit changes the voltage of the level shift voltage output from the level shift unit to a level shift voltage that is lower or higher than the power supply voltage. It is characterized by changing depending on the part.
[0025]
Here, the level shift unit has one end connected to the output end of the switch element, and the other end branched in parallel to the signal line to which the capacitor is connected and the signal line to which the resistor is connected, and is connected to the drive signal generation unit It can be characterized by that. The plurality of light emitting elements and the plurality of switch elements may be divided into a plurality of sets, and each of the plurality of sets may include a drive signal generation unit and a level shift unit. In particular, the level shift voltage changing unit can be provided for each of a plurality of sets.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on embodiments shown in the accompanying drawings. FIG. 1 is a diagram for explaining a light emitting element array driving apparatus according to the present embodiment. In FIG. 1, the light emitting element array driving device 50 includes a plurality of SLEDs 40 as a light emitting element array and a driving unit 41 for driving each SLED 40. The light emitting element array driving device 50 according to the present embodiment is mounted on an LED print head (LPH) and drives each LED.
As shown in FIG. 1, the SLED 40 includes n thyristors S1 to Sn, n light emitting diodes (LEDs) L1 to Ln, n + 1 diodes CR0 to CRn, n resistors R1 to Rn, and a signal line. The transfer current limiting resistors R1A and R2A are configured to prevent an excessive current from flowing through. The drive unit 41 includes resistors RS, R1B, R2B, RID1, RID2, capacitors C1, C2, and a signal generation circuit 42 as an example of drive signal generation means. In addition, although many SLED40 is connected to the drive part 41, in FIG. 1, the structure by which two SLED40 was connected to the drive part 41 as a part is shown.
[0027]
Below, the circuit structure of SLED40 and the drive part 41 is demonstrated. First, anode terminals (input terminals) A <b> 1 to An of the thyristors S <b> 1 to Sn are connected to the power supply line 12. A power supply voltage VDD (VDD = 3.3 V) is supplied to the power supply line 12.
The cathode terminals (output terminals) K1, K3,... Of the odd-numbered thyristors S1, S3,... Are connected to the signal generating circuit 42 via the transfer current limiting resistor R1A. A level shift circuit 43 as an example of level shift means configured by branching in parallel a signal line to which the resistor R1B is connected and a signal line to which the capacitor C1 is connected.
Furthermore, the cathode terminals (output terminals) K2, K4,... Of the even-numbered thyristors are connected to the signal generating circuit 42 via the transfer current limiting resistor R2A, but between the resistor R2A and the signal generating circuit 42, A level shift circuit 44 as an example of level shift means configured by branching in parallel a signal line connected to the resistor R2B and a signal line connected to the capacitor C2 is disposed.
[0028]
On the other hand, the gate terminals (control terminals) G1 to Gn of the thyristors S1 to Sn are respectively connected to the power supply line 16 via resistors R1 to Rn provided corresponding to the thyristors. The power supply line 16 is grounded (GND).
The gate terminals G1 to Gn of the thyristors S1 to Sn are connected to the gate terminals of the light emitting diodes L1 to Ln provided corresponding to the thyristors S1 to Sn, respectively.
Furthermore, the anode terminals of the diodes CR1 to CRn are connected to the gate terminals G1 to Gn of the thyristors S1 to Sn. The cathode terminals of the diodes CR1 to CRn are each connected to the gate terminal of the next stage thyristor. That is, the diodes CR1 to CRn are connected in series.
[0029]
The anode terminal of the diode CR1 is connected to the cathode terminal of the diode CR0, and the anode terminal of the diode CR0 is connected to the signal generating circuit 42 via the resistor RS. The cathode terminals of the light emitting diodes L1 to Ln are connected to the signal generation circuit 42 via the resistor RID1. The light emitting diodes L1 to Ln are made of AlGaAsP or GaAsP as an example, and the band gap is about 1.5V.
[0030]
Next, the operation of the light emitting element array driving apparatus 50 of the present embodiment will be described with reference to the timing chart shown in FIG. In the following, a case where there are four thyristors (n = 4) will be described as an example.
(1) In the initial state, no current flows through all the thyristors S1, S2, S3, and S4, so that they are off ((1) in FIG. 2).
(2) When the transfer signal CK1R is set to a low level (“L”) from the initial state (2 in FIG. 2), a current flows in the direction of the arrow in the level shift circuit 43 as shown in FIG. The potential of the transfer signal CK1 becomes GND. Since the potential of the transfer signal CK1C is 3.3V, the potential across the capacitor C1 is 3.3V (VDD). In this case, the transfer signal CKS may be set to the high level (“H”) as indicated by the dotted line portion in FIG.
[0031]
(3) At the same time, when the transfer signal CKS is set to “H” and the transfer signal CK1C is set to “L” ((3) in FIG. 2), the charge of the transfer signal CK1 is accumulated in the capacitor C1. It becomes about -3.3V. The potential of the transfer signal CK1 at this time is called a level shift voltage. The gate G1 potential is ΦS potential −Vf = about 1.8V. Here, ΦS potential = about 3.3V, and Vf means a diode forward voltage of AlGaAs, which is about 1.5V. Further, Φ1 potential = G1 potential−Vf = about 0.3V. For this reason, a potential difference of about 3.7 V is generated between the signal line Φ1 and the transfer signal CK1.
[0032]
In the state where the level shift voltage is generated, as shown in FIG. 4, the gate current of the thyristor S1 starts to flow through the route of the gate G1 → the signal line Φ1 → the transfer signal CK1. At this time, the tri-state buffer B1R of the signal generation circuit 42 is set to high impedance (Hi-Z) to prevent current backflow.
Thereafter, Tr2 is turned on by the gate current of thyristor S1, whereby the base current of Tr1 (Tr2 collector current) flows, and thyristor S1 starts to turn on in the order that Tr1 is turned on, and the gate current gradually increases. . At the same time, the current flows into the capacitor C1 of the level shift circuit 43, so that the potential of the transfer signal CK1 gradually increases.
[0033]
(4) After a lapse of a predetermined time (time when the transfer signal CK1 potential becomes close to GND), the tristate buffer B1R of the signal generation circuit 42 is set to “L” ((4) in FIG. 2). As the gate G1 potential rises, the signal line Φ1 potential rises and the transfer signal CK1 potential rises, and accordingly, a current starts to flow to the resistor R1B side of the level shift circuit 43. On the other hand, as the potential of the transfer signal CK1 increases, the current flowing into the capacitor C1 of the level shift circuit 43 gradually decreases.
When the thyristor S1 is completely turned on and is in a steady state, the potential at each point is as shown in FIG. That is, a current for maintaining the on state of the thyristor S1 flows through the resistor R1B of the level shift circuit 43, but does not flow through the capacitor C1. At this time, the potential of the transfer signal CK1 is CK1 potential≈1.8−1.8 × R1B / (R1A + R1B).
[0034]
(5) With the thyristor S1 fully turned on, the lighting signal ID 1 is set to “L” ((5) in FIG. 2). At this time, since the gate G1 potential> the gate G2 potential (gate G1 potential−gate G2 potential≈1.8 V), the LED L1 having the thyristor structure is turned on earlier and is lit. As the LED L1 is turned on, the potential of the signal line Φ1 rises, and the signal line Φ1 potential = the gate G2 potential≈1.8 V, so that the LEDs after the LED L2 are not turned on. That is, for L1, L2, L3, L4,..., Only the LED having the highest gate voltage is turned on (lit).
[0035]
(6) Next, when the transfer signal CK2R is set to “L” (FIG. 2 (6)), a current flows as in FIG. 2 (2), and a voltage is generated across the capacitor C2 of the level shift circuit 44. To do. In the steady state just before the end of FIG. 2 (6), since the gate G2 potential is about 1.8V, the voltage value at each point is slightly different from that in FIG. 2 (2), but there is no effect on the operation. This is because the signal line Φ2 potential = gate G2 potential−Vf≈1.8V−1.5V≈0.3V in the steady state just before the end of FIG. 2 (6), as shown in FIG. This is because a gate current flows through the thyristor S2 in the direction of the dotted line, but this is so small that the thyristor S2 is not turned on. In this case, the potential of the transfer signal CK2 is about CK2 potential≈0.3−0.3 × R2B / (R2A + R2B) ≈0.15.
[0036]
(7) When the transfer signal CK2C is set to “L” in this state ((7) in FIG. 2), the thyristor switch S2 is turned on.
(8) When the transfer signals CK1C and CK1R are simultaneously set to “H” ((8) in FIG. 2), the thyristor switch S1 is turned off and discharged through the resistor R1, thereby gradually lowering the potential of the gate G1. At that time, the gate G2 of the thyristor switch S2 becomes ≈3.3V and is completely turned on. Accordingly, by turning the lighting signal ID terminal corresponding to the image data “L” / “H”, the LED L2 can be turned on / off. In this case, since the potential of the gate G1 is already lower than the potential of the gate G2, the LED L1 is not turned on.
[0037]
As described above, in the light emitting element array driving apparatus 50 according to the present embodiment, the on-states of the thyristor switches S1, S2, S3, and S4 can be changed by alternately generating the transfer signals CK1 and CK2. Therefore, it becomes possible to selectively control lighting / non-lighting of the LEDs L1, L2, L3, and L4 in a time division manner. In particular, by driving the SLED 40 through the level shift circuits 43 and 44, 3.3V can be used as a drive power source.
[0038]
By the way, in the light emitting element array driving apparatus 50 of the present embodiment, as described in FIGS. 2 (3) and (7), the level shift circuit 43 and the level shift circuit 44 level shift to the transfer signal CK1 and the transfer signal CK2. Although a voltage is generated, the voltage value of this level shift voltage (level shift voltage value) can be changed.
The transfer current limiting resistors R1A and R2A built in the SLED chip have large variations in resistance values for each lot of the SLED chips. For example, even if the design value is set to 1 kΩ, it varies from 600Ω to 2400Ω. There is a difference of about 4 times. For this reason, when the drive unit 41 is designed on the assumption that the resistance values of the transfer current limiting resistors R1A and R2A are the maximum values (for example, 2400Ω), the level shift voltage value is increased in order to stably operate the SLED 40. Must be set. However, when the resistance values of the transfer current limiting resistors R1A and R2A are the minimum value (for example, 600Ω) in such a setting, the transfer current flowing through the signal line Φ1 and the signal line Φ2 becomes excessive, and the load of the drive unit 41 is increased. It becomes excessive and power consumption becomes large.
Therefore, in the light emitting element array driving apparatus 50 according to the present embodiment, the SLED 40 is stably operated at a low voltage and driven by changing the level shift voltage value according to the resistance values of the transfer current limiting resistors R1A and R2A. It is possible to suppress overload on the unit 41 and to realize low power consumption.
[0039]
Here, FIG. 7 shows a configuration of the signal generation circuit 42 that can set a level shift voltage value necessary for stably operating the SLED 40 in accordance with the resistance values of the transfer current limiting resistors R1A and R2A. It is a block diagram. As shown in FIG. 7, the signal generation circuit 42 receives the horizontal synchronization signal (LSYNC) and the clock (Mclk) from the image forming apparatus equipped with the LED print head (LPH), and transfers the transfer signals CKS, CK1C, CK2C. Or a signal generator 421 for generating a signal to be driven with a fixed value such as a reference clock Tref for determining the driving cycle of the SLED 40, a capacitor C1 provided in the level shift circuits 43 and 44 for setting the level shift voltage value, The TWR setting register 423 storing the charging period setting time TWR for setting the charging period of C2 (see FIG. 1), the charging period setting time TWR from the TWR setting register 423, and the reference clock Tref from the signal generator 421 are received. CKR signal generator 422 for generating a transfer signal, CKR signal generator A logic circuit 425 for generating a transfer signal CK1R based on a transfer signal from the unit 422 and a transfer signal CK1C from the signal generator 421; a transfer signal from the CKR signal generator 422; and a transfer signal CK2C from the signal generator 421; Is provided with a logic circuit 426 that generates a transfer signal CK2R.
[0040]
A process in which the level shift voltage value is set in the signal generation circuit 42 configured as described above will be described. FIG. 8 is a timing chart regarding signals generated by the signal generation circuit 42. As shown in FIG. 7, the CKR signal generation unit 422 receives the reference clock Tref output from the signal generation unit 421 and the charge period setting time TWR stored in the TWR setting register 423. Then, as shown in FIG. 8, the CKR signal generation unit 422 causes the logic circuit 425 to change the transfer signal CK1R from the high level (“H”) to the low level after the charge period setting time TWR from the rising edge Ta1 at which the reference clock Tref rises. The transfer signal is output to the logic circuit 425 so that the level is changed to “L”.
[0041]
The period from the falling edge Tb1 at which the transfer signal CK1R falls from “H” to “L” to the falling edge Tc1 at which the transfer signal CK1C falls from “H” to “L” is the same as in FIG. As described above, the period in which charges are accumulated in the capacitor C1 of the level shift circuit 43, and the level shift voltage value is determined by the amount of charges accumulated in the capacitor C1. Therefore, if the charge period setting time TWR is set longer, the period in which the charge is accumulated in the capacitor C1 is shortened, and as a result, the amount of accumulated charge is reduced. Therefore, the level of the transfer signal CK1 output from the level shift circuit 43 is reduced. The shift voltage value becomes smaller. On the other hand, if the charge period setting time TWR is set short, the period in which the charge is accumulated in the capacitor C1 is lengthened, and as a result, the amount of charge accumulated is increased, so the transfer signal CK1 output from the level shift circuit 43 is increased. The level shift voltage value of increases. Thus, by adjusting the charge period setting time TWR to be set, the level shift voltage value of the transfer signal CK1 output from the level shift circuit 43 can be changed.
The charge period setting time TWR is set based on the clock Mclk, and the length of the charge period setting time TWR is set by determining the number of clocks to be counted.
[0042]
Similarly, after the charge period setting time TWR from the falling edge Ta2 at which the reference clock Tref falls, the CKR signal generator 422 changes the transfer signal CK2R from “H” to “L” and outputs it. As described above, the transfer signal is output to the logic circuit 426. Thus, the amount of charge accumulated in the capacitor C2 of the level shift circuit 44 is adjusted between the falling edge Tb2 of the transfer signal CK2R and the falling edge Tc2 of the transfer signal CK2C, and is output from the level shift circuit 44. The level shift voltage value of the transfer signal CK2 can be changed.
Therefore, the level shift voltage values of the transfer signal CK1 and the transfer signal CK2 can be changed in the level shift circuit 43 and the level shift circuit 44 by changing the charge period setting time TWR according to the transfer current limiting resistors R1A and R2A. .
Here, the signal generation circuit 42 functions as level shift voltage changing means.
[0043]
By the way, the charge period setting time TWR is set in the EEPROM 424 by the serial communication using serial data (SDI) and serial clock (SCK), for example, and the TWR setting register 423 from the EEPROM 424 is set. Can be stored in the TWR setting register 423.
[0044]
Specifically, the charge period setting time TWR is determined by gradually reducing the charge period setting time TWR while driving the SLED 40 by generating various transfer signals and lighting signals ID from the drive unit 41. The period during which charges are accumulated in the capacitors C1 and C2 of the shift circuits 43 and 44 is gradually lengthened. Then, a charging period setting time TWR that is slightly smaller than the charging period setting time TWR when all the LEDs arranged in the SLED 40 connected to the drive unit 41 are turned on is set. The set charge period setting time TWR is written in the EEPROM 424 and further stored in the TWR setting register 423 by downloading from the EEPROM 424 to the TWR setting register 423. The reason why the setting is set to be slightly smaller than the charge period setting time TWR when all the LEDs are lit is to make a setting with allowance in consideration of fluctuations in the transfer current limiting resistors R1A and R2A.
[0045]
In addition, as a method for determining the charge period setting time TWR, the charge period setting time TWR is gradually reduced to gradually increase the period in which charges are accumulated in the capacitors C1 and C2 of the level shift circuits 43 and 44. In addition, the current flowing from the power supply through the power supply line 12 is monitored. A method of setting a slightly shorter charge period setting time TWR from the charge period setting time TWR when the current value saturates and stops changing can also be used. This is determined by the charge period setting time TWR when the level shift voltage value is gradually increased and all thyristors are turned on.
Furthermore, the transfer signals CK1 and CK2 can be directly detected to determine the charge period setting time TWR.
[0046]
The charge period setting time TWR can also be configured to be set directly in the CKR signal generator 422. That is, for example, a memory is installed in the CKR signal generator 422, and a plurality of charge period setting times TWR are stored in advance in this memory. The CKR signal generation unit 422 is provided with a plurality of dip switches, a code is designated by a combination of ON / OFF of each dip switch, and the charge period setting time TWR stored in the CKR signal generation unit 422 by the designated code is set. It can also be configured to specify.
[0047]
Next, the signal states when the level shift voltage values of the transfer signal CK1 and the transfer signal CK2 are changed in the drive unit 41 are compared. 9 shows a timing chart of signals generated from the drive unit 41 when the resistance values of the transfer current limiting resistors R1A and R2A are large, and FIG. 10 shows a drive unit when the resistance values of the transfer current limiting resistors R1A and R2A are small. The timing chart of the signal generated from 41 is shown.
As shown in FIG. 9, when the resistance values of the transfer current limiting resistors R1A and R2A are large, the transfer signal CK1R is set to “L” (the transfer signal CK1C is “H”) during the period (2) in FIG. As described above, the capacitor C1 is sufficiently charged by setting the period for charging the capacitor C1 of the level shift circuit 43 to be long. Therefore, in FIG. 9 (3) in which the transfer signal CK1C falls to “L”, the level shift voltage of the transfer signal CK1 can be set large.
In FIG. 9 (6), the same applies when the capacitor C2 of the level shift circuit 44 is charged, and the level shift voltage of the transfer signal CK2 can be set large.
[0048]
On the other hand, as shown in FIG. 10, when the resistance values of the transfer current limiting resistors R1A and R2A are small, the transfer signal CK1R is set to “L” (the transfer signal CK1C is set to “H” during the period (2) in FIG. )), The capacitor C1 is not sufficiently charged by setting the period for charging the capacitor C1 of the level shift circuit 43 to be short. Therefore, in FIG. 10 (3) in which the transfer signal CK1C falls to “L”, the level shift voltage of the transfer signal CK1 can be set small.
In FIG. 10 (6), the same applies to the case where the capacitor C2 of the level shift circuit 44 is charged, and the level shift voltage of the transfer signal CK2 can be set small.
[0049]
Next, a circuit when the light emitting element array driving apparatus 50 according to the present embodiment is mounted on the LPH will be described. FIG. 11 is a circuit diagram in which the light emitting element array driving device 50 is mounted on the LPH. FIG. 11 shows a configuration in which recording is performed at 600 dpi (dot per inch) on an A3 size recording sheet, and a 7424 dot LED element is driven. That is, the LPH of the present embodiment has 58 chips of SLEDs 40 incorporating 128 LEDs.
In FIG. 11, six drive units 41 are arranged in the LPH drive signal generation unit. Transfer signals CK1, CK2, and CKS output from one driver 41 drive 9 to 10 chips of SLEDs 40 per one. Further, one LED lighting signal ID (ΦI) is output per chip of the SLED 40, and 58 lighting signals (ΦI1 to ΦI58) are output in total from the six driving units 41. Level shift circuits 43 and 44 are arranged for each drive unit 41. At that time, the charge period setting time TWR is set to each of the six sets of driving units 41 through the serial communication line, and the level shift voltage value is adjusted.
With this configuration, all LED chips can be stably driven at a low voltage while reducing the number of signal lines of the transfer signals CK1, CK2, and CKS, and the load on the drive unit 41 becomes excessive. In addition to suppressing this, it is possible to realize low power consumption.
[0050]
Next, an LPH equipped with the light emitting element array driving apparatus 50 according to the present embodiment will be described. FIG. 12 is a cross-sectional view illustrating the configuration of an LPH on which the light emitting element array driving device 50 is mounted. In FIG. 12, an LPH 60 binds the light from the housing 61 as a support, the printed circuit board 62 on which the light emitting element array driving device 50 is mounted, the LED array 63 that irradiates exposure light, and the LED array 63 to the surface of the photosensitive drum 1. A SELFOC lens array (SLA) 64 to be imaged, an SLA holder 65 that supports the SLA 64 and shields the LED array 63 from the outside, and a leaf spring 66 that urges the housing 61 in the SLA 64 direction are provided.
[0051]
The housing 61 is formed of a block or sheet metal such as aluminum or SUS, and supports the printed circuit board 62 and the LED array 63. The SLA holder 65 supports the housing 61 and the SLA 64, and is configured so that the light emitting point of the LED array 63 and the focal point of the SLA 64 coincide. Further, the SLA holder 65 is disposed so as to seal the LED array 63. Therefore, dust does not adhere to the LED array 63 from the outside. On the other hand, the leaf spring 66 is biased in the SLA 64 direction via the housing 61 so as to maintain the positional relationship between the LED array 63 and the SLA 64.
The LPH 60 configured as described above is configured to be movable in the optical axis direction of the SLA 64 by an adjustment screw (not shown), and adjusted so that the image formation position (focal point) of the SLA 64 is positioned on the surface of the photosensitive drum 1. Is done.
[0052]
In the LED array 63, a plurality of LED chips are arranged on the chip substrate in a line with high accuracy parallel to the axial direction of the photosensitive drum 1. Similarly, in the SLA 64, self-focusing rod lenses are arranged in a line with high precision parallel to the axial direction of the photosensitive drum 1. Then, the light from the LED array 63 controlled by the light emitting element array driving device 50 forms an image on the surface of the photosensitive drum 1 to form an electrostatic latent image.
[0053]
In such an LPH 60, if the light emitting element array driving apparatus 50 according to the present embodiment is applied, 3.3 V can be used as the I / O power supply voltage, so that the design with a fine design rule such as 0.25 μm is possible. Is possible. Therefore, the chip area can be reduced and the number of driver ICs can be reduced. As a result, in the LPH 60, the light emitting element array driving device 50 can be mounted on the printed circuit board 62, and the width area of the printed circuit board 62 in the circumferential direction of the photosensitive drum 1 can be designed to be small. Miniaturization can be realized. In addition, since the level shift circuits 43 and 44 can be configured only with capacitors and resistors, there is an advantage that they can be manufactured at low cost.
In addition, since driving with 3.3V is possible, the power consumption in the LPH 60 can be reduced, so that the heat generated in the LED substrate due to the power consumed in the LPH 60 can be reduced to suppress the occurrence of thermal expansion in the LED array. Can do. For this reason, it is possible to suppress the occurrence of image shift (color shift) between the Y, M, C, and K color images.
[0054]
In particular, in the light emitting element array driving apparatus 50 according to the present embodiment, a level shift voltage value necessary for stably operating the SLED 40 can be set according to the resistance values of the transfer current limiting resistors R1A and R2A. . For this reason, even if the resistance values of the transfer current limiting resistors R1A and R2A vary among lots of SLED chips, it is possible to suppress the transfer current from becoming too large while stably driving the SLED 40. It is possible to suppress excessive power consumption and to further reduce power consumption.
[0055]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a light emitting element array driving apparatus capable of sequentially turning on light emitting elements at high speed and stably even with low voltage driving.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a configuration of a light emitting element array driving device.
FIG. 2 is a timing chart relating to signals generated from the light emitting element array driving apparatus;
FIG. 3 is a diagram for explaining a current flow of a level shift circuit when a transfer signal CK1R is set to “L” from an initial state;
FIG. 4 is a diagram illustrating a current flow immediately after a transfer signal CKS is set to “H” and CK1C is set to “L”.
FIG. 5 is a diagram for explaining the potential of each part in a steady state in which the thyristor S1 is completely turned on.
FIG. 6 is a diagram illustrating a state in which a gate current flows through thyristor S2.
FIG. 7 is a block diagram showing a configuration of a signal generation circuit.
FIG. 8 is a timing chart regarding signals generated by a signal generation circuit.
FIG. 9 is a timing chart of signals generated from the drive unit when the resistance values of the transfer current limiting resistors R1A and R2A are large.
FIG. 10 is a timing chart of signals generated from a drive unit when resistance values of transfer current limiting resistors R1A and R2A are small.
FIG. 11 is a circuit diagram in which a light emitting element array driving device is mounted on an LPH.
FIG. 12 is a cross-sectional view illustrating a configuration of an LPH equipped with a light emitting element array driving device.
FIG. 13 is a diagram illustrating a configuration of a color image forming apparatus.
FIG. 14 is a circuit diagram illustrating a conventional light emitting element array driving apparatus.
FIG. 15 is a timing chart regarding signals generated from a conventional light emitting element array driving apparatus;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 12,16 ... Power supply line, 40 ... SLED, 41 ... Drive part, 42 ... Signal generation circuit, 43, 44 ... Level shift circuit, 50 ... Light emitting element array drive device, 60 ... LPH, 61 ... Housing, 62 ... Printed circuit board 63 ... LED array, 64 ... SLA, 65 ... SLA holder, 66 ... leaf spring, S1, S2, S3, S4 ... thyristor, A1, A2, A3, A4 ... anode terminal (input end), K1, K2, K3 , K4 ... Cathode terminal (output terminal), G1, G2, G3, G4 ... Gate terminal (control terminal), CR0, CR1, CR2, CR3, CR4 ... Diode, L1, L2, L3, L4 ... Light emitting diode (LED) RS, R1B, R2B, RID1, RID2, R1, R2, R3, R4 ... resistor, R1A, R2A ... transfer current limiting resistor, C1, C2 ... capacitor, 421 ... signal generator, 422 ... CKR signal generator Department, 423 ... TWR setting register, 424 ... EEPROM, 425,426 ... logic circuit

Claims (7)

A plurality of light emitting elements;
A power supply for supplying power;
Control that is provided corresponding to the plurality of light emitting elements, and that inputs an input terminal for inputting power from the power source, an output terminal for outputting input power, and a control signal for outputting the input power from the output terminal A plurality of thyristors that have an end, hold an on state when a control signal is input to the control end, and can selectively control lighting / non-lighting of the light emitting element by transitioning the on state ;
A power supply line connected to the input terminal of the thyristor for supplying a power supply voltage from the power supply;
Two signal lines that are alternately connected to the even-numbered and odd-numbered thyristors at the output terminal of the thyristor, and that alternately turn on the thyristor by generating a transfer signal;
The control terminals of the thyristors are respectively connected in series via diodes, and a start signal for starting the operation of the thyristor that is turned on first among the thyristors is sent, and a signal line for inputting the control signal to the control terminals,
A signal line connected to the light emitting element and for sending a lighting signal for controlling lighting of the light emitting element;
Signal generating means for generating the transfer signal, the start signal, and the lighting signal;
A transfer current limiting resistor arranged via a signal line for sending the transfer signal and the signal generating means;
Level shift means for changing the voltage of the transfer signal from the signal generating means during a period in which the thyristor is turned on;
A self-scanning light emitting element array driving device comprising: level shift voltage changing means for changing a voltage value of a level shift voltage output by the level shift means based on a resistance value of the transfer current limiting resistor. . The level shift means has one end connected to the output terminal of the thyristor , and the other end branched in parallel to a signal line connected to a capacitor and a signal line connected to a resistor and connected to the signal generating means . The self-scanning light-emitting element array driving apparatus according to claim 1. 3. The level shift voltage changing unit changes the voltage value of the level shift voltage by changing a charging time or a discharging time of the capacitor disposed in the level shifting unit. The self-scanning light emitting element array driving device described. Exposure means for exposing the photoreceptor;
Optical means for imaging light emitted from the exposure means on the photoconductor,
The exposure means includes
A plurality of light emitting elements;
A power supply for supplying power;
Control that is provided corresponding to the plurality of light emitting elements, and that inputs an input terminal for inputting power from the power source, an output terminal for outputting input power, and a control signal for outputting the input power from the output terminal A plurality of thyristors that have an end, hold an on state when a control signal is input to the control end, and can selectively control lighting / non-lighting of the light emitting element by transitioning the on state ;
A power supply line connected to the input terminal of the thyristor for supplying a power supply voltage from the power supply;
Two signal lines that are alternately connected to the even-numbered and odd-numbered thyristors at the output terminal of the thyristor, and that alternately turn on the thyristor by generating a transfer signal;
The control terminals of the thyristors are respectively connected in series via diodes, and a start signal for starting the operation of the thyristor that is turned on first among the thyristors is sent, and a signal line for inputting the control signal to the control terminals,
A signal line connected to the light emitting element and for sending a lighting signal for controlling lighting of the light emitting element;
A signal generator for generating the transfer signal, the start signal, and the lighting signal;
A transfer current limiting resistor arranged via a signal line for sending the transfer signal and the signal generator;
A level shift unit that changes a voltage of a transfer signal from the signal generation unit during a period in which the thyristor is turned on;
A print head comprising: a level shift voltage changing unit that changes a voltage value of a level shift voltage output by the level shift unit based on a resistance value of the transfer current limiting resistor . The level shift unit has one end connected to the output terminal of the thyristor and the other end branched in parallel to a signal line connected to a capacitor and a signal line connected to a resistor and connected to the signal generation unit . The print head according to claim 4 . Wherein the light-emitting element and the thyristor is configured by being divided into two groups, the two sets of print head according to claim 4, wherein the signal generating unit for each set, comprising the said level shift unit . The print head according to claim 4, wherein the level shift voltage changing unit is provided for each of the two sets .

Images