JP4298800B2 - キャッシュメモリにおけるプリフェッチ管理 - Google Patents

キャッシュメモリにおけるプリフェッチ管理 Download PDF

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Publication number
JP4298800B2
JP4298800B2 JP52577399A JP52577399A JP4298800B2 JP 4298800 B2 JP4298800 B2 JP 4298800B2 JP 52577399 A JP52577399 A JP 52577399A JP 52577399 A JP52577399 A JP 52577399A JP 4298800 B2 JP4298800 B2 JP 4298800B2
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Japan
Prior art keywords
prefetch
memory
address
cache
information
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JP52577399A
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Japanese (ja)
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JP2001507845A5 (US07122603-20061017-C00045.png
JP2001507845A (ja
Inventor
エイノ ヤコブス
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NXP BV
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NXP BV
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP52577399A 1997-10-31 1998-09-24 キャッシュメモリにおけるプリフェッチ管理 Expired - Fee Related JP4298800B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/961,963 US6134633A (en) 1997-10-31 1997-10-31 Prefetch management in cache memory
US08/961,963 1997-10-31
PCT/IB1998/001479 WO1999023564A1 (en) 1997-10-31 1998-09-24 Prefetch management in cache memory

Publications (3)

Publication Number Publication Date
JP2001507845A JP2001507845A (ja) 2001-06-12
JP2001507845A5 JP2001507845A5 (US07122603-20061017-C00045.png) 2006-02-02
JP4298800B2 true JP4298800B2 (ja) 2009-07-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP52577399A Expired - Fee Related JP4298800B2 (ja) 1997-10-31 1998-09-24 キャッシュメモリにおけるプリフェッチ管理

Country Status (6)

Country Link
US (1) US6134633A (US07122603-20061017-C00045.png)
EP (1) EP0950222B1 (US07122603-20061017-C00045.png)
JP (1) JP4298800B2 (US07122603-20061017-C00045.png)
KR (1) KR100593582B1 (US07122603-20061017-C00045.png)
DE (1) DE69841640D1 (US07122603-20061017-C00045.png)
WO (1) WO1999023564A1 (US07122603-20061017-C00045.png)

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JP3439350B2 (ja) * 1998-10-02 2003-08-25 Ｎｅｃエレクトロニクス株式会社 キャッシュ・メモリ制御方法及びキャッシュ・メモリ制御装置
US6314494B1 (en) * 1999-04-15 2001-11-06 Agilent Technologies, Inc. Dynamically size configurable data buffer for data cache and prefetch cache memory
US6651088B1 (en) * 1999-07-20 2003-11-18 Hewlett-Packard Development Company, L.P. Method for reducing coherent misses in shared-memory multiprocessors utilizing lock-binding prefetchs
JP3922844B2 (ja) * 1999-09-02 2007-05-30 富士通株式会社 キャッシュｔａｇ制御方法及びこの制御方法を用いた情報処理装置
JP2001125829A (ja) * 1999-10-28 2001-05-11 Internatl Business Mach Corp <Ibm> コントローラ装置、ディスクコントローラ、補助記憶装置、コンピュータ装置、および補助記憶装置の制御方法
JP4680340B2 (ja) * 1999-12-14 2011-05-11 独立行政法人科学技術振興機構 プロセッサ
US6643743B1 (en) * 2000-03-31 2003-11-04 Intel Corporation Stream-down prefetching cache
JP3842218B2 (ja) * 2001-01-30 2006-11-08 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 命令フェッチ制御ビットを有するコンピュータ命令
US6889242B1 (en) 2001-06-29 2005-05-03 Koninklijke Philips Electronics N.V. Rounding operations in computer processor
US6886091B1 (en) 2001-06-29 2005-04-26 Koninklijke Philips Electronics N.V. Replacing VLIW operation with equivalent operation requiring fewer issue slots
US6851010B1 (en) 2001-06-29 2005-02-01 Koninklijke Philips Electronics N.V. Cache management instructions
US6848030B2 (en) 2001-07-20 2005-01-25 Freescale Semiconductor, Inc. Method and apparatus for filling lines in a cache
CA2468793A1 (en) * 2001-12-21 2003-07-10 Universite Laval Plant pot and soil watering system
KR100546403B1 (ko) * 2004-02-19 2006-01-26 삼성전자주식회사 감소된 메모리 버스 점유 시간을 가지는 시리얼 플레쉬메모리 컨트롤러
JP4504134B2 (ja) * 2004-08-16 2010-07-14 富士通株式会社 システム制御装置、投機フェッチ方法および情報処理装置
US7587580B2 (en) 2005-02-03 2009-09-08 Qualcomm Corporated Power efficient instruction prefetch mechanism
US7840761B2 (en) * 2005-04-01 2010-11-23 Stmicroelectronics, Inc. Apparatus and method for supporting execution of prefetch threads
US7886112B2 (en) * 2006-05-24 2011-02-08 Sony Computer Entertainment Inc. Methods and apparatus for providing simultaneous software/hardware cache fill
US8510509B2 (en) * 2007-12-18 2013-08-13 International Business Machines Corporation Data transfer to memory over an input/output (I/O) interconnect
US7958314B2 (en) * 2007-12-18 2011-06-07 International Business Machines Corporation Target computer processor unit (CPU) determination during cache injection using input/output I/O) hub/chipset resources
US7925865B2 (en) * 2008-06-02 2011-04-12 Oracle America, Inc. Accuracy of correlation prefetching via block correlation and adaptive prefetch degree selection
US8244978B2 (en) 2010-02-17 2012-08-14 Advanced Micro Devices, Inc. IOMMU architected TLB support
US8904115B2 (en) * 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines
US9201796B2 (en) * 2012-09-27 2015-12-01 Apple Inc. System cache with speculative read engine
US9223705B2 (en) * 2013-04-01 2015-12-29 Advanced Micro Devices, Inc. Cache access arbitration for prefetch requests
US9218291B2 (en) 2013-07-25 2015-12-22 International Business Machines Corporation Implementing selective cache injection
JP6252348B2 (ja) * 2014-05-14 2017-12-27 富士通株式会社 演算処理装置および演算処理装置の制御方法
US10387320B2 (en) 2017-05-12 2019-08-20 Samsung Electronics Co., Ltd. Integrated confirmation queues

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4583165A (en) * 1982-06-30 1986-04-15 International Business Machines Corporation Apparatus and method for controlling storage access in a multilevel storage system
US5357618A (en) * 1991-04-15 1994-10-18 International Business Machines Corporation Cache prefetch and bypass using stride registers
JP2744882B2 (ja) * 1993-01-15 1998-04-28 インターナショナル・ビジネス・マシーンズ・コーポレイション キューにより命令の実行を制御する装置及び方法
TW228580B (en) * 1993-10-01 1994-08-21 Ibm Information processing system and method of operation
US5634025A (en) * 1993-12-09 1997-05-27 International Business Machines Corporation Method and system for efficiently fetching variable-width instructions in a data processing system having multiple prefetch units
US5649144A (en) * 1994-06-13 1997-07-15 Hewlett-Packard Co. Apparatus, systems and methods for improving data cache hit rates
JPH08263424A (ja) * 1995-03-20 1996-10-11 Fujitsu Ltd コンピュータ装置
US5778435A (en) * 1996-05-30 1998-07-07 Lucent Technologies, Inc. History-based prefetch cache including a time queue
US5835947A (en) * 1996-05-31 1998-11-10 Sun Microsystems, Inc. Central processing unit and method for improving instruction cache miss latencies using an instruction buffer which conditionally stores additional addresses
US5854911A (en) 1996-07-01 1998-12-29 Sun Microsystems, Inc. Data buffer prefetch apparatus and method
JP3554208B2 (ja) * 1998-10-29 2004-08-18 キヤノン株式会社 現像剤供給装置

Also Published As

Publication number Publication date
KR20000069797A (ko) 2000-11-25
EP0950222B1 (en) 2010-04-28
DE69841640D1 (US07122603-20061017-C00045.png) 2010-06-10
WO1999023564A1 (en) 1999-05-14
KR100593582B1 (ko) 2006-06-28
US6134633A (en) 2000-10-17
EP0950222A1 (en) 1999-10-20
JP2001507845A (ja) 2001-06-12

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