JP4298601B2 - Interposer and manufacturing method of interposer - Google Patents

Interposer and manufacturing method of interposer Download PDF

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JP4298601B2
JP4298601B2 JP2004199785A JP2004199785A JP4298601B2 JP 4298601 B2 JP4298601 B2 JP 4298601B2 JP 2004199785 A JP2004199785 A JP 2004199785A JP 2004199785 A JP2004199785 A JP 2004199785A JP 4298601 B2 JP4298601 B2 JP 4298601B2
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hole
plating
layer
interposer
seed layer
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JP2006024649A (en
JP2006024649A5 (en
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智久 星野
健一 加川
正巳 八壁
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Tokyo Electron Ltd
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Priority to KR1020077014093A priority patent/KR100786166B1/en
Priority to EP05765494A priority patent/EP1783832A4/en
Priority to CNB2005800009842A priority patent/CN100413058C/en
Priority to KR1020067004600A priority patent/KR100786156B1/en
Priority to PCT/JP2005/012424 priority patent/WO2006004127A1/en
Priority to US11/631,635 priority patent/US20080067073A1/en
Priority to CN 200810089719 priority patent/CN101256999B/en
Priority to TW094122867A priority patent/TW200614896A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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Description

この発明は、インターポーザおよびその製造方法に関し、特に、貫通孔内でボイド（隙間）が生じない、インターポーザおよびその製造方法に関する。 The present invention relates to an interposer and a method for manufacturing the interposer, and more particularly to an interposer and a method for manufacturing the interposer in which no void (gap) is generated in a through hole.

図４は、シリコン基板６０に導通孔を設けてインターポーザを製造する場合の、従来の問題点を説明するための、シリコン基板６０の断面図である。図４を参照して、従来は、シリコン基板６０にまず貫通孔７１を設ける。このとき、貫通孔７１は、まっすぐな円柱状とならずに、図に示すように、中央部が凸状に膨らんだ形状になる。   FIG. 4 is a cross-sectional view of the silicon substrate 60 for explaining a conventional problem when an interposer is manufactured by providing a conduction hole in the silicon substrate 60. Referring to FIG. 4, conventionally, first, a through hole 71 is provided in a silicon substrate 60. At this time, the through-hole 71 does not have a straight cylindrical shape, but has a shape in which the central portion swells convexly as shown in the figure.

この貫通孔７１に対して、基板の表面６１と裏面６２において、貫通孔７１の周囲にまずスパッタリングでシード層６３、６４を設け、次いで、シード層６３，６４をシードとして、電界メッキ等を用いて導電層６５，６６を形成する。   For this through-hole 71, on the front surface 61 and the back surface 62 of the substrate, first, seed layers 63 and 64 are provided around the through-hole 71 by sputtering, and then using the seed layers 63 and 64 as seeds, electroplating or the like is used. Thus, conductive layers 65 and 66 are formed.

従来のインターポーザは上記のように構成されていた。シリコン基板を用いて貫通孔を形成する場合は、貫通孔の中央部が凸状であり、表面または裏面から内部へ向かうほど、径が広がっているため、シード層を貫通孔の内部に設けようとしても、内部まで十分にシード層を形成できなかった。そのため、シード層からメッキ等により導電層を成長させても、導電層が十分に成長せず、貫通孔７１の内部に、導電層の存在しない、いわゆる「ボイド」７２が形成される、という問題があった。 Conventional interposers have been configured as described above. When a through-hole is formed using a silicon substrate, the center portion of the through-hole is convex, and the diameter increases from the front surface or the back surface toward the inside. Therefore, a seed layer should be provided inside the through-hole. However, the seed layer could not be sufficiently formed to the inside. Therefore, even when grown conductive layer by plating or the like from the seed layer, not conductive layer fully grown, the interior of the through hole 71, no conductive layer, the so-called "void" 72 is formed, a problem that was there.

この発明は、上記のような課題に鑑みてなされたもので、製造工程が簡単で、かつ貫通孔の内部にボイドが生じない、インターポーザおよびその製造方法を提供することを目的とする。 The present invention has been made in view of the above-described problems, and an object thereof is to provide an interposer and a method for manufacturing the interposer in which the manufacturing process is simple and no void is generated inside the through hole.

この発明にかかるインターポーザは、一方面と、一方面に対向する他方面とを有し、一方面から他方面に貫通する貫通孔を有する基板と、基板の一方面側の貫通孔の開口部に設けられたシード層と、シード層を覆って設けられたメッキ用電極層と、メッキ用電極層から、他方面側へ延び、貫通孔を埋めるように形成されたメッキ層とを含む。   The interposer according to the present invention includes a substrate having a first surface and a second surface facing the first surface, the through hole penetrating from the first surface to the second surface, and an opening of the through hole on the first surface side of the substrate. A seed layer provided, a plating electrode layer provided so as to cover the seed layer, and a plating layer formed so as to extend from the plating electrode layer to the other surface side and fill the through hole.

貫通孔は、中央部が膨らんだ形状であってもよい。また、シード層、メッキ用電極層およびメッキ層とは、同一の材質であってもよく、相互に異なる材質であってもよい。   The through hole may have a shape in which the central portion is swollen. Further, the seed layer, the plating electrode layer, and the plating layer may be made of the same material or different materials.

この発明の他の局面においては、インターポーザの製造方法は、一方面と、一方面に対向する他方面とを有する基板を準備するステップと、基板に貫通孔を形成するステップと、一方面側の貫通孔の開口部にシード層を形成するステップと、一方面側のシード層から、他方面側にメッキ層を形成して貫通孔を埋めるステップとを含む。   In another aspect of the present invention, a method for manufacturing an interposer includes: preparing a substrate having one side and the other side facing the one side; forming a through hole in the substrate; Forming a seed layer in the opening of the through hole; and forming a plating layer on the other surface side from the seed layer on the one surface side to fill the through hole.

好ましくは、一方面側のシード層から、他方面側にメッキ層を形成して貫通孔を埋めるステップは、一方面側の貫通孔を閉じてメッキ用電極層を形成するステップと、電極層を用いてメッキ層を形成するステップとを含む。   Preferably, the step of forming a plating layer on the other surface side from the seed layer on the one surface side and filling the through hole closes the through hole on the one surface side to form an electrode layer for plating, and Using to form a plating layer.

さらに好ましくは、貫通孔を形成するステップは、中央部が膨らんだ貫通孔を形成するステップを含む。
なお、シード層、メッキ用電極層およびメッキ層とは、同一の材質で形成してもよいし、相互に異なる材質で形成してもよい。 More preferably, the step of forming the through hole includes the step of forming a through hole having a bulged central portion.
Note that the seed layer, the plating electrode layer, and the plating layer may be formed of the same material or different materials.

この発明にかかるインターポーザは、貫通孔の一方面側の開口部に設けられたシード層と、シード層を覆って設けられたメッキ用電極層と、メッキ用電極層から、他方面側へ延び、メッキによって貫通孔を埋めるように形成されたメッキ層とを含むため、基板の一方面側のシード層から他方面側に向けて、メッキ層が確実に形成される。   The interposer according to the present invention extends from the seed layer provided in the opening on one side of the through hole, the plating electrode layer provided so as to cover the seed layer, and the plating electrode layer to the other side, And a plating layer formed so as to fill the through hole by plating, the plating layer is reliably formed from the seed layer on one side of the substrate toward the other side.

その結果、製造工程が簡単で、かつ貫通孔の内部にボイドが生じない、インターポーザが提供できる。 As a result, it is possible to provide an interposer in which the manufacturing process is simple and no void is generated inside the through hole.

この発明の他の局面においては、インターポーザの製造方法は、基板の一方面側の貫通孔の開口部にシード層を形成し、そのシード層から、基板の他方面側にメッキ層を形成して貫通孔を埋める。貫通孔の基板の一方面側から他方面側へ確実にメッキによる導電層が形成されるため、貫通孔の内部にボイドが生じない。 In another aspect of the present invention, an interposer manufacturing method includes: forming a seed layer in an opening of a through hole on one side of a substrate; and forming a plating layer on the other side of the substrate from the seed layer. Fill the through hole. Since the conductive layer by plating is reliably formed from one side of the substrate to the other side of the through hole, no void is generated inside the through hole.

その結果、製造工程が簡単で、かつ貫通孔の内部にボイドが生じない、インターポーザの製造方法が提供できる。 As a result, it is possible to provide a method for manufacturing an interposer in which the manufacturing process is simple and no void is generated inside the through hole.

以下、図面を参照して、この発明の一実施形態を図面を参照して説明する。図１は、この発明の一実施の形態に係るインターポーザの製造工程をステップごとに示す図である。図１を参照して、まず、表面１１および裏面１２を有するシリコンの基板１０を準備し、それに貫通孔１３を設ける（図１（Ａ））。このとき、貫通孔１３は、図に示すように、従来と同様に、中央部が凸状に膨らんで形成されてもよい。この状態で、まず、貫通孔１３の内部を含んで、基板１０に、図示のない、絶縁膜が形成される。この絶縁膜は、ＳｉＯ２、ＳｉＮ等の絶縁膜であってもよく、スパッタリング、ＣＶＤまたは酸化によって形成される。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an interposer manufacturing process according to an embodiment of the present invention step by step. Referring to FIG. 1, first, a silicon substrate 10 having a front surface 11 and a back surface 12 is prepared, and a through hole 13 is provided in the silicon substrate 10 (FIG. 1A). At this time, as shown in the figure, the through-hole 13 may be formed so that the central portion bulges in a convex shape as in the conventional case. In this state, first, an insulating film (not shown) is formed on the substrate 10 including the inside of the through hole 13. This insulating film may be an insulating film such as SiO 2 or SiN, and is formed by sputtering, CVD, or oxidation.

次いで、基板１０の裏面１２側の絶縁膜が形成された貫通孔１３の周囲に、まずバリア層としてＴｉをスパッタリング等で形成する（図示無し）。そして、このバリア層の上に、スパッタリング等でＣｕのシード層（メッキのための電流を流す電極の基となる層）１４を形成する（図１（Ｂ））。次いで、このＣｕのシード層１４を基に、裏面１２側から電界メッキを行なう。このメッキは、メッキの端面が接合して貫通孔１３の裏面１２側が閉じるまで行い、Ｃｕのメッキ層１５からなるメッキ用電極層を形成する（図１（Ｃ））。   Next, Ti is first formed as a barrier layer by sputtering or the like around the through-hole 13 in which the insulating film on the back surface 12 side of the substrate 10 is formed (not shown). Then, a Cu seed layer (a layer serving as a base of an electrode for supplying a current for plating) 14 is formed on the barrier layer by sputtering or the like (FIG. 1B). Next, electroplating is performed from the back surface 12 side based on the Cu seed layer 14. This plating is performed until the end faces of the plating are joined and the back surface 12 side of the through hole 13 is closed to form a plating electrode layer composed of a Cu plating layer 15 (FIG. 1C).

次に、このＣｕのメッキ用電極層１５を電極として、表面１１側へＣｕの電界メッキを行なう。すると、図１（Ｄ）において矢印で示す方向にＣｕのメッキが成長し、メッキ層１６が得られる（図１（Ｄ））。   Next, Cu electroplating is performed on the surface 11 side using the Cu plating electrode layer 15 as an electrode. Then, Cu plating grows in the direction indicated by the arrow in FIG. 1D, and the plating layer 16 is obtained (FIG. 1D).

このように、この実施の形態によれば、貫通孔１３の内部に凸状の孔が形成されていても、内部にボイドが生じることなく、貫通孔１３をＣｕの導電層とすることができる。 As described above, according to this embodiment, even if a convex hole is formed inside the through-hole 13, the through-hole 13 can be formed as a Cu conductive layer without causing voids inside. .

なお、上記実施の形態においては、Ｔｉをバリア層として用いたが、これは省略してもよい。   In the above embodiment, Ti is used as the barrier layer, but this may be omitted.

次に、他の実施の形態について説明する。図２は、この実施の形態における図１（Ｄ）に対応する図であり、基本的に同じ構造である。図２を参照して、この実施の形態においては、シリコン基板２０に貫通孔２３が設けられ、その貫通孔２３がシード層２４、メッキ用電極層２５およびメッキ層２６で埋められている。   Next, another embodiment will be described. FIG. 2 is a view corresponding to FIG. 1D in this embodiment, and basically has the same structure. Referring to FIG. 2, in this embodiment, a through hole 23 is provided in silicon substrate 20, and the through hole 23 is filled with seed layer 24, plating electrode layer 25 and plating layer 26.

先の実施の形態においては、シリコン基板にＣｕのシード層およびメッキ層を設けたが、この実施の形態においては、シード層２４と、メッキ用電極層２５およびメッキ層２６はＣｕに限らず、Ｎｉ、Ｃｒ、Ａｕ、Ａｇ等の電界メッキを行えるものであれば、任意の材料が選ばれる。また、シード層２４、メッキ用電極層２５およびメッキ層２６の材質を相互に変えてもよい。たとえば、シード層をＣｕとし、それをメッキ用電極層として、Ａｕのメッキを行ってもよい。   In the previous embodiment, the Cu seed layer and the plating layer were provided on the silicon substrate. However, in this embodiment, the seed layer 24, the plating electrode layer 25, and the plating layer 26 are not limited to Cu. Any material can be selected as long as it can perform electroplating such as Ni, Cr, Au, and Ag. The materials of the seed layer 24, the plating electrode layer 25, and the plating layer 26 may be mutually changed. For example, Au may be plated using the seed layer as Cu and using it as an electrode layer for plating.

次に、この発明のさらに他の実施の形態について説明する。図３は、この発明が適用される貫通孔の形状を示す図である。先の実施の形態においては、中央部が凸状に膨らんだ貫通孔にこの発明を適用したが、この発明は、基板３０に、円柱状の貫通孔３１（図３（Ａ））や、表面から裏面に向けて順に孔の径が小さくなる貫通孔３２にも適用可能である。   Next, still another embodiment of the present invention will be described. FIG. 3 is a diagram showing the shape of a through hole to which the present invention is applied. In the previous embodiment, the present invention is applied to the through hole whose central portion bulges in a convex shape. However, the present invention provides the substrate 30 with a cylindrical through hole 31 (FIG. 3 (A)) and a surface. It is applicable also to the through-hole 32 in which the diameter of a hole becomes small in order toward a back surface.

上記実施の形態においては、基板としてシリコン基板を用いた例について説明したが、これに限らず、ガラス基板やサファイヤ基板のような絶縁基板を用いてもよい。この場合は、上記した絶縁膜の形成は不要になる。   In the above embodiment, an example in which a silicon substrate is used as a substrate has been described. However, the present invention is not limited to this, and an insulating substrate such as a glass substrate or a sapphire substrate may be used. In this case, it is not necessary to form the insulating film.

上記実施の形態においては、貫通孔への導電性材料の埋め込みを電界メッキを用いて行なう場合について説明したが、これに限らず、無電解メッキで埋め込んでもよい。   In the above-described embodiment, the case where the conductive material is embedded in the through hole using electroplating has been described. However, the present invention is not limited to this, and the conductive material may be embedded by electroless plating.

以上、図面を参照してこの発明の実施形態を説明したが、この発明は、図示した実施形態のものに限定されない。図示された実施形態に対して、この発明と同一の範囲内において、あるいは均等の範囲内において、種々の修正や変形を加えることが可能である。   As mentioned above, although embodiment of this invention was described with reference to drawings, this invention is not limited to the thing of embodiment shown in figure. Various modifications and variations can be made to the illustrated embodiment within the same range or equivalent range as the present invention.

この発明に係るインターポーザの製造方法は、通孔の基板の一方面側から他方面側へ確実にメッキによる導電層が形成されるため、貫通孔の内部にボイドが生じないインターポーザの製造方法として有利に利用されうる。 The method for manufacturing an interposer according to the present invention is advantageous as a method for manufacturing an interposer in which voids are not generated inside through-holes because a conductive layer is reliably formed by plating from one side of the through-hole substrate to the other side. Can be used.

インターポーザの製造方法をステップごとに示す図である。It is a figure which shows the manufacturing method of an interposer for every step. 他の実施の形態にかかるインターポーザの製造方法を示す図である。It is a figure which shows the manufacturing method of the interposer concerning other embodiment. この発明が適用される貫通孔の形状を示す図である。It is a figure which shows the shape of the through-hole to which this invention is applied. 従来のインターポーザの問題点を示す図である。It is a figure which shows the problem of the conventional interposer.

符号の説明Explanation of symbols

１０、２０ 基板、１１、２１ 表面、１３、２３ 裏面、１３、２３ 貫通孔、１４、２４ シード層、１５、２５ メッキ用電極層、１６、２６ メッキ層。

10, 20 Substrate, 11, 21 Front surface, 13, 23 Back surface, 13, 23 Through hole, 14, 24 Seed layer, 15, 25 Plating electrode layer, 16, 26 Plating layer.

Claims (11)

一方面と、前記一方面に対向する他方面とを有し、前記一方面から他方面に貫通する貫通孔を有する基板と、
前記基板の前記一方面側の貫通孔の開口部にスパッタリングにより形成されたシード層と、
前記シード層を覆って前記開口部が閉じるように電解メッキにより形成されたメッキ用電極層と、
前記メッキ用電極層から、前記他方面側へ延び、前記貫通孔を埋めるように形成されたメッキ層とを含む、インターポーザ。 A substrate having one side and the other side facing the one side, and having a through-hole penetrating from the one side to the other side;
A seed layer formed by sputtering in the opening of the through hole on the one surface side of the substrate;
An electrode layer for plating formed by electrolytic plating so as to cover the seed layer and close the opening,
An interposer including a plating layer formed so as to extend from the plating electrode layer to the other surface side and fill the through hole. 前記貫通孔は、中央部が膨らんだ形状である、請求項１に記載のインターポーザ。 The interposer according to claim 1, wherein the through hole has a shape in which a central portion is swollen. 前記シード層、前記メッキ用電極層および前記メッキ層とは、同一の材質である、請求項１または２に記載のインターポーザ。 The interposer according to claim 1 or 2, wherein the seed layer, the plating electrode layer, and the plating layer are made of the same material. 前記シード層、前記メッキ用電極層および前記メッキ層とは、相互に異なる材質である、請求項１または２に記載のインターポーザ。 The interposer according to claim 1 or 2, wherein the seed layer, the plating electrode layer, and the plating layer are made of mutually different materials. 一方面と、前記一方面に対向する他方面とを有する基板を準備するステップと、
前記基板に貫通孔を形成するステップと、
前記一方面側の貫通孔の開口部にスパッタリングによりシード層を形成するステップと、
前記一方面側のシード層を覆って前記開口部が閉じるように電解メッキにより前記他方面側にメッキ層を形成して貫通孔を埋めるステップとを含む、インターポーザの製造方法。 Providing a substrate having one side and the other side opposite the one side;
Forming a through hole in the substrate;
Forming a seed layer by sputtering at the opening of the through hole on the one surface side;
Forming a plating layer on the other surface side by electrolytic plating so as to cover the seed layer on the one surface side and closing the opening, and filling the through hole. 前記一方面側のシード層から、前記他方面側にメッキ層を形成して貫通孔を埋めるステップは、前記一方面側の貫通孔を閉じてメッキ用電極層を形成するステップと、前記電極層を用いてメッキ層を形成するステップとを含む、請求項５に記載のインターポーザの製造方法。 The step of forming a plating layer on the other surface side from the seed layer on the one surface side to fill the through hole includes the step of closing the through hole on the one surface side to form a plating electrode layer, and the electrode layer And forming a plating layer using the interposer according to claim 5. 前記貫通孔を形成するステップは、中央部が膨らんだ貫通孔を形成するステップを含む、請求項５または６に記載のインターポーザの製造方法。 The method of manufacturing an interposer according to claim 5 or 6, wherein the step of forming the through hole includes a step of forming a through hole having a bulged central portion. 前記シード層、前記メッキ用電極層および前記メッキ層とは、同一の材質である、請求項６に記載のインターポーザの製造方法。 The interposer manufacturing method according to claim 6, wherein the seed layer, the plating electrode layer, and the plating layer are made of the same material. 前記シード層、前記メッキ用電極層および前記メッキ層とは、相互に異なる材質である、請求項６に記載のインターポーザの製造方法。 The interposer manufacturing method according to claim 6, wherein the seed layer, the plating electrode layer, and the plating layer are made of mutually different materials. 前記貫通孔は、前記一方側の面において第１の開口面積を有し、前記一方側の面から他方側の面に向けて、順に前記第１の開口面積より小さい面積を有する、請求項１に記載のインターポーザ。   The through-hole has a first opening area on the one side surface, and an area smaller than the first opening area in order from the one side surface toward the other side surface. The interposer described in. 前記貫通孔は、前記基板の一方面から他方面に向かって順に開口面積が狭くなるようにエッチングを行なうことにより形成される、請求項５に記載のインターポーザの製造方
法。 The method of manufacturing an interposer according to claim 5, wherein the through hole is formed by performing etching so that an opening area is gradually reduced from one surface of the substrate toward the other surface.
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TW094122867A TW200614896A (en) 2004-07-06 2005-07-06 Interposer and interposer producing method
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