JP4298493B2 - Integrated circuit filter - Google Patents

Description

  The present invention relates to integrated circuit filters with associated bandwidth control functions.

  In recent years, the number of cases in which a filter is built in an integrated circuit has increased, and it is necessary to adjust or switch the characteristics of the filter depending on the application. For example, a band-limiting filter for band limitation in a receiver can be realized without changing the filter constant by changing the center frequency and bandwidth within the integrated circuit so that characteristics matching different specifications can be realized. The number of parts can be reduced. However, it is generally difficult to independently adjust the center frequency and bandwidth, which are important factors that determine the characteristics of the bandpass filter circuit. This problem will be described in detail below with reference to FIG.

  FIG. 10 is a block diagram showing a second-order band-pass filter circuit configured by using two transconductance amplifiers (hereinafter abbreviated as Gm amplifiers) in the prior art, and 4 is a first Gm amplifier. The transconductance value gm1 (hereinafter abbreviated as gm1) of the 1 Gm amplifier 4 is controlled by a control current I1. Reference numeral 6 denotes a second Gm amplifier, and a transconductance value gm2 (hereinafter abbreviated as gm2) of the second Gm amplifier 6 is controlled by a control current I2. 5 and 7 are buffer amplifiers having a gain of 1, 8 is a current source that outputs current I1, 9 is a current source that outputs current I2, C1 and C2 are capacitors, R1 and R2 are resistors, and VB is a reference voltage source. .

  The circuit configured as described above forms a secondary band-pass filter by an integration element formed by the capacitance of gm1 and the capacitor C1 and an integration element formed by the capacitance of gm2 and the capacitor C2.

Here, as shown in FIG. 8, a Gm amplifier having a transconductance value gm (hereinafter abbreviated as gm) has a relationship between an input voltage Vi and an output current Iout: gm = dIout / dVi
The gm can be changed by the control current Ib.

  FIG. 9 is a block diagram showing an example of the Gm amplifier circuit. The transistors Q501 and Q502 constitute a first differential amplifier, the resistor R501 is the emitter resistance of the first differential amplifier, and the transistors Q503 and Q504 are the first differential amplifier. The output load of the differential amplifier. Transistors Q505 and Q506 constitute a second differential amplifier, and transistors Q507 and Q508 constitute a current mirror. Ia is a current source, Ib is a current source, Vi is an input terminal of a Gm amplifier that receives a voltage difference, Iout is an output terminal that outputs a current, and ΔV is a voltage difference between outputs on both sides of the first differential amplifier. . Hereinafter, the input voltage from the input terminal Vi is also referred to as input Vi or simply Vi. Similarly, the output current from the output terminal Iout is also referred to as output Iout or simply Iout.

  In FIG. 9, the relationship between the input Vi and the output ΔV of the first differential amplifier can be approximately expressed by (Equation 1).

ここで、Ｖt＝ｋＴ／ｑで、ｋはボルツマン定数、Ｔは絶対温度、ｑは電子電荷である。

Here, Vt = kT / q, k is the Boltzmann constant, T is the absolute temperature, and q is the electronic charge.

  Next, in the second differential amplifier, when the output ΔV of the first differential amplifier is used as the input and the output Iout of the output terminal is used as the output, Equation (2) is established for ΔV and Iout.

このときのｇｍは（数１）と（数２）を用いて次の（数３）で表せる。

The gm at this time can be expressed by the following (Equation 3) using (Equation 1) and (Equation 2).

電流源に流れる電流Ｉaを固定とし、比例定数をＫ0とするとｇｍは（数４）で表せる。

If the current Ia flowing through the current source is fixed and the proportionality constant is K0, gm can be expressed by (Equation 4).

（数４）より、Ｉbを可変すればｇｍが調整できることがわかる。

(Equation 4) shows that gm can be adjusted by changing Ib.

  Next, the transfer function of the filter of FIG. 10 is given by (Equation 5).

ただし、Ｖinは入力端子ＩＮの電圧、Ｖoutは出力端子ＯＵＴの電圧、ｒ1は抵抗Ｒ1の抵抗値、ｒ2は抵抗Ｒ2の抵抗値、ｃ1はコンデンサＣ1の容量値、ｃ2はコンデンサＣ2の容量値である。

Where Vin is the voltage at the input terminal IN, Vout is the voltage at the output terminal OUT, r1 is the resistance value of the resistor R1, r2 is the resistance value of the resistor R2, c1 is the capacitance value of the capacitor C1, and c2 is the capacitance value of the capacitor C2. is there.

On the other hand, the general expression of the transfer function of the second-order bandpass filter is as shown in (Equation 6) :

と与えられる。ωoは角周波数であり、中心周波数をｆoとするとωo＝２πｆoで与えられる。Ｑは、図７で示すようにバンドパスフィルタ特性において、帯域幅Ｗを中心周波数ｆoの時のゲインに対してゲインが−３ｄＢとなる点の周波数の帯域幅としたときに、Ｑ＝ωo／Ｗで与えられる。

And given. ωo is the angular frequency, given the center frequency fo and Then ωo = 2πfo. As shown in FIG. 7, Q is Q = ωo / when the bandwidth W is the bandwidth at the point where the gain is -3 dB with respect to the gain at the center frequency fo in the bandpass filter characteristics. Given by W.

  From (Equation 5) and (Equation 6), in the case of the second-order bandpass filter shown in FIG. 10, ωo and Q are expressed by (Equation 7) and (Equation 8), respectively.

となる。ところで、（数４）で示したように、ｇｍ1，ｇｍ2は制御電流Ｉ1，Ｉ2に比例するので、比例定数をＫ1，Ｋ2とおくと（数９）と表される。

It becomes. By the way, as shown in (Equation 4), gm1 and gm2 are proportional to the control currents I1 and I2, and therefore when the proportionality constants are set to K1 and K2, they are expressed as (Equation 9).

この（数９）に示される関係を、（数７），（数８）に代入すると（数１０），（数１１）となり、

Substituting the relationship shown in (Equation 9) into (Equation 7) and (Equation 8) gives (Equation 10) and (Equation 11).

ここで、ωoとＱとを調整することを考えてみると、ωoの調整はＩ1もしくはＩ2を変化させれば可能であり、また、Ｑの調整もＩ1もしくはＩ2を変化させれば可能であることがわかる。

Here, considering that ωo and Q are adjusted, ωo can be adjusted by changing I1 or I2, and Q can be adjusted by changing I1 or I2. I understand that.

  However, if I1 or I2 is changed in order to adjust ωo, Q also changes simultaneously. If I1 or I2 is changed in order to adjust Q, ωo also changes simultaneously. Therefore, in order to adjust fo and Q of the bandpass filter, it is necessary to gradually adjust by repeating the operation of moving one of fo and Q and then moving the other. There is.

  In the conventional band-pass filter circuit, the adjustment of the center frequency and the adjustment of the bandwidth in the state where the center frequency is set cannot be performed independently. There wasn't.

  The present invention has been made in order to solve the problems of the prior art, and an integrated circuit filter having a band-pass filter circuit capable of adjusting only the bandwidth with the center frequency set. The purpose is to provide.

In order to solve this problem, the integrated circuit filter of the present invention includes a first gm amplifier whose gm is controlled by a control signal input to the first control terminal and a control signal input to the second control terminal. a filter circuit including a second gm amplifier gm is controlled by a first input terminal, a second input terminal, a first output terminal connected to said first control terminal, said first A control signal generation circuit having a second output terminal connected to the control terminal of the second control terminal , wherein the control signal generation circuit has a current input side connected to the first input terminal and a current output side connected to the first output terminal. The first current mirror circuit connected to the second control terminal, the first current mirror circuit and the emitters on the current input side and the current output side are commonly connected, and the current input side is connected to the constant voltage source Second current mirror A third current circuit having a current input side connected to the current output side of the second current mirror circuit, a current output side connected to the first control terminal, and an emitter connected to a constant voltage source or a ground terminal. A common connection point of the emitter on the current output side of the first current mirror circuit and the emitter on the current output side of the second current mirror circuit is connected to the second input terminal. It is a feature.

  According to the present invention, it is possible to adjust Q while keeping ωo constant by using gm control, and it is possible to adjust both ωo and Q of BPF by external input. A filter circuit can be realized.

  The integrated circuit filter of the present invention will be described below with reference to the drawings.

  FIG. 1 is a configuration diagram of an integrated circuit filter according to an embodiment of the present invention. Since the filter circuit portion has the same configuration as the circuit shown in FIG. 10, here, the same reference numerals as those in FIG. 10 are given to the circuit elements, and the description thereof is omitted, and only different portions will be described. And

  In FIG. 1, 1 is a variable constant current source that outputs a current Io, 2 is a variable constant current source that outputs a current Ix, 3 is a control signal generation circuit, and includes a variable constant current source 1 and a variable constant current source 2. Control currents I1 and I2 are output from the output terminal. At this time, the control currents I1 and I2 are set so as to be expressed by the following (Equation 12) and (Equation 13).

（数１２），（数１３）より、制御電流Ｉ1，Ｉ2は次の（数１４），（数１５）で表せる。

From (Equation 12) and (Equation 13), the control currents I1 and I2 can be expressed by the following (Equation 14) and (Equation 15).

ここで、図１のフィルタの伝達関数は図１０と同様で（数５）で与えられる。Ωo，Ｑについても図１０と同様で（数１０），（数１１）で与えられる。

Here, the transfer function of the filter of FIG. 1 is the same as that of FIG. Ωo and Q are also given by (Equation 10) and (Equation 11) as in FIG.

  Substituting the relationships shown in (Equation 14) and (Equation 15) into (Equation 10) and (Equation 11) yields (Equation 16) and (Equation 17).

上記数式より、ωoはＩoに比例し、ＱはＩxで調整されることがわかる。

From the above equation, it can be seen that ωo is proportional to Io and Q is adjusted by Ix.

  Next, considering that ωo and Q are adjusted, ωo can be adjusted by changing Io, and Q can also be adjusted by changing Io or Ix. Recognize. At this time, if only Ix is changed while adjusting Io in a fixed state, only Q can be adjusted with ωo fixed.

  FIG. 2 is a configuration diagram of a control signal generation circuit provided in the integrated circuit filter according to the first embodiment of the present invention. Transistors Q1 and Q2, transistors Q3 and Q4, and transistors Q5 and Q6 each constitute a current mirror, where 10 is a constant voltage terminal, 12 is a constant voltage source or ground terminal, and Io and Ix are inputs that receive current. Terminals I1 and I2 are output terminals that output current. A current mirror composed of transistors Q5 and Q6 changes the direction of current control.

  The current flowing through each transistor is assumed to have a sufficiently large hFE and Early voltage, and is assumed to be approximately equal without considering the difference in current due to variations and the like.

At this time, the relationship between the input current Io and the output currents I1 and I2 is as follows. When V _BE of the transistors Q1, Q2, Q3, and Q4 is expressed as V _BE1 , V _BE2 , V _BE3 , and V _BE4 , the following ( _Equation 18) to (Equation 21) hold.

Ｉs1は定数でＮＰＮトランジスタの順方向能動領域の伝達特性を表し、Ｉs2は定数でＰＮＰトランジスタの順方向能動領域の伝達特性を表す。

Is1 is a constant representing the transfer characteristic of the forward active region of the NPN transistor, and Is2 is a constant representing the transfer characteristic of the forward active region of the PNP transistor.

  Also, from FIG. 2, (Equation 22) is derived,

（数２２）に（数１８），（数１９），（数２０），（数２１）を代入すると（数２３）が導かれる。

Substituting (Equation 18), (Equation 19), (Equation 20), and (Equation 21) into (Equation 22) leads to (Equation 23).

また、図２において、Ｉxを引っ張り出す方向の電流とすると（数２４）が成立する。

Further, in FIG. 2, (Equation 24) is established when Ix is a current in a pulling direction.

したがって、ωo、Ｑについては図１と同様で（数１４），（数１５）で与えられる。これらにより、ωoはＩoに比例し、ＱはＩxで調整されることがわかる。

Accordingly, ωo and Q are given by (Equation 14) and (Equation 15) as in FIG. From these, it can be seen that ωo is proportional to Io and Q is adjusted by Ix.

  Here, considering that ωo and Q are adjusted, ωo can be adjusted by changing Io, and Q can also be adjusted by changing Io or Ix. Recognize. At this time, if only Ix is changed while adjusting Io in a fixed state, only Q can be adjusted with ωo fixed.

  FIG. 3 is a configuration diagram of a control signal generation circuit provided in the integrated circuit filter according to the second embodiment of the present invention. Note that portions having the same configuration as the circuit shown in FIG. 2 are denoted by the same reference numerals as those in FIG. 2 and description thereof is omitted, and only different portions are described.

In FIG. 3, each of transistors Q7 and Q8 and transistors Q9 and Q10 forms a current mirror. When the control current Io is input from the input terminal, a current equal to the transistors Q1, Q7, Q9, Q3 flows. At this time, when V _BE of the transistors Q7, Q8, Q9, and Q10 is expressed as V _BE7 , V _BE8 , V _BE9 , and V _BE10 , the following ( _Equation 25) is established.

トランジスタＱ7に流れ込む電流はＩo、トランジスタＱ8に流れる電流はＩ2、トランジスタＱ10に流れる電流はＩ1であるため、（数２５）の関係は図２から導かれる（数２２）と同等とみなすことができ、図２と同様に（数２３），（数２４）が成立し、以下、図２の説明で明記したようにωoとＱとを調整することが可能となる。

Since the current flowing into the transistor Q7 is Io, the current flowing through the transistor Q8 is I2, and the current flowing through the transistor Q10 is I1, the relationship of (Equation 25) can be regarded as equivalent to (Equation 22) derived from FIG. As in FIG. 2, (Equation 23) and (Equation 24) hold, and ωo and Q can be adjusted as specified in the description of FIG.

  FIG. 4 is a configuration diagram of a control signal generation circuit provided in the integrated circuit filter according to the third embodiment of the present invention. Note that portions having the same configuration as the circuit shown in FIG. 2 are denoted by the same reference numerals as those in FIG. 2 and description thereof is omitted, and only different portions are described. Transistors Q11 and Q12 and transistors Q13 and Q14 each constitute a current mirror.

  Next, in FIG. 4, when the control current Io is input from the input terminal, currents equal to the transistors Q11, Q1, Q3, and Q13 flow. At this time, the transistors Q1, Q2, Q3, and Q4 can be regarded as equivalent to (Equation 22) derived from FIG. 2, and (Equation 23) and (Equation 24) are established as in FIG. It is possible to adjust ωo and Q as specified in the description of FIG.

  FIG. 5 is a configuration diagram of a control signal generation circuit provided in an integrated circuit filter according to a fourth embodiment of the present invention. Note that parts having the same configuration as the circuit shown in FIG. 3 are denoted by the same reference numerals as those in FIG. 3 and description thereof is omitted, and only different parts will be described. The transistor is replaced with a current mirror circuit portion comprising transistors Q15 and Q16, transistors Q1 and Q2, and Q3 and Q4 in FIG.

  Next, in FIG. 5, when the control current Io is input from the input terminal, a current equal to the transistors Q7 and Q9 flows. At this time, the transistors Q7, Q8, Q9, and Q10 can be regarded as equivalent to (Equation 25) of FIG. 3. At this time, the current flowing into the transistor Q7 is Io, the current flowing through the transistor Q8 is flowing through I2, and the transistor Q10. The current is I1. Therefore, the relationship of (Equation 25) can be regarded as equivalent to (Equation 22) derived from FIG. 2, and (Equation 23) and (Equation 24) are established as in FIG. As specified in the description, it becomes possible to adjust ωo and Q.

  FIG. 6 is a block diagram of a control signal generation circuit provided in an integrated circuit filter according to the fifth embodiment of the present invention. Note that portions having the same configuration as the circuit shown in FIG. 2 are denoted by the same reference numerals as those in FIG. 2 and description thereof is omitted, and only different portions are described. Transistors Q17 and Q18 are added for base current compensation, and 11 is a constant voltage source. In FIG. 6, when the control current Io is input from the input terminal, a current equal to the transistors Q1 and Q3 flows. At this time, the transistors Q1, Q2, Q3, and Q4 can be regarded as equivalent to (Equation 22) derived from FIG. 2, and (Equation 23) and (Equation 24) are established as in FIG. As specified in FIG. 2, ωo and Q can be adjusted.

  The present invention can be used for a bandpass filter for band limitation in a receiver.

The block diagram of the integrated circuit filter in the 1st Embodiment of this invention 1 is a configuration diagram of a control signal generation circuit provided in an integrated circuit filter according to a first embodiment of the present invention. The block diagram of the control signal generation circuit with which the integrated circuit filter in the 2nd Embodiment of this invention was equipped. The block diagram of the control signal generation circuit with which the integrated circuit filter in the 3rd Embodiment of this invention was equipped The block diagram of the control signal generation circuit with which the integrated circuit filter in the 4th Embodiment of this invention was equipped The block diagram of the control signal generation circuit with which the integrated circuit filter in the 5th Embodiment of this invention was equipped The figure which shows the characteristic of a band pass filter, and the relationship between gm1 and gm2 The figure which shows the input / output terminal of Gm amplifier The figure which shows an example of the circuit of Gm amplifier Configuration diagram of conventional semiconductor integrated filter circuit of the present invention

Explanation of symbols

1, 2 Variable constant current source 3 Control signal generating circuit 4 1st Gm amplifier 5, 7 Buffer 6 2nd Gm amplifier 8, 9 Current source 10, 11 Constant voltage source 12 Constant voltage source or ground terminal

Claims (6)

A first transconductance amplifier whose transconductance value is controlled by a control signal input to the first control terminal and a second transconductance whose transconductance value is controlled by a control signal input to the second control terminal a filter circuit including an amplifier,
A first input terminal; a second input terminal; a first output terminal connected to the first control terminal; and a second output terminal connected to the second control terminal . A control signal generation circuit,
The control signal generation circuit includes :
A first current mirror circuit having a current input side connected to the first input terminal and a current output side connected to the second control terminal;
A second current mirror circuit in which the first current mirror circuit and each emitter on the current input side and the current output side are commonly connected, and the current input side is connected to a constant voltage source;
A third current mirror circuit having a current input side connected to the current output side of the second current mirror circuit, a current output side connected to the first control terminal, and an emitter connected to a constant voltage source or a ground terminal; Consists of
An integrated circuit filter characterized in that a common connection point between a current output side emitter of the first current mirror circuit and a current output side emitter of the second current mirror circuit is connected to the second input terminal. . The first current mirror circuit includes:
A first NPN transistor whose collector and base are short-circuited and connected to the first input terminal ;
A base connected to a collector and a base of the first NPN transistor, and a collector connected to the second output terminal ;
The second current mirror circuit includes:
The collector and base are short connected to a constant voltage source, a first PNP transistor whose emitter is connected to the emitter of the first NPN transistor,
A base connected to the collector and base of the first PNP transistor, and an emitter connected to the emitter of the second NPN transistor and the second PNP transistor connected to the second input terminal ;
The third current mirror circuit includes:
A third NPN transistor whose collector and base are short-circuited and connected to the collector of the second PNP transistor, and whose emitter is connected to a constant voltage source or a ground terminal;
A base connected to the collector and base of the third NPN transistor, a collector connected to the first output terminal, and an emitter connected to a constant voltage source or a ground terminal. The integrated circuit filter according to claim 1. The first current mirror circuit includes:
A first NPN transistor whose collector and base are short-circuited and connected to the first input terminal ;
A second NPN transistor having a base connected to the collector and base of the first NPN transistor, and a collector connected to the second output terminal ;
A third NPN transistor whose collector and base are short-circuited and connected to the emitter of the second NPN transistor;
A base connected to a collector and a base of the third NPN transistor, and a collector connected to an emitter of the first NPN transistor ;
The second current mirror circuit includes:
A first PNP transistor whose collector and base are short-circuited and connected to a constant voltage source ;
A second PNP transistor base over scan is connected to the collector and base of said first PNP transistor,
A third PNP transistor whose collector and base are short-circuited and connected to the emitter of the second PNP transistor, the emitter connected to the emitter of the third NPN transistor and the second input terminal ;
A fourth PNP transistor having a base connected to the collector and base of the third PNP transistor, a collector connected to the emitter of the first PNP transistor, and an emitter connected to the emitter of the fourth NPN transistor; Consists of
The third current mirror circuit includes:
A fifth NPN transistor having a collector and base short-circuited and connected to the collector of the second PNP transistor, and an emitter connected to a constant voltage source or a ground terminal;
A base connected to the collector and base of the fifth NPN transistor; a collector connected to the first output terminal; and an emitter connected to a constant voltage source or a ground terminal. The integrated circuit filter according to claim 1. The first current mirror circuit includes:
A first NPN transistor whose collector and base are short-circuited and connected to the first input terminal ;
A second NPN transistor having a base connected to the collector and base of the first NPN transistor, and a collector connected to the second output terminal ;
A third NPN transistor whose collector and base are short-circuited and connected to the emitter of the first NPN transistor;
Base connected to the collector and base of said third NPN transistor, consists of a fourth NPN transistor having a collector connected to the emitter of the second NPN transistor,
The second current mirror circuit includes:
A first PNP transistor whose collector and base are short-circuited and connected to a constant voltage source ;
A second PNP transistor base over scan is connected to the collector and base of said first PNP transistor,
A third PNP transistor having a collector and base short-circuited and connected to the emitter of the first PNP transistor, the emitter connected to the emitter of the third NPN transistor ;
Base over scan is connected to the collector and base of said third PNP transistor, a collector connected to the emitter of the second PNP transistor, the emitter emitter and the second input terminal of said fourth NPN transistor A fourth PNP transistor connected ,
The third current mirror circuit includes:
A fifth NPN transistor having a collector and base short-circuited and connected to the collector of the second PNP transistor, and an emitter connected to a constant voltage source or a ground terminal;
A base connected to the collector and base of the fifth NPN transistor; a collector connected to the first output terminal; and an emitter connected to a constant voltage source or a ground terminal. The integrated circuit filter according to claim 1. The first current mirror circuit includes:
A first NPN transistor having a base connected to the first input terminal and a collector connected to the second output terminal ;
A second NPN transistor whose collector and base are short-circuited and connected to the emitter of the first NPN transistor;
Base connected to the collector and base of the second NPN transistor, and a third NPN transistor having a collector connected to said first input terminal,
The second current mirror circuit includes:
A first PNP transistor whose base is connected to a constant voltage source;
A second PNP transistor having a collector and base short-circuited and connected to the emitter of the first PNP transistor, the emitter connected to the emitter of the second NPN transistor and the second input terminal ;
A third PNP transistor having a base connected to the collector and base of the second PNP transistor, a collector connected to a constant voltage source, and an emitter connected to the emitter of the third NPN transistor ;
The third current mirror circuit includes:
A fourth NPN transistor having a collector and base short-circuited and connected to the collector of the first PNP transistor, and an emitter connected to a constant voltage source or a ground terminal;
A base connected to the collector and base of the fourth NPN transistor, a collector connected to the first output terminal, and an emitter connected to a constant voltage source or a ground terminal. The integrated circuit filter according to claim 1. The first current mirror circuit includes:
A first NPN transistor having a base connected to the first input terminal and a collector connected to a constant voltage source;
A second NPN transistor having a collector connected to the first input terminal and a base connected to an emitter of the first NPN transistor;
A third NPN transistor having a base connected to the base of the second NPN transistor and a collector connected to the second output terminal ;
The second current mirror circuit includes:
A first PNP transistor having a base connected to a constant voltage source and a collector connected to the constant voltage source or a ground terminal ;
A second PNP transistor having a collector connected to a constant voltage source, a base connected to the emitter of the first PNP transistor, and an emitter connected to the emitter of the second NPN transistor;
A base connected to the base of the second PNP transistor, and an emitter comprising a third PNP transistor connected to the emitter of the third NPN transistor and the second input terminal ;
The third current mirror circuit includes:
A fourth NPN transistor whose collector and base are short-circuited and connected to the collector of the third PNP transistor, and whose emitter is connected to a constant voltage source or a ground terminal;
A base connected to the collector and base of the fourth NPN transistor, a collector connected to the first output terminal, and an emitter connected to a constant voltage source or a ground terminal. The integrated circuit filter according to claim 1.

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