JP4283788B2 - Digital protection controller - Google Patents

Description

  The present invention relates to a digital protection control apparatus, and more particularly, to a digital protection control apparatus that facilitates expansion and monitoring of each element by connecting components to a serial bus.

  As conventional digital protection control devices, for example, digital protection relays described in Patent Literature 1 and Non-Patent Literature 1 are known. The digital protection relay includes a communication interface such as an analog input unit, a digital arithmetic processing unit including a human interface unit, an input / output unit, an accident detection unit, and PCM communication. The analog input unit and the PCM communication interface unit are connected in parallel (parallel connection) to the system bus from the digital arithmetic processing unit, and the input / output unit is connected in parallel to the I / O bus. In these buses, the digital arithmetic processing unit serves as a bus master and performs data transfer between each element.

JP 2004-64892 A 2002 IEEJ Power and Energy Division Conference] Lecture number 215

  In the prior art described above, data between components cannot be transferred without a bus master. For this reason, a lot of time is spent on the transfer processing of the bus master, and the processing load is unbalanced.

  In addition, if each component is abnormal, the digital arithmetic processing unit, which is the bus master, reads and confirms the data, and finally outputs an abnormality to the output unit. There was a restriction that could not be output.

  Furthermore, when expanding functions, it is necessary to connect each printed circuit board to a parallel bus, and the unit size (number of boards that can be mounted) is limited, so there are restrictions on bus expansion, and flexible system expansion is difficult. It was. In addition, since it is composed of a parallel bus, there are mounting restrictions.

  An object of the present invention is to provide a digital protection control device that eliminates the processing burden of the bus master and enables standardization and expandability of each unit in view of the above-described problems of the prior art.

  The digital protection control device of the present invention connects each element constituting the device with a serial bus composed of fixed-cycle protocol communication means, and each element is equipped with a global memory and a communication controller, and updates data every fixed cycle. It is comprised so that it may carry out.

  The serial bus of the fixed-cycle protocol communication means has a bus master function capable of taking the bus right, and transmits data between the elements at a fixed cycle. The fixed-cycle protocol communication means sends the corresponding data at a predetermined data transfer cycle and receives the transmission data by all elements.

  In such a configuration, a power system protection / control device that requires hard real-time control can be realized.

  In the digital protection control device of the present invention, each element has a common serial bus interface, and each can transmit and receive data at a fixed period, so that the degree of freedom of combination for each element is increased, and expansion and aggregation of the device configuration are easy There is an effect that can be done.

  In addition, since the processing load related to the data transfer of the CPU calculation means constituting the protection control device can be remarkably reduced, it is possible to allocate a large amount of CPU resources to the original protection control calculation and increase the CPU's original calculation capability. effective.

  Furthermore, since all data flows on the serial bus and each element can obtain the data as shared information, mutual monitoring becomes easy. Further, since it is serial data, it is possible to easily verify the data and to achieve high reliability.

  The digital protection control device of the present invention is configured by serial bus connection and shares input / output information for each component. Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing Embodiment 1 of the digital protection control apparatus of the present invention. This apparatus includes an input converter 1k that takes in a signal from the power system, protection arithmetic means 1a that performs main detection arithmetic processing based on a predetermined arithmetic processing, main information that takes in contact information of the device and gives an operation output signal to the device. It has a digital input / output means 1b on the detection side. Further, based on the signal 11 from the input converter 1k and a predetermined calculation process, the protection calculation means 1d for performing an accident detection calculation process for fail-safe use, an accident that takes in the contact information of the apparatus and gives an operation output signal to the apparatus It has a digital input / output means 1e on the detection side.

  Furthermore, a human interface means 1c is provided which is connected to the communication HUB 1h and the portable HI 1j via the external network 1i to perform communication and is connected to the operation panel 1g to capture operation information. Moreover, the extended function 4a comprised by the PCM communication mechanism 4b and the optical module 4d, and auxiliary | assistant arithmetic CPU4c is provided. The PCM communication mechanism 4b and the optical module 4d are coupled to a protection control dedicated network (PCM communication network) by an optical cable 4e.

  Each of the above-described constituent means is connected to the real-time serial bus 3a to constitute a protection control unit. In each component, the protection arithmetic units 1a and 1d, the PCM communication mechanism 4b, and the optical module 4c are preliminarily equipped with a shared memory 100, and the input / output units 1b and 1e are preliminarily equipped with a shared I / O 101.

  The real-time serial bus 3a is operated under the condition that the maximum delay time of the transmission time is guaranteed. This maximum delay time refers to the maximum delay time determined by the transmission speed and the number of components connected to the serial bus. In general, Ethernet (registered trademark) communication is used as a communication means, and TCP / IP is used as a protocol. However, collision of data on communication is allowed and the maximum delay time is not guaranteed. The communication of the present embodiment is characterized in that data is transmitted so that there is no data collision by sequentially allocating the time for occupying the transmission line for each constituent means.

  Next, the operation in the system of FIG. 1 will be described. The protection calculation means 1a that performs the main detection calculation process and the protection calculation means 1d that performs the accident detection calculation process convert the analog input signal into an analog digital signal in increments of 7.5 electrical degrees. Filter processing is performed using the converted data, and protection calculation processing and protection sequence processing are periodically performed in increments of 30 degrees.

  As a result of the calculation, when it is detected that an accident has occurred in the system, the cutoff output and the operation command output to the external device are output to the digital input / output means 1b via the serial bus 3a. Similarly, the accident detection unit 1d outputs a cutoff output and an operation command to an external device to the digital input / output means 1e via the serial bus 3a. The above-described main detection output and accident detection output are output as a final shut-off command under an AND condition configured by TelRY1f.

  As described above, since signals can be transmitted and received via the serial bus, it is possible to greatly reduce the number of lines and to greatly increase the degree of freedom of mounting due to the line saving. For the real-time serial bus 3, if the data is transferred between each component within 30 degrees (1.38ms or 1.66ms) of electrical angle required for real-time processing of the protection control device, the electrical angle of the device is 30 degrees. There is no loss of cycle performance.

  FIG. 2 shows an outline of the operation of the apparatus of FIG. 1, and shows the data communication function, the shared memory (global memory), and the operations of the shared I / O that are essential for the operation of the configuration of FIG. The overall configuration consists of a main detection protection calculation unit 200a, an accident detection calculation unit 200b, an HI unit 200c, a PCM communication processing unit 200d, and an I / O unit 200e, and the global memory 2b via the communication mechanisms 2c, 2g, 2k, and 2o. 2f, 2j and 2n, respectively. In addition, the I / O is output from the communication mechanism 2t to the auxiliary relay driver 2s that drives the auxiliary relay 2q, and the isolated input is input via a photocoupler that inputs and electrically isolates external device information. The signal from the means 2r is input.

  As a matter of course, in order to electrically isolate each arithmetic unit and the I / O unit, pulse transformers 2d, 2h, 2l, 2p, and 2u are mounted between the communication unit and the serial bus 200f. That is, even if each communication means fails, the serial bus signal is not affected.

  Each communication mechanism operates to sequentially update data with respect to each global memory at a predetermined cycle. In the global memory 100, an area is provided for each arithmetic function connected to the serial bus, so that there is no overlap.

  This is realized by providing the time management means 20a in the communication mechanism 2c. The time management means 20a adjusts the timing between the components, operates so as to keep almost the same time, and controls the serial bus access by operating in accordance with the timing assigned in advance to the components. To avoid duplication.

  Specifically, the time management means 20a is provided with a counter, and this counter is updated so as to match the movement of the entire serial bus, and control is performed so as to determine the access right based on a match with a predetermined counter value.

  Further, the area provided for each calculation function can be accessed from each calculation unit, but the data is guaranteed for the write operation so that only the area defined for the own station can be written. For example, the CPU calculation unit (M) 2a can write only the M-RY area. Other areas are read only.

  Also in the I / O unit, each communication mechanism can arbitrarily read. For writing, the main detection side CPU 2a can write only to the main detection DI / DO 1b, and only the accident detection side CPU 2e can write to the accident detection side DI / DO 1e. I am doing so. This is because the main detection and the accident detection are performed by separate hardware, so that the I / O board is separated so that an unnecessary operation does not occur due to a failure of a single component.

FIG. 3 shows an outline of the operation of the configuration described in FIGS. The communication mechanism (1) 2c, the communication mechanism (2) 2g, the communication mechanism (3) 2k, and the communication mechanism (4) 2o are connected to the shared memory GM100. The right to access the serial bus 200f is given every cycle T _{LAN in} order from the communication mechanism (1) 2c, and data is written. A communication mechanism having no access right to the serial bus 200f waits for the access right to come around.

When the operation of the communication mechanism (1) 2c is completed, the right to access the serial bus 200f is transferred to the next communication mechanism (2) 2g. Similarly, the communication mechanism (2) 2g accesses the serial bus 200f and writes data. Such operations are performed in order, and the access right is sent to the communication mechanism (1) 2c again. These series of operations are performed for a certain time every time T _CPU to guarantee real-time performance. That is, the maximum delay time for data transfer is guaranteed.

  Next, a detailed operation of the communication control method using the real-time serial bus will be described. FIG. 4 shows the operation sequence of the CPU substrate, the real-time communication unit, and the real-time serial bus side of each arithmetic unit shown in FIG. 2 in time series.

First, the CPU writes the information part and data part of its own station data in the interface memory every fixed period T _CPU period (for example, every 30 electrical angles). At this time, on the serial bus side, a transmission operation is performed while sequentially turning tokens which are the right to access at regular intervals. The real-time communication control side detects a token addressed to itself, transmits transmission data to the serial bus side, waits for a response signal, sends a transmission end information after confirming the response signal. Thereafter, the token is passed to the next station, and the series of cycles is completed.

As a matter of course, this series of cycles cannot be guaranteed unless the cycle is shorter than the T _CPU cycle, and therefore the intervals are sufficiently short. Moreover, the transfer operation time of all stations is also made shorter than the T _CPU cycle.

  With this configuration, information can be transmitted and received in real time via a serial bus. Of course, since it is a serial signal, it is possible to detect communication failure and correct data by adding a redundant code, and it goes without saying that high reliability can be achieved.

  FIG. 5 shows an example of the internal configuration of the M-RY and FD-RY, which are CPU arithmetic mechanisms. An input signal (system input) that has been voltage-converted from the power system via the input converter is taken in and filtered by an analog filter 5a for preventing aliasing errors due to sampling. The output signal of the analog filter 5a is sequentially switched by the multiplexer 5b, converted into a digital signal by the A / D converter 5c, the digital signal is output, and stored in the memory 5d.

  After A / D conversion, the digital filter processing and the protection calculation / sequence processing for removing the low-order harmonic components generated at the time of a system fault are executed by the microcontroller 5f. The microcontroller 5f includes a CPU core for executing calculations, a floating-point calculation mechanism FPU, a ROW that stores the filter calculation program and the communication processing program in advance, a calculation RAM, a peripheral circuit, and an interrupt control mechanism. Is provided.

  The timing control circuit 5e manages a communication cycle for each fixed cycle, and issues an interrupt signal to the CPU every 30 electrical angles, a channel switching signal to the multiplexer 5b, and an A to the A / D converter 5c. / D conversion timing command, write signal to memory 5d, etc. are output.

  The real-time communication unit 5i is connected to the serial bus 5m via the driver 5j and the pulse transformer 5k. The real-time communication unit 5i includes an interface memory 5ia as a global memory. The real-time communication unit 5i operates to accumulate data written from the microcontroller 5f in the interface memory and distribute this data to each unit at regular intervals.

  FIG. 6 shows the internal configuration of the human interface. The HI unit 1c corresponds to two networks of a real-time communication serial bus 6m and an Ethernet (registered trademark) LAN 6s. The human interface 1c includes a microcontroller 6f and a controller bus 6i, and an arithmetic / processing work RAM 6g, a data saving memory 6h, a real-time communication unit 6i, and a LAN communication 6p are tightly coupled to the controller bus 6i. The controller 6f has the same function as 5f shown in FIG. 5, but the stored program is different.

  The LAN communication 6p is output to the external network 6s via the pulse transformer 6r and receives a signal from the external network 6s. The Ethernet (registered trademark) LAN is connected to the external Ethernet (registered trademark) LAN 1i via the HUB 1h shown in FIG. 1, and remote communication can be achieved by exchanging communication information with the portable HI 1c.

  Similarly to the real-time communication unit 5i shown in FIG. 5, the real-time communication unit 6i has an interface memory 6ia and is connected to the real-time serial bus 6m via a driver 6j and a pulse transformer 6k for signal insulation.

  FIG. 7 shows an example in which the above-described protection control unit is mounted on a panel. The protection control unit mounting board 700a includes a power supply unit 7a, an input converter PCT7b, a CPU board 7c for HI, a main detection CPU board MCPU7d, an accident detection CPU board FDCPU7e, an MI / O unit on which a plurality of MDI / DO7g are mounted, and an FDDI / DO7h. It is composed of the FDI / O unit that implements multiple. The FI / O part is connected by a serial cable 7f which is a real-time serial, and the MI / O part is connected by a serial cable 7h, both of which are the same network cable.

  As described above, since the signal connection between the I / O unit and the CPU can be performed with a light and flexible serial cable, there is an effect of increasing the degree of freedom of the configuration layout in the panel. Naturally, if the number of I / O points is increased, the above-described serial cable may be expanded and configured, so that there is an advantage that it is possible to flexibly cope with changes in device specifications.

  Further, since all the components constituting the protection control unit can be connected by a real-time serial bus, not only the implementation example shown in FIG. 7 but also, for example, the racks can be distributed and arranged in different units for each component. For example, since it is clear that the HICPU is positioned at the eye level of the operator, the operability and visibility are clearly improved, and thus there is an advantage that the system configuration is not restricted in this way.

  Next, another embodiment of the present invention will be described. 8 is a modification of the configuration of the first embodiment. The HI mechanism unit 1c is configured not to be connected to the real-time serial 3a but to be connected to a dedicated internal serial bus 8a.

  In this configuration, since the HI mechanism 1c does not require real-time performance as much as the protection control calculation, it is connected to another low-speed serial bus 8a to increase the load factor of the serial bus related to protection control.

  FIG. 9 shows still another modification of the first embodiment. Here, the real-time serial bus is divided into a main detection serial bus 9a and an accident detection serial bus 9c. As a result, the main detection and the accident detection can be completely separated.

  The embodiments of the present invention have been described above. Furthermore, since the present invention can capture externally sensed analog input information and device information captured as a digital signal via a serial bus, the calculation part, the input unit, and the output part are not in the same unit, but at separate positions. Can also be configured. For this reason, the present invention can also be applied to I / O device control applications that are distributed.

1 is a block diagram of a digital protection control apparatus according to a first embodiment of the present invention. FIG. 2 is a block configuration diagram illustrating a communication mechanism and a shared memory of the digital protection control device according to the first embodiment. FIG. 6 is a schematic explanatory diagram of an operation of a communication mechanism. 3 is a timing chart showing the operation of the first embodiment. FIG. 3 is a block configuration diagram illustrating protection control calculation means according to the first embodiment. 1 is a block configuration diagram illustrating a human interface of Embodiment 1. FIG. The block block diagram which shows the accident detection means of the digital protection control apparatus of Example 1. FIG. The block block diagram by Example 2 of the digital protection control apparatus of this invention. The block block diagram by Example 3 of the digital protection control apparatus of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1a ... Protection arithmetic means (main detection side), 1b ... Digital input / output means (main detection side), 1c ... Human interface means, 1d ... Protection arithmetic means (accident detection side), 1e ... Digital input / output means (accident) Detection side), 1f ... TelRY, 1g ... operation panel, 1h ... communication HUB, 1i ... external network, 1j ... portable HI, 1k ... input converter, 2a, 2e, 2i, 2m ... CPU calculation unit, 2b, 2f , 2j, 2n ... global memory, 2c, 2g, 2k, 2o, 2t ... communication mechanism, 2d, 2h, 2l, 2p, 2u ... pulse transformer, 2q ... auxiliary relay, 2r ... insulated input means (photocoupler), 3a ... real-time serial bus, 4b ... PCM communication mechanism, 4c ... auxiliary operation CPU, 4d ... optical module, 5a ... analog filter, 5b ... multiplexer 5c ... A / D converter, 5d ... memory, 5e ... timing control circuit, 5f ... micro controller, 5i ... real time communication unit, 5ia ... interface memory, 5j ... driver, 5k ... pulse transformer, 5m ... serial bus, 6f ... Microcontroller, 6g ... RAM for calculation / processing work, 6h ... Memory for data saving, 6i ... Controller bus, 6ia ... Interface memory, 6j ... Driver, 6k ... Pulse transformer, 6m ... Real-time serial bus, 6p ... LAN communication, 6r ... pulse transformer, 6s ... network, 7a ... power supply unit, 7b ... input converter PCT, 7c ... CPU board for HI, 7d ... main detection CPU board MCPU, 7e ... accident detection CPU board FDCPU, 7f, 7i ... serial cable, 7h ... FDDI / DO, 7g ... MDI / DO, 20a ... Time manager Stage: 100 ... Shared (global) memory, 101 ... Shared I / O, 200a ... Main detection protection calculation unit, 200b ... Accident detection calculation unit, 200c ... HI unit, 200d ... PCM communication processing unit, 200e ... I / O unit 700a ... Protection control unit mounting board.

Claims (5)

An analog input means for taking in an analog AC electric quantity of a power system and converting the electric quantity into a digital quantity, a digital input for taking in status information from the system equipment and a digital output for outputting an operation output to the system equipment a / O unit, the digital protective control apparatus having a protection operation means for performing a protective control operation of the main detection, a fault detection hand stage for performing protective control operation of fault detection,
The protection calculation means, the accident detection means, and the digital I / O means for main detection and accident detection are connected to the same serial bus, and the protection calculation means and the accident detection means are provided for each calculation function of their own calculation means. a global memory having an area that can be written to, a communication means for updating written sequentially corresponding area of another global memory at a fixed cycle via the serial bus the data stored in each area of the global memory of the arithmetic means A digital protection control device, wherein each of the computing means monitors data in another area of the global memory . In claim 1, the digital protective control apparatus which sets a writable access to the global memory for each operating means, except for the own unit is characterized in that so as to allow only reading of said operation means. 2. The digital protection control device according to claim 1, wherein transmission timings of the protection calculation unit, the accident detection unit, and the digital I / O unit are set to predetermined timings to avoid transmission timing conflicts. 2. The digital protection control device according to claim 1, wherein the protection calculation means, the accident detection means, and the digital I / O means are arranged in a distributed manner. An analog input means for taking in an analog AC electric quantity of a power system and converting the electric quantity into a digital quantity, a digital input for taking in status information from the system equipment and a digital output for outputting an operation output to the system equipment In a digital protection control apparatus comprising: / O means; protection calculation means for performing protection control calculation for main detection; accident detection means for performing protection control calculation for accident detection; and human interface means for performing setting operation and status display.
The protection calculation means, the accident detection means, and the digital I / O means for main detection and accident detection are connected to the first serial bus, and the human interface means is connected to the first serial bus or the second serial bus. And a global memory having an area that can be written for each calculation function of the protection calculation means, the accident detection means, and the human interface means, and a global memory of the protection calculation means, the accident detection means, and the human interface means Communication means for sequentially writing and updating data stored in each area in a corresponding area of another global memory at regular intervals, and each of the protection calculation means, the accident detection means, and the human interface means is the global memory. Monitor data in other areas Digital protective control apparatus according to claim Rukoto.

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