JP2006311761A - Digital protection relay system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve digital filter processing at an inexpensive cost by suppressing a burden increase of main CPU of an operation processing part and suppressing the increase in space. <P>SOLUTION: A digital protection relay system is provided with an analog input part 1, to which the measured electrical quantity information of a system is inputted, a digital input part 4 to which contact point information of a circuit breaker is inputted, the calculation processing part 8 performing relay calculation determination by output information from the analog input part 1, a digital output part 3 for controlling the circuit breaker, by including the result of relay operation determination and a man/machine I/F part 5 for setting and/or changing the set value for relay calculation determination. A digital filter function is loaded on a bus control part 81, which conducts the bus function of the calculation processing part 8 transmitting information with the respective parts. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a digital protection relay device installed in a power system.

  In the conventional digital protection relay device, each function unit is divided into branches with the internal system bus as the center, and each function is divided, and information transfer between these function units is performed by the system bus. A configuration is employed (see, for example, page 286 of Non-Patent Document 1, FIG. 14.14). In addition, the main CPU performing the main function performs digital filter processing with a fixed processing method and no branch processing (for example, page 113 of Non-Patent Document 1, page 5.14 and page 113 of page 113). Line 5 to page 114, line 3).

  The configuration of the conventional digital protection relay device is configured as shown in FIG. 14.14 on page 286 of Non-Patent Document 1, and the digital filter processing is shown in FIG. 5.14 on page 113 of Non-Patent Document 1. Thus, it is implemented as part of the main CPU processing. FIG. 6 is a block diagram showing a conventional digital protective relay device, and is a diagram supplementing FIG. 14.14 on page 286 of Non-Patent Document 1. FIG. 7 is a diagram for explaining the processing method of the arithmetic processing unit of the conventional digital protection relay device, and explains the processing of the main CPU. In addition, in FIG. 6, the function controller in FIG. 14.14 on page 286 of Non-Patent Document 1 is supplemented with a bus controller (B-CNT) and a buffer (Buf) that are naturally included in the part that cooperates with the system bus. Yes.

  In order for the conventional digital protective relay device to perform its function, the analog input unit 1 obtains an analog input value from the input conversion unit (which converts the measured current value, voltage value, etc. at a predetermined ratio), and calculates In the processing unit 2, individual relay operation calculation determination (protection relay operation calculation determination) is performed. Before the relay operation calculation is performed, input data is captured as shown in FIG. Calculation (S2) is performed.

  The operation up to this point will be described with reference to FIGS. FIG. 8 is a diagram for explaining the flow from self-end A / D data generation to data saving after digital filtering. First, the analog input value from the input conversion unit is cut by noise or the like by the analog filter 11. An analog value is held from the analog input value by the sample hold function 12, and is sequentially applied to the A / D converter 14 by the multiplexer 13 to obtain digital data (hereinafter referred to as A / D data) (S11). By setting the A / D data in the buffer 16 of the analog input unit 1 (S12), both buses of the analog input unit 1 and the arithmetic processing unit 2 are stored in the memory unit 21 (RAM) of the arithmetic processing unit 2. The data is transferred via the system bus 7 by the bus function of the controller 15 (S13). The above is implemented by a hardware function (see FIG. 8).

  Thereafter, the processing by the CPU 22 of the arithmetic processing unit 2, that is, processing by software is performed. In FIG. 6, reference numeral 23 denotes an internal bus of the arithmetic processing unit 2. In order to show the handling of A / D data in detail, details of the arithmetic processing unit 2 are shown in FIG. The A / D data transferred to the arithmetic processing unit 2 exists in the RAM 25 of the arithmetic processing unit 2. Based on the program stored in the ROM 24, the CPU 22 of the arithmetic processing unit 2 performs digital filter processing (S2) (S14) from the A / D data (input data) of the RAM 25, and the result is again stored in another area of the RAM 25. Is stored as data after the digital filter (S15).

  Using the data after the digital filter, the operation calculation and determination of each individual relay element are performed thereafter (S3). Further, based on the operation calculation / determination result of the relay element, a timer / logic sequence calculation (for example, a sequence calculation of a time limit element, a logic circuit, etc.) is performed (S4), and the result is output to the outside (S6). At the same time, an automatic monitoring calculation (for example, a calculation for periodically monitoring whether the input is normally input or the relay operation is normal) is performed (S5). The output of the timer / logic sequence calculation is saved as a result (S7), saved in a temporary save area of the RAM 25, and further saved in the data save memory 26 from the data save memory 26 as a normal save. It is saved in the area as a past history (first phenomenon, second phenomenon, ----- tenth phenomenon).

  FIG. 10 is a diagram for explaining a flow from serial data at the other end to saving of data after digital filtering. The flow from serial data at the other end to saving of the data after the digital filter will be described with reference to FIGS. An optical signal from the other end is converted into an electrical signal and input. Serial data from the other end is converted into parallel data by the serial-parallel converter 64 and transferred from the bus controller (B1-CNT) 65 to the memory unit 61 in the transmission unit 6 via the internal bus 66 of the transmission unit 6. (S21). Up to this point, the processing is performed by hardware.

  Next, the counterpart A / D data is extracted from the data in the memory unit 61 of the transmission unit 6 and saved in the buffer 16 in the transmission unit 6 (S22). Up to this point, the processing is performed by software of the CPU 62 in the transmission unit 6. By saving in the buffer 16, the data is transferred to the RAM 25 of the memory unit 21 of the arithmetic processing unit 2 as A / D data by the bus functions of both the bus controllers 15 of the transmission unit 6 and the arithmetic processing unit 2. The above is implemented by hardware functions.

  Thereafter, the processing by the CPU 22 of the arithmetic processing unit 2, that is, processing by software is performed. The A / D data transferred to the arithmetic processing unit 2 exists in the RAM 25 (FIG. 9) of the arithmetic processing unit 2. The CPU 22 of the arithmetic processing unit 2 performs digital filter processing from the A / D data in the RAM 25 based on the program in the ROM 24 (S24), and stores the result again as data after the digital filter in another area of the RAM 25 ( S25). The operation calculation / determination of each individual relay element is performed using the counterpart data after the digital filter and the self-end A / D data after the digital filter.

  Further, based on the operation calculation / determination result of the relay element, the timer / logic sequence calculation is performed and the result is output to the outside. The output of the timer / logic sequence calculation is the result of data saving, saving to a temporary saving area of the RAM 25, and further storing the data in the data saving memory 26 to the normal saving area of the data saved in the past. It is saved as a history (first phenomenon, second phenomenon, ----, tenth phenomenon). In addition, in the transmission part 6 of FIG. 6, 63 is the parallel-serial converter 63 of the transmission part 6, and transmits the signal of an end to the other end from there. Each functional unit not described in FIG. 6 will be described later.

Supervised by Yoshifumi Oura, protection relay system engineering, published by the Institute of Electrical Engineers, published on March 15, 2002

As described above, since the CPU 22 of the arithmetic processing unit 2 always performs the digital filter process before the operation calculation / determination of the relay element, when the number of inputs from the input conversion unit is large, the digital filter process is performed. It takes a lot of time, and there is a problem that a separate processing unit 2 is provided and digital filter processing is realized with an increase in space and cost.
The present invention has been made to solve the above-described problems. Even when the number of inputs from the input conversion unit is large, an increase in the load on the main CPU of the arithmetic processing unit is suppressed, and the space is increased. The first object is to realize digital filter processing at a low cost.

In addition, in the digital protection relay device that performs the protection relay function based on the information on the local end and the information on the other end, as shown in FIG. 6, there are many hardware parts related to the transmission unit, which is an obstacle to downsizing. It was.
The present invention has been made to solve the above-described problems. The second object is to achieve the first object and to reduce the size of the digital protective relay device including the transmission unit. To do.

  The digital protective relay device according to the present invention includes an analog input unit to which measured electrical quantity information of a system is input, a digital input unit to which contact point information of a circuit breaker is input, and a relay based on output information from the analog input unit. Operation processing unit for determining operation calculation, digital output unit for controlling the circuit breaker including the result of relay operation operation determination, digital having man-machine I / F unit for setting and / or changing settling value for relay operation operation determination In the protective relay device, a digital filter function is mounted on a bus control unit that handles the bus function of the arithmetic processing unit that performs information transmission with each of the above units.

  The digital protective relay device according to the present invention includes an analog input unit to which measured electrical quantity information of a system is input, a digital input unit to which contact point information of a circuit breaker is input, and output information from the analog input unit. A processing unit for determining the relay operation calculation by a digital output unit for controlling the circuit breaker including the result of the relay operation calculation determination, and a man-machine I / F unit for setting and / or changing a set value for the relay operation calculation determination The digital protection relay device includes a digital filter function in the bus control unit that handles the bus function of the arithmetic processing unit that performs information transmission with each of the units, and the other end and the own terminal in the bus control unit of the arithmetic processing unit. It is equipped with an information transmission function and an information editing function.

  According to the digital protection relay device of the present invention, since the digital filter function is mounted on the bus control unit responsible for the bus function of the arithmetic processing unit, an increase in the burden on the main CPU of the arithmetic processing unit is suppressed, and an increase in space is suppressed. In addition, digital filter processing can be realized at low cost.

  Further, according to the digital protection relay device of the present invention, the digital filter function is mounted on the bus control unit responsible for the bus function of the arithmetic processing unit, and information on the other end and the own end is provided in the bus control unit of the arithmetic processing unit. Since the transmission function and the information editing function are installed, the burden on the main CPU of the arithmetic processing unit is suppressed, the increase in space is suppressed, and digital filter processing is realized at low cost, without passing through the system bus. The digital protective relay including the transmission unit can be reduced in size.

Embodiment 1 FIG.
1 is a block diagram showing a digital protection relay apparatus according to Embodiment 1 of the present invention. FIG. 2 is a diagram illustrating the configuration and operation of the arithmetic processing unit in FIG. FIG. 3 is a diagram for explaining the processing method of the main CPU of the arithmetic processing unit. In the drawings, the same reference numerals as those in the conventional example indicate the same or corresponding parts, and redundant description may be omitted. In FIG. 1, the analog input unit 1 measures the amount of electricity in the system, and the current output of the instrument current transformer or the voltage output of the instrument transformer is converted and input by the input conversion unit, and an analog filter (AF) 11 A sample hold function (S / H) 12, a multiplexer (MPX) 13, an A / D converter 14, a buffer (Buf) 16, and a bus controller (B-CNT) 15, which are connected to the system bus 7.

  The digital input unit 4 receives ON / OFF information of contacts such as a circuit breaker (CB) and has a digital input (D / I) 41, a buffer (Buf) 16, and a bus controller (B-CNT) 15. Connected to bus 7. The arithmetic processing unit 8 is connected to the system bus 7 and includes a bus control unit (B2-CNT) 81, a CPU 22, and a memory unit 21. As shown in FIG. 2, the bus control unit (B2-CNT) 81 includes a digital filter (DF) 84 and a transmission unit 68 having an information transmission function and an information editing function with the counterpart end. In the transmission unit 68, the electrical signal transmitted from the other end is converted and edited from serial data to parallel data by the serial-parallel converter (S / P) 64, and is taken in as the other end A / D data 82. The / D data 83 is converted and edited from parallel data to serial data by a parallel-serial converter (P / S) 63, and is converted from an electrical signal to an optical signal and transmitted to the other end.

  The digital output unit 3 is connected to the system bus 7 and has a bus controller (B-CNT) 15, a buffer (Buf) 16, and a digital output (D / O) 31. The trip circuit (breaker) is controlled by the result of the timer / logic sequence operation that reflects the result. The man machine I / F unit 5 has an input / output screen (display) made up of a touch panel or the like, and is connected to the system bus 7, and includes a bus controller (B-CNT) 15, a buffer (Buf) 16, and a man machine I / F 51. And a settling value and a change value for relay operation calculation determination are input.

  1, 2, 3, and 4 until the amount of electricity input from the own input converter is saved in the RAM 25 in the arithmetic processing unit 8 as data after digital filtering. I will explain. FIG. 4 is a diagram for explaining the flow from self-end A / D data generation to data saving after digital filtering. The information input from the input converter at its own end is saved in the buffer 16 in the analog input unit 1 as A / D data (output information of the analog input unit 1) (S41) as in the prior art (S42). . Referring to FIG. 2, the contents of the buffer 16 of the analog input unit 1 are then transferred from the bus controller 15 of the analog input unit 1 and the bus control unit 81 in the arithmetic processing unit 8 to the local end A in the bus control unit 81. / D data is taken into the bus control unit 81 (S43).

  Next, the bus control section 81 in the arithmetic processing section 1 performs processing of the digital filter 84 (S44), and the result is saved in the RAM 25 (S45). S41 to S45 so far are processing by hardware. The bus control unit 81 in the arithmetic processing unit 1 is realized by an LSI that can change detailed functions such as an FPGA (Field Programmable Gate Array). The FPGA is hardware that can process a digital signal at high speed and can be set and changed.

  As shown in S1 to S7 of FIG. 7, the CPU processing in the conventional arithmetic processing unit must be digitally filtered by the CPU of the arithmetic processing unit, but is configured as shown in FIGS. In the digital protection relay device, digital filter processing is realized by hardware with the digital filter 84 of the bus control unit 81 of the arithmetic processing unit, and the software processing of the CPU of the arithmetic processing unit does not require digital filter processing. Operational operation / determination (S3), timer / logic sequence (S4), automatic monitoring (S5), output (S6), and data saving (S7) of the individual relay elements in FIG. Thus, even when the number of inputs is large, it is possible to suppress an increase in the burden on the CPU of the arithmetic processing unit. Compared with what implements the arithmetic processing part 2 separately provided like before, the increase in a space can be suppressed and the increase in cost can be suppressed.

Embodiment 2. FIG.
In the first embodiment, the digital filter processing of the own A / D data has been described. In the second embodiment, further, what performs the protection function by using the A / D data at the other end and the A / D data at the other end will be described with reference to FIGS. FIG. 5 is a diagram for explaining the flow from serial data at the other end to saving of data after digital filtering. The serial data of the electrical signal from the other end is input to the bus control unit 81 in the arithmetic processing unit 8. Further, the serial data is directly input to the serial-parallel converter 64, and converted to parallel data and edited. In the function of the conventional digital protection relay device, there is further editing processing after parallel data conversion, and this function is implemented by the bus control unit 81. After extracting the counterpart A / D data (S51), the processing of the digital filter unit 41 is performed by the bus function in the bus control unit 81 (S52), as in the case of the own end A / D data (S52). The data is transferred to the data area after the digital filter in the RAM 25 (S53). These S51 to S53 are hardware processes of the bus control unit 81.

  Since the data after the digital filter of the own end and the other end has been prepared in the RAM, the CPU 22 thereafter performs relay operation calculation determination (S3), timer logic sequence (S4), automatic monitoring (S5), output (S6), Data saving (S7) is performed. On the other hand, the own end A / D data needs to be transmitted to the other end, but as already described in the first embodiment, the end end A / D data is in the bus control unit 81. Serial data is converted and edited through a parallel-serial conversion unit 63 in the bus control unit 81, and an electrical signal is converted to an optical signal and transmitted to the other end. Here, when parallel-serial conversion is performed, as in the case of serial-parallel conversion, there is further editing processing and the like, and the function is performed by this bus control unit.

  The above-described serial-parallel conversion, parallel-serial conversion, and the editing / extraction processing associated therewith are performed by the same FPGA (Field Programmable Gate Array) as in the first embodiment in which a digital filter is implemented. As described above, the conventional transmission unit function is implemented in the bus control unit in the arithmetic processing unit, so that even in the case of a digital protection relay device that requires an information transmission function with the other end, no additional hardware is added. The digital protective relay device including the transmission unit can be reduced in size without passing through the system bus.

Embodiment 3 FIG.
In the first and second embodiments, the bus control unit 81 in the arithmetic processing unit 1 is realized by an LSI that can change detailed functions such as an FPGA (Field Programmable Gate Array). Filter processing and transmission processing functions can be changed, and A / D data only at its own end can be used by rewriting digital protection relay devices that require information on the other end or digital protection relay devices with corresponding functions. It will be possible. Further, even when the detailed specification of the transmission function is different, it can be realized by changing to the specification. Therefore, it can be configured by unified hardware regardless of the type of digital protection relay device, and mass production can be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the digital protection relay apparatus which is Embodiment 1 of this invention. It is a figure explaining the structure and operation | movement of an arithmetic processing part of FIG. It is a figure explaining the processing method of main CPU of the arithmetic processing part of FIG. 6 is a diagram illustrating a flow from self-end A / D data generation to saving of data after digital filtering according to Embodiment 1. FIG. FIG. 10 is a diagram for explaining a flow from serial data at the other end to saving of data after digital filtering in the second embodiment. It is a block diagram which shows the conventional digital protection relay apparatus. It is a figure explaining the processing method of the arithmetic processing part of the conventional digital protection relay apparatus. It is a figure explaining the flow from the conventional A / D data generation in the past to the save of the data after a digital filter. It is a figure explaining the structure and operation | movement of the conventional arithmetic processing part. It is a figure explaining the flow from the serial data of the other party in the past to the save of the data after a digital filter.

Explanation of symbols

1 Analog Input Unit 2 Arithmetic Processing Unit 3 Digital Output Unit 4 Digital Input Unit 5 Man-Machine I / F Unit 6 Transmission Unit 7 System Bus 8 Arithmetic Processing Unit 11 Analog Filter 12 Sample Hold Function 13 Multiplexer 14 A / D Converter 15 Bus Controller 16 Buffer 21 Memory unit 22 CPU
23 Internal bus 24 ROM
25 RAM 26 Data Save Memory 31 Digital Output 41 Digital Input 51 Man-Machine I / F 61 Memory Unit 62 CPU 63 Parallel-Serial Converter 64 Serial-Parallel Converter 65 Bus Controller 66 Internal Bus 68 Transmission Unit 81 Bus Control Unit 82 Counter end A / D data 83 Own end A / D data 84 Digital filter

Claims (3)

  An analog input unit to which the measured electrical quantity information of the system is input, a digital input unit to which the contact information of the circuit breaker is input, an arithmetic processing unit for determining a relay operation calculation based on output information from the analog input unit, a relay operation calculation In a digital protective relay device having a digital output unit for controlling a circuit breaker including a determination result and a man-machine I / F unit for setting and / or changing a set value for relay operation calculation determination, information transmission with each of the above units A digital protection relay device characterized in that a digital filter function is mounted on a bus control unit responsible for the bus function of the arithmetic processing unit.   An analog input unit to which the measured electrical quantity information of the system is input, a digital input unit to which the contact information of the circuit breaker is input, an arithmetic processing unit for determining a relay operation calculation based on output information from the analog input unit, a relay operation calculation In a digital protective relay device having a digital output unit for controlling a circuit breaker including a determination result and a man-machine I / F unit for setting and / or changing a set value for relay operation calculation determination, information transmission with each of the above units The bus control unit responsible for the bus function of the arithmetic processing unit is equipped with a digital filter function, and the bus control unit of the arithmetic processing unit is equipped with an information transmission function and an information editing function between the other end and the other end. A digital protective relay device.   3. The digital protection relay device according to claim 1, wherein the bus control unit of the arithmetic processing unit is configured by an LSI of an FPGA (Field Programmable Gate Array) capable of changing functions.

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