JP5839708B2 - Multiplexing control system - Google Patents

Description

  The present invention relates to a multiplexing control system, and more particularly to a multiplexing control system suitable for performing communication by switching a line.

  In a control system used for plant control or the like, communication related to control (hereinafter referred to as control communication) is performed between control devices. Specifically, for example, in a control system comprising an arithmetic device that is a control device that mainly executes various data calculations and an input / output device that is a control device that executes input / output by passing signals to the plant, between each control device Are connected by communication connection means to execute control communication.

  As a communication connection means in this case, a method of transmitting using a parallel signal cable or a serial signal cable is the mainstream. At present, however, many of the field buses in the market are composed of serial cables using various media in response to the demand for remote wiring that realizes high-speed and long-distance serial signals.

  On the other hand, when constructing a control system consisting of highly reliable multiplexing, the computing device and the input / output device are multiplexed, and the communication connection means for connecting them is also, for example, redundant in order to make the communication cable redundant. May be wired with heavy.

  Since the communication connection means may include a relay device in addition to the communication cable, when these communication cables are used, the relay device connected between the arithmetic device and the input / output device should be single or duplicated. As a result, many methods have been adopted for realizing duplex communication cables.

  As an application, I / O devices that have a relatively large number of boards are line duplex, but there are many cases where the device is handled as a form that increases the number of common parts. In this case, the configuration of line single and line duplex is used. Will be mixed on one control system.

  Specific examples in which single line and double line configurations are mixed on one control system include the following cases.

  For example, in a control system, monitoring is performed together with control. In the case of control, a signal detected on site is transmitted from the input / output device to the arithmetic device, and a control signal is sent from the arithmetic device to the input / output device, so this part includes the detector and the operation end. And On the other hand, the part that transmits the signal detected in the field for monitoring purposes from the input / output device to the arithmetic unit may not be required to be as reliable as the control system part, so it may have a single configuration. Many.

  Patent Document 1 shows a specific example in which configurations of single line and dual line are mixed on one control system.

Japanese Patent Laid-Open No. 4-28956

  In a mixed system in which a relay device is provided between an arithmetic device and an input / output device and they are connected from one line or two or more lines, the lines may be switched and operated. As this process, a system is known in which a node address is set in each device and communication is performed.

  For example, a node address is set by a switch or the like mounted for each device, a memory map is created based on configuration information obtained by communicating with a device to be accessed, a microcomputer is allocated to an area allocated for each device, and A method of judging and accessing by software is adopted.

  According to this method, two major problems occur. The first is that processing overhead is added due to the presence of software determination processing.

  Second, when the common part of the input / output device is configured with line duplex, the communication data when accessing the relay device configured with a single line reaches the input / output device at the timing of the input / output device. When the receiving circuit is in a data waiting state and a large amount of time-out occurs during the online operation, a problem occurs in terms of performance delay and ensuring timeliness of control.

  In view of the above, an object of the present invention is to provide a multiplexing control system that can smoothly perform line switching without delay in a multiplexing control system.

  As described above, in the present invention, the arithmetic device and the input / output device are connected via the multiplexed relay device, and the control signal is transmitted from the arithmetic device to the input / output device, and the input / output device according to the control signal. Transmitting a response signal to the arithmetic device, and the input / output device is a multiplexing control system configured to receive a control signal from both multiplexed relay devices and transmit the response signal. A dual-system mode for transmitting a control signal to both multiplexed relay apparatuses and a single-system mode for transmitting a control signal to one of the multiplexed relay apparatuses are designated, and the input / output apparatus is a multiplexed relay apparatus. When a control signal is received from one of these, a response signal is returned after a predetermined confirmation time, and the response signal is returned without waiting for the predetermined confirmation time by determining the one-system mode.

  According to the control system of the present invention, line switching can be smoothly performed without delay in a multiplex configuration control system.

The figure which shows the typical basic composition of a duplication control system. The figure which shows the conventional process flow showing operation | movement of an arithmetic unit. The time chart which shows the process of each part of the system by a conventional system. The figure which shows the processing flow of this invention showing operation | movement of an arithmetic unit. The figure which shows the address map of an arithmetic unit. The figure which shows the structure of the data format of a transmission frame. The figure explaining operation | movement of a transmission frame and a response frame. The figure which shows the structure of the transmission control part in an arithmetic unit. The figure which shows the structure in an input / output device. Configuration of Input / Output Control Circuit FIG. The flowchart which shows operation | movement of the input-output control circuit after data reception. The time chart which shows the process of each part of the system by this invention system. The figure which shows a conventional series of each part process at the time of transfer from an input / output device to a relay apparatus. The figure which shows a series of each process of this invention at the time of transfer from an input / output device to a relay apparatus.

  A mode for carrying out the present invention will be described with reference to the drawings.

  The present invention applies not only to the information equipment and information communication fields, but also inputs signals from sensors, etc. in large-scale power plant plants, etc., executes calculations, outputs command values to valves, etc., and performs real-time processing online. This is applied to the control method and operation method of the control system that is executed periodically while keeping the control cycle. In this embodiment, in order to satisfy the required performance when applying system redundancy to improve redundancy and availability by applying redundancy by using a redundant configuration of arithmetic devices and applying field duplex to the fieldbus. This method is proposed.

  FIG. 1 is a basic configuration diagram of a typical duplex control system to which the present invention is applied.

  The duplex control system in FIG. 1 inputs / outputs data from a control target 30 and gives signals to the control target, input / output devices 22, 23, and 24, arithmetic units 10 and 11 that execute predetermined calculations, It is comprised by the relay apparatuses 16 and 18 which connect. In order to improve reliability, this system is realized by a duplex configuration in which a plurality of arithmetic devices 10 and 11 and relay devices 16 and 18 are installed and coupled.

  In FIG. 1, the arithmetic unit has a dual configuration of a main arithmetic unit 10 and a subordinate arithmetic unit 11. From the main processor 10, an A-system communication line 12A and a B-system communication line 12B are connected to the relay apparatus 16A and the relay apparatus 16B, respectively. Similarly, the A-system communication line 14A and the B-system communication line 14B are connected to the relay apparatus 16A and the relay apparatus 16B from the slave arithmetic unit 11, respectively.

  The relay device 16A and the relay device 16B transmit and receive signals to and from the next-stage relay device, and the illustrated relay device 18A and relay device 18B are the last-stage relay devices on the control target 30 side. As is apparent from the figure, the A-system relay devices 16A and 18A and the B-system relay devices 16B and 18B are independent of each other.

  A plurality of input / output devices 22, 23, and 24 serving as an interface with the control target 30 are mounted in an appropriate housing, connected to the upper arithmetic devices 10 and 11 via the relay devices 16 and 18, and communicated. Done.

  The input / output devices 22, 23, and 24 are connected to a control device 27 such as a valve and a sensor that are controlled objects 30. Inside the input / output devices 22, 23, and 24, conversion of analog signals and digital signals, and noise In order to improve tolerance, internal and external signals, power supply insulation, etc. are performed.

  The input / output devices 22 and 23 are connected to the relay device 18A via the A-system communication line 20A, and the input / output devices 22, 23 and 24 are connected to the relay device 18B via the B-system communication line 20B.

  As a result, the input / output devices 22 and 23 are connected to the higher-level relay devices 18A and 18B via the communication lines 20A and 20B with the duplicated lines, and the relay devices 16 and 18 are arranged in units. ing. On the other hand, the input / output device 24 connected to the relay device 18B via the B-system communication line 20B is single line communication.

  Note that the relay device 16A and the relay device 18A, and the relay device 16B and the relay device 18B are connected by a communication cable or the like, respectively, so that an abnormality in one system does not propagate to other system paths. The A-system communication line 20A and the B-system communication line 20B are connected by a cable or a wiring board. In order to match the impedance of the transmission line, the termination device 25 is mounted on the terminal of the relay device 18.

  Note that power is supplied from the power supply device 26 to the illustrated relay devices 16 and 18 and the input / output devices 22, 23, and 24.

  Next, in the system of FIG. 1, an operation when the calculation result of the calculation device is output to the control target 30 will be described. The main processor 10 transmits data to the relay devices 16A and 16B via the A-system communication line 12A and the B-system communication line 12B. Address information to be accessed is added to the data. This communication data is transmitted to the input / output devices 22, 23, 24 through the relay devices 16A, 16B and the relay devices 18A, 18B.

  The input / output devices 22, 23, and 24 to be accessed receive communication data from the A-system communication line 20 A and the B-system communication line 20 B, and after selecting those data depending on whether or not they are designated addresses When the address is the designated address, conversion from serial data to parallel data is performed. The converted parallel data is output from the input / output devices 22, 23, 24 to the control device 27 such as a valve or a sensor that is the control target 30.

  On the other hand, the secondary arithmetic unit 11 having a duplex configuration is in a standby operation. However, the subordinate arithmetic unit 11 includes a signal on the control target 30 side obtained by the main arithmetic unit 10 via the A-system communication line 12A and the B-system communication line 12B, or the main arithmetic unit 10 receives the A-system communication line. The control signals of the control target 30 given to the 12A and B system communication lines 12B are all given in the same way.

  The subordinate arithmetic unit 11 obtains the same signal as that of the main arithmetic unit 10 and normally monitors the data from the main arithmetic unit 10. If the main arithmetic unit 10 fails, the control data is transferred to the subordinate arithmetic unit 11, and the subordinate arithmetic unit 11 continues to control instead of the main arithmetic unit 10.

  Advantages of the control system according to the present invention shown in FIG. 1 will be described below. First, as an example in the case where the main processing unit 10 is a control system, communication data is transmitted to the input / output device via a duplexed communication line and relay device for each system. In this system, data is output to both systems at the same time, so if one system relay device failure or cable disconnection occurs, the data can be transmitted to the I / O device in one system, which improves the availability. There is.

  Another advantage of the present system configuration is that the relay device is separated in units of lines, and even if the power is cut off or disconnected, the influence on other systems can be minimized.

  By the way, in such a control system, in order to ensure the line quality state of the communication path, RAS information stored in each relay device is collected and monitored, thereby facilitating maintenance work such as notification and replacement to maintenance personnel. It is possible to make it. In this case, since the RAS information is stored in the relay device, it is necessary to collect the RAS information for each relay device for each line device.

  In the system configuration of FIG. 1, operations and problems when collecting RAS information held by the relay apparatus will be described.

  In order to collect RAS information of the relay device, the main processing unit 10 makes a transition to a state where it can be accessed by a single system line so that data transmission / reception using the A system communication line 12A can be performed. In the normal operation of transmitting / receiving control signals to / from the input / output device, data is sent to both lines, and the transmission and reception operations are repeated.

  Therefore, as the line operation mode, switching between both system operations at the time of control signal transmission and one system operation for collecting RAS information occurs during the online operation. In order to enable such switching, the mode switching setting is performed by setting by software such as a μ processor. As a result, the overhead time required for mode switching is periodically added to the online processing time, resulting in a decrease in performance of the arithmetic device.

  A processing flow showing the operation of the arithmetic unit at this time is shown in FIG. In process S1 of FIG. 2, data is written to the memory of the relay device by software processing, and then the mode is changed from line duplex to line single operation (process S2), and response data is waited (process S3).

  FIG. 3 shows a time chart showing processing of each part of the system at this time. FIG. 3 illustrates the operation of the input / output device 22 when the main processor 10 transmits a frame to the relay device 16A in order to collect RAS information from the relay device 16A.

  In this case, since it is assumed that frame transmission is performed using a single-system line using only the A-system communication line 12A, the frame is transmitted to the relay apparatus 16A via the A-system communication line 10A of the main processor 10. Transmission (100) is performed. The relay device 16A receives (101) the frame. Further, since the relay device 16A transfers the received frame to the input / output device side, the input / output device 22 recognizes the reception of the frame from the A system.

  On the other hand, since no frame is transmitted to the B-system communication line 12B, the transmission frame does not reach the relay device 16B to which the B-system communication line 12B is connected (102). Therefore, the relay device 16B does not transfer the received frame to the input / output device side.

  In the input / output device 22 to which both lines are connected, only the transmission frame transmitted using the A-system communication line is received by the input / output device 22. The input / output device 22 shifts to the data waiting state of the B-system communication line at the timing t1 when the transmission frame received from the A-system communication line 12A is captured. At the same time, a B time-out (hereinafter referred to as T.O) counter is started (104), data is received when data is received before the time is up, and when time is up, the reception time-out T.O. Report the occurrence of O to the top (105).

  The report frame from the input / output device 22 passes through the intermediate relay devices 12A and 12B. During this return processing, the relay device 16A adds the RAS information in the frame and sends it to the computing device side, so that the computing device 10 achieves the initial purpose of obtaining the RAS information.

  According to this method, RAS information can be collected, but communication (105) occurs with a timeout occurring each time. Since a timer is started every time data is received through the A-system communication line, a timeout occurs in frame units. As a result, the A-system data capture time is prolonged, and the data output to the controlled object 30 or the data input is delayed, so that the performance of the entire system is degraded.

  Therefore, in the method of the present invention, the line state mode switching periodically performed by the main processor 10 is performed as shown in the processing flow of the processor in FIG. Here, data writing (processing S1) is performed to the memory of the relay device by software processing, and response data is waited (processing S3). The part corresponding to the process S2 in FIG. 2 is not implemented in software.

  In this regard, the main processing unit 10 determines whether the frame transmission target is a relay device to which a one-system communication line is connected or an input / output device to which both system communication lines are connected without depending on software. To automatically switch the operation mode and transmit data. According to the operation shown in this flow, it is possible to improve performance degradation due to mode switching by the software processing method of FIG.

  Hereinafter, means for realizing the present invention will be described in detail. First, FIG. 5 is an address map of each device targeted for the relay device and the input / output device, as viewed from within the arithmetic device. The configuration of the address map includes a space (A-system communication space) 50 of a module (typically a relay device) connected to an A-system communication line, a space (B-system communication space) 51 of a module connected to a B-system communication line, It is composed of a module space (A, B communication space) 52 connected to both the A system and B system lines. Relay devices 16A and 18A are defined in the A-system communication space 50, relay devices 16B and 18B are defined in the B-system communication space 51, and input / output devices 22, 23, and 24 are defined in the A- and B-system communication spaces 52. Defined.

In the configuration shown in FIG. 1, the input / output devices 22 and 23 are connected to both the A system and the B system, but the input / output device 24 is connected only to the B system. From this point of view, the input / output device 24 seems to be defined in the B-system communication space 51, but what is desired to be implemented in the present invention is the distinction between normal communication and RAS information collection communication. For this reason, it is divided into a relay device (RAS information collection communication) and an input / output device (normal communication), and further, the relay device is separated and defined for each communication system connected.
As described above, in the present invention, the access space of the device connected to the one-system communication line and the access space of the device connected to the two-system communication line are divided, and the communication operation assigned to each space is divided into area units. And defining it.

  In this embodiment, the operation of the communication line performs memory transfer, and a case where the communication operation is performed between the arithmetic device and the relay device or between the arithmetic device and the input / output device will be described below.

  For example, when the main processing unit 10 transmits a frame to the relay device 16A via the A-system communication line 12A, the software of the main processing unit 10 is stored in the main storage device (memory) according to a command from the microprocessor. Data is written in the area of the space 50 shown in FIG. The arithmetic device 10 converts the written data into serial data for transmission from the A-system communication line 16A, and transmits the serial data to the relay device 16A.

  On the other hand, when transmitting to the input / output device 22, the software writes data to the area of the input / output device 22 in the space 52 of FIG. The arithmetic unit 10 converts the written data into serial data in the same manner, and transmits the data to the A-system and B-system communication lines 16A and 16B.

  As described above, the communication operation is determined by the areas (50, 51, 52) defined in the address map 53 of FIG. 5, and is operated without setting such as mode switching.

  It should be noted that the physical address of the address map 53 may be fixed or arbitrary, but the arithmetic unit constructs and determines the memory map based on the configuration information obtained from the device at the time of start-up. Many forms are adopted. The address for each device is determined by a switch or the like set for each device, and the setting information and the memory address must be associated with each other. In the present embodiment, there is no mention of means for determining correspondence between these addresses and the memory map.

  FIG. 6 shows a configuration of a data format 60 of a transmission frame FS of serial data transmitted from the arithmetic device.

  This data format consists of a preamble P, a flag F, a transmission destination address SA, a transmission source address RA, data DT, and CRC from the head. When transmitted from the arithmetic device, the source address RA is set as the address of the arithmetic device, and the destination address SA is set differently depending on whether the destination is a relay device or an input / output device. The field of the destination address SA on the format is related to the address map of FIG. 5, and when transmitting data in the A-system module space 50, an address corresponding to the area 50 is added to the destination address SA. Has been generated.

  FIG. 7 illustrates operations of the transmission frame FS and the response frame FR. The transmission frame FS transmitted from the arithmetic device 10 is received by the input / output device 22 via the relay device 16A, and the device whose transmission address matches returns the response frame FR to the arithmetic device 10. The data format 60 of the transmission frame FS and the response frame FR is configured as shown in FIG.

  FIG. 8 shows a configuration of the transmission control unit 70 in the arithmetic device. This configuration is for the A-system communication line 12A for transmitting transmission data stored in the memory of FIG. 5 to the A-system relay apparatus 16A and the B-system communication line 12B for transmitting to the B-system relay apparatus 162B. , An internal block for transmitting.

  The transmission control unit 70 includes a buffer 71 that temporarily stores data from the memory, a parallel-serial conversion block 72 that converts parallel data into serial data, an address determination unit 73, an A-system data selection unit 74, and a B-system data selection unit 75. , An A-system transmission circuit 76 and a B-system transmission circuit 77.

  The transmission data stored in the buffer 71 is sent to the parallel / serial conversion unit 72. At the same time, the address determination unit 73 monitors the addresses in the memory and determines the areas (50, 51, 52) of the address map 53 in FIG.

  Based on the transmission areas (50, 51, 52) determined by the address determination unit 73, the parallel-serial conversion unit 72 generates a portion corresponding to the transmission destination address SA of the transmission frame FS. The address determination unit 73 determines whether to use a single-system communication line or a dual-system communication line, and outputs a command to the A-system data selection unit 74 and the B-system data selection unit.

  If the data address is within one system communication module, for example, the data address in the space 50 of FIG. 5, the frame is transmitted only from the A system transmission circuit 76. If the data address is in the space 52, the A system transmission circuit 76 and the B system transmission are transmitted. Frames are transmitted from both circuits 77.

  By using the means described above, it is possible to prevent the transmission control unit 70 from degrading performance during transmission frame transmission on the arithmetic device side without periodically performing online mode switching by software.

  Next, the configuration within the input / output device will be described. First, FIG. 9 shows the overall configuration of 22 as an example of the input / output device. When data is received from both the A system communication line 20A and the B system communication line 20B, timeout monitoring and data conversion are performed in the input / output control circuit 82 via the A system reception circuit 80 and the B system reception circuit 81. After being performed, data is output to the control target 30.

  Among these, the configuration of the input / output control circuit 82 is shown in FIG. The input / output control circuit 82 includes a timeout determination circuit 84, a data line control circuit 85, and a parallel / serial conversion unit 86.

  FIG. 11 is a flowchart showing the operation of the input / output control circuit 82 after data reception. In the flowchart of FIG. 11, an example in which a frame is transmitted from the arithmetic device to the relay device using the A-system communication line is given.

  First, when data is received from the A-system communication line 12 (process S20), the timeout determination circuit 84 performs a destination address comparison (process S21). The time-out determination 84 is based on the information set by the switch 83 for setting the type of the own device, and when it matches with the transmission destination address SA of the transmission frame corresponding to the address of the space 50 in the figure (processing S22), It is determined that the transmission destination is a relay device, and a reception timeout suppression instruction is output to the data line control circuit 85 (processing S23).

  Thereafter, the received data is fetched (step S24). If no match is determined in step S22, the received data is fetched in step S24 without executing step S23.

  The data line control circuit 85 transmits the received frame FS from the A-system communication line 12 to the parallel-serial conversion unit 86, and the conversion unit 86 outputs it to the control target.

  According to the present embodiment, when a frame to a one-system communication line for a relay device is received, the timeout is suppressed when the frame is received, and the data capture time is minimized so that the data is received and output to the control target. The effect of improving the response performance up to is obtained.

  On the other hand, for the transmission address to the input / output device, the timeout determination circuit 84 functions as valid without suppressing the timeout. Therefore, the timer is started after receiving the data from the A-system communication circuit 12, and the B-system Waiting for data received from the communication line 13.

  As described above, the switching overhead is optimized by dynamically switching whether the timeout on the receiving side is valid or invalid depending on the type of the transmission address.

  FIG. 12 shows a time chart showing processing of each part of the system in the present invention. FIG. 12 shows the operation of the input / output device 22 when the main processor 10 transmits a frame to the relay device 16A in order to collect RAS information from the relay device 16A.

  In this case, since it is assumed that frame transmission is performed using a single-system line using only the A-system communication line 12A, the frame is transmitted to the relay apparatus 16A via the A-system communication line 10A of the main processor 10. Transmission (100) is performed. The relay device 16A receives (101) the frame. Further, since the relay device 16A transfers the received frame to the input / output device side, the input / output device 22 recognizes the reception of the frame from the A system.

  On the other hand, since no frame is transmitted to the B-system communication line 12B, the transmission frame does not reach the relay device 16B to which the B-system communication line 12B is connected (102). Therefore, the relay device 16B does not transfer the received frame to the input / output device side.

  In the input / output device 22 to which both lines are connected, only the transmission frame transmitted using the A-system communication line is received by the input / output device 22.

  The operation so far is the same as that in FIG. 3, but in the case of the present invention, when the input / output device 22 determines that it matches the transmission destination address SA of the transmission frame corresponding to the address of the space 50 in FIG. It is determined that the destination is a relay device, and instructs the data line control circuit 85 to suppress reception timeout. Therefore, the input / output device 22 returns a response frame at its own timing without waiting for the B system timeout (106).

  The report frame from the input / output device 22 passes through the intermediate relay devices 12A and 12B. During this return processing, the relay device 16A adds the RAS information in the frame and sends it to the computing device side, so that the computing device 10 achieves the initial purpose of obtaining the RAS information.

  FIG. 13 and FIG. 14 show a series of processing when shifting from normal communication for the input / output device to normal communication for the relay device, FIG. 13 shows conventional processing, and FIG. 14 shows processing of the present invention. .

  Briefly describing this series of processing, in normal communication with the input / output device, the arithmetic device 10 transmits frames of the same content to the relay devices 16A and 16B of each system (201). This communication is line duplex communication. The frame is transmitted to the input terminal of each system of the input / output device 22 via the relay apparatuses 16A and 16B of each system (202). The input / output device 22 receives the same signal from both systems at the same time, determines that it is normally received, and starts the subsequent return operation.

  It is assumed that the normal communication with the relay device is shifted to at the next timing. In the conventional case of FIG. 13, the frame is transmitted to the relay device 16A (203), but the frame is not transmitted to the relay device 16B (204).

  Since the input / output device 22 is a dual-system line, it shifts to a B-system reception waiting state at the timing of receiving a frame from the A-system (205). However, there is no reception from the B system, and timeout counting starts. Thereafter, a timeout is notified (206).

  The arithmetic device 10 receives the timeout of the B line and obtains the RAS information added by the relay device 16A (207). However, with this method, a delay due to timeout occurs every time communication is started from the arithmetic device, leading to a decrease in the performance of the entire system.

  In the case of the present invention shown in FIG. 14, since the normal communication for the input / output device and the normal communication for the relay device are exactly the same, the description thereof is omitted. Since the operation after the one-system reception of the input / output device 22 is different, the following will be described.

  In the input / output device 22, in order to instruct the data line control circuit 85 to suppress the reception timeout, the input / output device 22 returns a response frame at its own timing without waiting for the B system timeout (209). In this case, since time-out is prevented, information can be collected without delay.

  According to the method of the present invention, even when the frame transmission to the A-system communication line is performed to the relay device, the input / output device side prevents the performance degradation of the entire system without causing a timeout for each received frame. It is said.

10: Main processing unit 11: Subordinate processing unit 12A: A system communication line 12B: B system communication line 16A: A system relay device 16B: B system relay device 14A: A system communication line 14B: B system communication line 18A: A system relay device 18B: B system relay device 16A: A system relay device 16B: B system relay devices 22, 23, 24: Input / output device 30: Control target

Claims (5)

A relay device in which an arithmetic device and an input / output device are connected via a multiplexed first communication line, a multiplexed relay device, and a multiplexed second communication line, and multiplexed from the arithmetic device A control signal is transmitted to the input / output device via a relay, and a response signal is transmitted from the input / output device to the arithmetic device via a relay device multiplexed according to the control signal. A multiplexing control system configured to receive the control signal from both of the multiplexed relay devices and transmit the response signal;
The arithmetic device designates a both-system mode for transmitting a control signal to both of the multiplexed relay devices and a one-system mode for transmitting a control signal to one of the multiplexed relay devices,
The input / output device determines the two-system mode when receiving a control signal from one of the multiplexed relay devices, returns a response signal after a predetermined confirmation time, and determines the one-system mode. A response signal is returned without waiting for the predetermined confirmation time,
The relay apparatus, when the control signal is addressed to itself, includes information on the relay apparatus in the response signal from the input / output apparatus and transmits the information to the arithmetic apparatus. . The multiplexing control system according to claim 1,
The arithmetic device stores in a memory both system modules that define a device that performs transmission in both systems mode and a single system module that defines a device that performs transmission in one system mode, and the control signal A multiplexing control system characterized in that information on both-system mode or one-system mode is transmitted by being superimposed on the transmission signal with reference to the memory during transmission. A multiplexing control system according to claim 2, comprising:
The multiplexing control system is characterized in that the input / output device is divided into the two-system modules, and the relay device is divided into the one-system module. A multiplexing control system according to any one of claims 1 to 3 , wherein
A multiplexing control system characterized in that processing for designating both system mode and one system mode is executed by hardware. The multiplexing control system according to any one of claims 2 to 4, wherein
Multiplexing characterized in that when the input / output device is connected to only one of the multiplexed relay devices, the input / output device does not have the confirmation time and is defined in the modules of both systems Control system.

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