JP4283656B2 - Manufacturing method of semiconductor device, semiconductor device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a package by which a chip can be thinned remarkably without a back grinding treatment resulting in a crack and a grinding trace, the chip can be manufactured at a lower cost in a higher throughput and the dispersion of the thickness of the chip can be inhibited; and to provide its manufacturing method. <P>SOLUTION: A semiconductor film as a thin-film having a film thickness of &le;500 nm formed on a substrate functioning as a supporter is crystallized by a laser beam in continuous oscillation, and the chip with a semiconductor element as the thin-film of the total film thickness of 5&mu;m, more desirably &le;2&mu;m is formed by using the crystallized semiconductor film. The chip is mounted on an interposer under the state in which the substrate is peeled finally. <P>COPYRIGHT: (C)2004,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor device (package) such as a CSP (Chip Size Package) or MCP (Multi Chip Package) on which a chip on which an integrated circuit (IC) is formed is mounted, and a method for manufacturing the semiconductor device. Related to the electronic equipment.

  Portable electronic devices such as mobile phones and electronic notebooks are required to have various functions such as sending and receiving e-mails, voice recognition, and video capture with a small camera, but there are also user needs for downsizing and weight reduction. Still strong. Therefore, it is necessary to mount more chips with larger circuit scale and memory capacity in the limited volume of portable electronic devices.

  Therefore, CSP (Chip Size Package), which is a kind of package, has attracted attention as a technology for mounting a chip in which an IC is built on a printed wiring board. The CSP can be as small and light as a bare chip. In addition, unlike bare chips, it does not require equipment or technology such as a clean room or special bonder when mounting a chip supplied by a packaging manufacturer on the electronic device manufacturer side, and is suitable for standardization. The CSP also protects the chip from the external environment, a general-purpose function that can standardize the footprint of the printed wiring board, and expands the wiring of the sub-micron scale chip to the same millimeter scale as the printed wiring board. It also has the advantageous functions of a package that is not available in bare chips, such as a scale conversion function, which has become an indispensable element technology for electronic device manufacturers to achieve downsizing and weight reduction.

  In order to realize further miniaturization and weight reduction of the CSP, it is recognized as a problem that the chip mounted on the CSP is thin. For example, the following Non-Patent Document 1 describes that a chip thickness of 50 μm or less is a target value at present.

SEMICON Japan 2002, Dec. 5, 2002, Sponsored by SEMI Japan, Technical programs for the semiconductor equipment and materials industries, Current status of thin chip (die) mounting ~ Prospect to below 50μm, Fujitsu Limited Noboru Hayasaka “Standardization examples and future Items to be standardized "p1 to p8

  Generally, a series of manufacturing steps of a chip mounted on a package represented by a CSP includes a step of performing a polishing process called back grinding on the back surface of a silicon wafer on which a semiconductor element to be a chip later is formed. Is provided. By this polishing treatment, the chip is thinned, and the package can be reduced in size and weight.

  However, this back grinding process leaves a polishing mark with a depth of about several tens of nanometers on the back surface of the silicon wafer, which is a cause of lowering the mechanical strength of the chip. Sometimes a crack is formed in addition to the polishing mark. Cracks can have a depth of several μm and sometimes as much as 20 μm. Both of these polishing marks and cracks cause chip breakage in a later process, and this problem is becoming more serious as the chip becomes thinner.

  In order to deal with this problem, there is a case where a process called stress relief is added after the back grinding process. The stress relief is a process for flattening the back surface of the silicon wafer. Specifically, plasma etching, wet etching, dry polishing or the like is performed. However, the stress relief described above is effective for removing polishing marks having a depth of about several tens of nanometers, but it has only one effect on cracks ranging from several μm to 20 μm, and the stress relief is increased as the cracks disappear. If this is performed, the processing time becomes long, and the throughput in the chip manufacturing process is lowered, which is not preferable.

  Further, when the back grinding process is performed on the back surface, it is necessary to protect the element by attaching a tape or a substrate to the surface on which the element of the silicon wafer is formed. Therefore, the control of the thickness of the silicon wafer in the back grinding process is actually controlled by the total thickness of the silicon wafer and the tape or substrate attached for protection. Therefore, if the protective tape or the substrate is bent or the thickness thereof is not uniform, unevenness of about several μm to several tens of μm occurs in the thickness of the polished silicon wafer. Since the thickness of the silicon wafer affects the characteristics of the manufactured chip, if the thickness varies, there arises a problem that the characteristics of the chip vary.

  Furthermore, silicon wafers have a higher unit price than glass substrates and the size of silicon wafers that are relatively distributed in the market is about 12 inches in diameter at most. Although silicon wafers having a size larger than 12 inches are on the market, the price per unit area further increases as the size increases, and is not suitable for providing inexpensive chips. However, since the number of chips produced from one silicon wafer is limited, it is difficult to increase the throughput of a silicon wafer having a diameter of about 12 inches, which is not suitable for mass production.

  In view of the above-mentioned problems, the present invention is capable of (i) dramatically reducing the thickness of the chip without performing back grind processing that causes cracks and polishing marks. It is an object of the present invention to provide a package and a manufacturing method thereof, in which a chip can be manufactured with high throughput and (c) variation in chip thickness can be suppressed. Another object is to provide an electronic device in which the package is mounted.

  In the present invention, a thin semiconductor film having a thickness of 500 nm or less formed on a substrate functioning as a support is crystallized with continuous wave laser light, and the total film thickness is obtained using the crystallized semiconductor film. A chip having a thin film semiconductor element of 5 μm, more preferably 2 μm or less is formed. The chip is mounted on an interposer with the substrate finally peeled off.

  Specifically, a metal film is formed on the first substrate, and a thin metal oxide film of several nm is formed by oxidizing the surface of the metal. Next, an insulating film and a semiconductor film are sequentially stacked on the metal oxide film. Then, the semiconductor film is crystallized with continuous wave laser light, and a semiconductor element is manufactured using the crystallized semiconductor film. Next, when a semiconductor element is formed, a second substrate is attached so as to cover the element, and the semiconductor element is sandwiched between the first substrate and the second substrate.

  Then, a third substrate is bonded to the side of the first substrate opposite to the side where the semiconductor element is formed in order to reinforce the rigidity of the first substrate. When the first substrate is higher in rigidity than the second substrate, the semiconductor element is less likely to be damaged when the first substrate is peeled off, and can be removed smoothly. Note that the third substrate is not necessarily bonded to the first substrate if the first substrate has sufficient rigidity when the first substrate is peeled off from the semiconductor element later.

  Next, heat treatment or the like is performed to crystallize the metal oxide film, increase brittleness, and facilitate separation of the substrate from the semiconductor element. Then, the first substrate is peeled off from the semiconductor element together with the third substrate. Note that the heat treatment for crystallizing the metal oxide film may be performed before the third substrate is bonded, or may be performed before the second substrate is bonded. Alternatively, the heat treatment performed in the step of forming the semiconductor element may also serve as the step of crystallizing the metal oxide film.

  By this peeling, a portion that is separated between the metal film and the metal oxide film, a portion that is separated between the insulating film and the metal oxide film, and a portion where the metal oxide film itself is separated into both are generated. In any case, the semiconductor element is peeled off from the first substrate so as to stick to the second substrate side.

  Then, after peeling off the first substrate, the semiconductor element is mounted on the interposer, and the second substrate is peeled off. Note that the second substrate is not necessarily peeled off. For example, if the mechanical strength is emphasized rather than the thickness of the chip, the second substrate may be completed while being attached to the chip.

  Further, the electrical connection (bonding) between the interposer and the chip may be performed using a flip chip method or a wire bonding method. When the flip chip method is used, bonding is performed simultaneously with mounting to the interposer. When the wire bonding method is used, the bonding process is performed after the chip is mounted and the second substrate is peeled off.

  When a plurality of chips are formed on one substrate, dicing is performed in the middle so that the chips are separated from each other. The dicing step is performed by inserting between any steps after forming the semiconductor element. Desirably, (a) before mounting after peeling the first substrate, (b) after mounting, before peeling the second substrate, and (c) at any timing after peeling the second substrate. Good to do.

  In the present invention, an MCP may be formed by mounting a plurality of chips on the same interposer. Also in this case, an electric wire bonding method between chips may be used, or a flip chip method may be used.

  The interposer may be of a type that makes electrical connection with the printed wiring board using a lead frame, may be a type that uses bumps, or may have a known form.

  Furthermore, in the present invention, one chip is formed in the crystallized region by using two laser beams and scanning the two laser beams in one direction. The two laser beams are referred to as a first laser beam and a second laser beam, respectively. Specifically, the first laser beam has a wavelength (approximately 780 nm or less) that is approximately the same as or shorter than that of visible light.

A semiconductor film crystallized using only pulsed laser light is formed by aggregating a plurality of crystal grains, and the positions and sizes of the crystal grains are random. Compared with the inside of a crystal grain, the interface (crystal grain boundary) of a crystal grain has innumerable recombination centers and trap centers due to an amorphous structure or crystal defects. When carriers are trapped in this trapping center, the potential of the crystal grain boundaries is increased, which becomes a barrier against the carriers, so that there is a problem that the current transport characteristics of the carriers are deteriorated. On the other hand, in the case of a continuous wave laser beam, a crystal is continuously grown in the scanning direction by irradiating the semiconductor film while scanning the irradiation region (beam spot) of the laser beam in one direction. A collection of crystal grains made of a single crystal extending along the length can be formed. However, continuous wave laser light has a lower output energy of laser light per unit time than pulsed laser, and it is difficult to increase the beam spot area and increase throughput. Furthermore, when crystallizing a silicon film of several tens to several hundreds of nanometers normally used for a semiconductor device with a YAG laser or a YVO ₄ laser, the second harmonic having a shorter wavelength than the fundamental wave has a higher absorption coefficient, Crystallization can be performed efficiently. However, since the nonlinear optical element that converts to harmonics is extremely low in resistance to laser light, for example, a continuous wave YAG laser can output a fundamental wave of 10 kW, whereas an output energy of the second harmonic is only about 10 W. I can't. For example, in the case of an Nd: YAG laser, the conversion efficiency from the fundamental wave (wavelength: 1064 nm) to the second harmonic (wavelength: 532 nm) is around 50%. Therefore, in order to obtain the energy density necessary for crystallization of the semiconductor film, the area of the beam spot must be reduced to about 10 ⁻³ mm ^2, which is inferior to the pulse oscillation in terms of throughput.

In the present invention, the region that is melted by the first laser beam of the harmonic pulse oscillation is irradiated with the second laser beam of continuous oscillation. Therefore, by melting the semiconductor film with the first laser light, the absorption coefficient of the second laser light into the semiconductor film is dramatically increased, and the second laser light is easily absorbed into the semiconductor film. FIG. 8A shows the value of the absorption coefficient (cm ⁻¹ ) of the amorphous silicon film (amorphous silicon) with respect to the wavelength (nm) of the laser beam. FIG. 8B shows the value of the absorption coefficient (cm ⁻¹ ) of the polycrystalline silicon film (amorphous silicon) with respect to the wavelength (nm) of the laser beam. The measurement was obtained from the extinction coefficient obtained with a spectroscopic ellipsometer. From FIGS. 8A and 8B, it is considered that when the absorption coefficient is 1 × 10 ⁴ cm ⁻¹ or more, the semiconductor film can be sufficiently melted by the first laser beam. In order to obtain an absorption coefficient in this numerical range, in the case of an amorphous silicon film, it is considered that the wavelength of the first laser beam is preferably 780 nm or less. Note that the relationship between the wavelength of the first laser beam and the absorption coefficient varies depending on the material of the semiconductor film, crystallinity, and the like. Therefore, the wavelength of the first laser beam is not limited to this, and the wavelength of the first laser beam may be set as appropriate so that the absorption coefficient is 1 × 10 ⁴ cm ⁻¹ or more. Then, the portion melted by the first laser light moves in the semiconductor film while being maintained in the molten state by the irradiation of the second laser light that is continuous oscillation, so that it continuously grows in the scanning direction. A collection of crystal grains can be formed.

  The time during which the molten state can be maintained is determined by the balance between the output of the pulsed laser and the continuous wave laser. If the semiconductor film is irradiated with the next pulsed laser within a time during which the molten state can be maintained, annealing of the semiconductor film can be continued while the molten state is maintained. In an extreme case, once the semiconductor film is melted with a pulse laser, there may be a condition in which the molten state can be maintained only by irradiation with the fundamental wave. In this case, it is only necessary to irradiate only one shot of the pulse laser and then maintain the molten state with a continuous wave laser.

  Since higher harmonics have lower energy, the first laser beam is most preferably the second harmonic when the wavelength of the fundamental wave is about 1 μm. However, the present invention is not limited to this, and the first laser beam only needs to have a wavelength of visible light or less. In the second laser beam, for the purpose of assisting energy with respect to the first laser beam, the output power output is more important than the absorption coefficient to the semiconductor film. Therefore, it is most desirable to use a fundamental wave as the second laser light. However, the present invention is not limited to this, and the second laser beam may be a fundamental wave or a harmonic wave.

  When the fundamental wave is used for the second laser light, it is not necessary to convert the wavelength, and thus it is not necessary to suppress energy in consideration of deterioration of the nonlinear optical element. For example, the second laser beam can have an output that is 100 times or more (for example, an output of 1000 W or more) compared to a continuous-wave laser of visible light or less. Therefore, the complexity of the maintenance of the nonlinear optical element can be eliminated, the total energy of the laser light absorbed by the semiconductor film can be increased, and a crystal having a larger particle diameter can be obtained.

  In pulse oscillation, the energy of the oscillated laser light per unit time is higher than in continuous oscillation. Moreover, in the harmonic and the fundamental wave, the energy of the harmonic is lower, and the energy of the fundamental wave is higher. In the present invention, a laser beam having a wavelength of harmonics or less than visible light is pulsed oscillation, and the fundamental laser beam is continuously oscillated. Compared to a configuration in which the oscillation is continuous and the fundamental wave is pulse oscillation, the size of the area where the harmonic beam spot and the fundamental beam spot overlap each other can be secured. Can be dramatically reduced.

The first laser light is pulsed Ar laser, Kr laser, excimer laser, CO ₂ laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, Alexandride laser, Ti: sapphire laser, copper vapor laser or gold vapor laser can be used.

The second laser beam is a continuous wave Ar laser, Kr laser, CO ₂ laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, alexandride laser, Ti: sapphire laser or It can be obtained by using a helium cadmium laser.

  For example, the overlap of two beam spots formed by two lasers will be described by taking a continuous wave YAG laser and a pulsed excimer laser as examples.

  FIG. 3A shows a state in which a beam spot 10 of a continuous wave YAG laser having a fundamental wave and a beam spot 11 of a continuous wave YAG laser having a second harmonic are superimposed. The fundamental YAG laser can obtain an output energy of about 10 kW, and the second harmonic YAG laser can obtain an output energy of about 10 W.

Assuming that 100% of the energy of the laser beam is absorbed by the semiconductor film, the crystallinity of the semiconductor film is improved by setting the energy density of each laser beam to 0.01 to 100 MW / cm ^2. Can do. Therefore, here, the energy density is 1 MW / cm ² .

The shape of the beam spot 10 of a continuous wave YAG laser having a fundamental wave is assumed to be rectangular, the length in the minor axis direction is L _X1 , and the length in the major axis direction is L _Y1. Therefore, L _X1 is set to 20 μm to 100 μm. For example, when L _X1 = 20 μm, L _Y1 = about 50 mm, when L _X1 = 30 μm, L _Y1 = about 30 mm, and L _X1 = 100 μm. _It is appropriate that _Y1 = about 10 mm. That is, in this case, L _Y1 is an appropriate value for obtaining better crystallinity between 10 mm and 50 mm.

Further, assuming that the shape of the beam spot 11 of a continuous wave YAG laser having harmonics is rectangular, the length in the short axis direction is L _X2 , and the length in the long axis direction is L _Y2 , the above energy density is satisfied. For this purpose, L _X2 is 20 μm to 100 μm. For example, when L _X2 = 10 μm, L _Y2 = 100 μm is appropriate.

  The area of the region where the beam spot 10 of the continuous wave YAG laser having the fundamental wave overlaps with the beam spot 11 of the continuous wave YAG laser having the second harmonic wave is such that the beam spot 11 completely overlaps the beam spot 10. It is equivalent to the area of the beam spot 11.

Next, FIG. 3B shows a state where a beam spot 10 of a continuous wave YAG laser having a fundamental wave and a beam spot 12 of a pulsed excimer laser are superimposed. A pulsed excimer laser can obtain an output energy of about 1 J per pulse. If the pulse width is about 30 ns, the output per unit time is 30 MW. Accordingly, assuming that the shape of the beam spot 12 of the pulsed excimer laser is rectangular, the length in the minor axis direction is L _X3 , and the length in the major axis direction is L _Y3 , in order to satisfy the above energy density. L _X3 is 20 μm to 500 μm. For example, when L _X3 = 400 μm, L _Y3 = 300 mm is appropriate.

  Assuming that the beam spot 10 of the continuous wave YAG laser having the fundamental wave overlaps with the beam spot 12 of the pulsed excimer laser, the beam spot 10 completely overlaps the beam spot 12. This corresponds to the area of the spot 10.

  Therefore, rather than making both the first laser beam and the second laser beam continuously oscillate as shown in FIG. 3A, the first laser beam is continuously oscillated and the second laser beam is used as in the present invention. When pulse oscillation is used, it is possible to greatly expand the overlapping region of the two laser beams, and it is possible to drastically suppress design restrictions in chip fabrication and further increase throughput.

  Note that the number of laser beams is not limited to two, but may be two or more. A plurality of first laser beams having harmonics may be used, or a plurality of second laser beams may be used.

  By making the beam spot linear, the width of the beam spot in the major axis direction of the region where crystal grains crystallized in the scanning direction gather can be made as wide as possible. That is, it can be said that the ratio of the area occupied by all the beam spots in the region of poor crystallinity formed at both ends of the long axis can be reduced. However, in the present invention, the shape of the beam spot is not limited to a linear shape, and there is no problem even if it is rectangular or planar as long as sufficient annealing can be performed on the irradiated object.

  Further, when the beam spot is processed into an elliptical shape or a rectangular shape that is long in one direction and is scanned in the short axis direction of the beam spot to crystallize the semiconductor film, the throughput can be increased. The reason why the shape of the laser beam after processing is elliptical is that the shape of the original laser beam is circular or close to it. If the original shape of the laser beam is a rectangular shape, it may be used after being processed so that the long axis becomes longer by enlarging it in one direction with a cylindrical lens or the like. In addition, a plurality of laser beams may be processed into an elliptical or rectangular shape that is long in one direction, and connected to create a longer beam in one direction, thereby further increasing the throughput.

  Here, “linear” does not mean “line” in a strict sense, but means a rectangle (or oval) having a large aspect ratio. For example, an aspect ratio of 2 or more (preferably 10 to 10000) is called a linear shape, but the linear shape is still included in a rectangular shape.

  FIG. 1A shows a state in which the semiconductor film is crystallized with the first and second laser beams. Reference numeral 101 denotes a first substrate, and a semiconductor film 102 is formed over the first substrate 101. Reference numeral 103 denotes a beam spot (first beam spot) formed on the semiconductor film 102 by the first laser beam, and reference numeral 104 denotes a beam spot (second beam spot) formed on the semiconductor film 102 by the second laser beam. ).

  Dashed arrows indicate the relative movement directions of the beam spots 103 and 104 with respect to the semiconductor film 102. The beam spots 103 and 104 scan in one direction on the semiconductor film 102 and then slide in a direction perpendicular to the scanning direction. Next, scanning is performed again on the semiconductor film 102 in one direction opposite to the one direction. By repeating such scanning in order, the beam spots 103 and 104 can be irradiated to the entire surface of the semiconductor film 102. It is desirable that the distance at which the beam spots 103 and 104 are slid is approximately the same as the width of the beam spot 103 in the direction perpendicular to the scanning direction.

  Reference numerals 105 to 107 correspond to areas to be used as chips later, and each of the areas 105 to 107 falls within a crystallized area by scanning the first and second beam spots 103 and 104 in one direction. Thus, in other words, the chip is laid out so as not to cross regions (edges) having poor crystallinity formed at both ends of the long axis of the second beam spot 104. By laying out in this way, a semiconductor film having at least almost no crystal grain boundary can be used for a semiconductor element in the chip.

  FIG. 1B shows a perspective view of a package formed by mounting the chips 105a to 107a formed in the regions 105 to 107 on the interposer 108, respectively. Mounting to the interposer 108 may be performed by stacking like the chip 105a and the chip 106a, or may be mounted by a single layer like the chip 107a. The terminals provided in the interposer 108 may be of a ball grid array type provided with solder balls, a lead frame type in which terminals are arranged in the periphery, or other types having known forms. There may be.

  In the present invention, since the semiconductor film is crystallized with laser light, crystallization can be performed while suppressing thermal damage given to the glass substrate, so that a chip using a polycrystalline semiconductor film on an inexpensive glass substrate is used. Can be formed.

  In addition, since the present invention can use a large glass substrate that is cheaper than silicon wafers, it can mass-produce chips at a lower cost and with a higher throughput, and the production cost per chip has increased dramatically. Can be suppressed. In addition, since the substrate can be used repeatedly, the cost per chip can be reduced.

  In addition, it is possible to form a chip so that the total film thickness is 5 μm, more desirably 2 μm or less, and the chip can be drastically cut without performing back grind processing that causes cracks and polishing marks. Can be thinned. The variation in the thickness of the chip also depends on the variation in the formation of each film constituting the chip, so it is about several hundred nanometers at most, and the variation of several to several tens of μm due to the back grinding process. Compared to, it can be dramatically reduced.

  By using the package of the present invention for an electronic device, a larger number of chips having a larger circuit scale and memory capacity can be mounted in a limited volume of the electronic device, while realizing the multifunction of the electronic device. It can also be reduced in size and weight. In particular, in the case of a portable electronic device, it is important to use the package of the present invention because the reduction in size and weight is regarded as important.

  The package of the present invention includes a liquid crystal display device, a light emitting device having a light emitting element represented by an organic light emitting element in each pixel, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display), etc. It can be used for various circuits for controlling the driving of the display device. For example, in the case of an active matrix liquid crystal display device and a light-emitting device, a scanning line driving circuit that selects each pixel, a signal line driving circuit that controls timing for supplying a video signal to the selected pixel, a scanning line driving circuit, and a signal A controller or the like that generates a signal to be supplied to the line driver circuit can be formed using the package of the present invention. In addition, the present invention can be applied not only to a circuit for controlling driving of a display device but also to a microprocessor (MPU), a memory, a power supply circuit, and other digital circuits and analog circuits. In addition, when the characteristics of a semiconductor element typified by TFT are drastically improved, various circuits generally called high-frequency circuits can be realized by the package of the present invention.

  The electronic device of the present invention is not limited to the display device described above, but a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, an audio playback device (car audio, audio component, etc.), a personal computer, a game device. , A portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), an image playback device equipped with a recording medium (specifically, a DVD (Digital Versatile Disc) or other recording medium, and the image In the scope of the device). In particular, the present invention is represented by a notebook personal computer, a portable video camera, a portable digital camera, a goggle type display (head mounted display), and a portable information terminal (mobile computer, cellular phone, portable game machine, electronic book, etc.). This is effective when used in portable electronic devices.

  The package of the present invention can be applied not only to CSP and MCP, but also to packages of all known forms such as DIP (Dual In-line Package), QFP (Quad Flat Package), and SOP (Small Outline Package). It is.

  In addition, since the present invention can use a large glass substrate that is cheaper than silicon wafers, it can mass-produce chips at a lower cost and with a higher throughput, and the production cost per chip has increased dramatically. Can be suppressed. In addition, since the substrate can be used repeatedly, the cost per chip can be reduced.

  In addition, it is possible to form a chip so that the total film thickness is 5 μm, more desirably 2 μm or less, and the chip can be drastically cut without performing back grind processing that causes cracks and polishing marks. Can be thinned. The variation in the thickness of the chip also depends on the variation in the formation of each film constituting the chip, so it is about several hundred nanometers at most, and the variation of several to several tens of μm due to the back grinding process. Compared to, it can be dramatically reduced.

  By using the package of the present invention for an electronic device, a larger number of chips having a larger circuit scale and memory capacity can be mounted in a limited volume of the electronic device, while realizing the multifunction of the electronic device. It can also be reduced in size and weight. In particular, in the case of a portable electronic device, it is important to use the package of the present invention because the reduction in size and weight is regarded as important.

  Further, in the present invention, the semiconductor film is melted by irradiating a pulsed first laser beam having a wavelength of visible light or less that is easily absorbed by the semiconductor film, and the absorption coefficient of the fundamental wave is increased. By using pulse oscillation for the first laser beam, the area of the beam spot can be drastically increased compared to continuous oscillation. By irradiating the second laser light having the fundamental wave in the melted state, the second laser light is efficiently absorbed by the semiconductor film having an increased fundamental wave absorption coefficient. Therefore, since the long axis of the beam spot can be made long, the throughput of laser crystallization can be increased, and it is effective in relaxing the chip design rule.

  Further, since the second laser beam is used as a fundamental wave, it is not necessary to consider the tolerance of the nonlinear optical element used for the conversion to the harmonic, and the second laser beam is a very high output laser, for example, a harmonic. Can be used having an energy of 100 times or more. And the maintenance complexity due to the alteration of the nonlinear optical element is eliminated. In particular, the advantage of a solid-state laser that can maintain a maintenance-free state for a long time can be utilized.

(Embodiment 1)
In this embodiment mode, a method for forming a package using a thin semiconductor film crystallized by first and second laser beams will be described. Note that in this embodiment mode, two TFTs are shown as an example of a semiconductor element. However, in the present invention, a semiconductor element included in a chip is not limited to this and includes any circuit element. For example, in addition to the TFT, a memory element, a diode, a photoelectric conversion element, a resistance element, a coil, a capacitor element, an inductor, and the like can be typically given.

  First, as shown in FIG. 5A, a metal film 501 is formed over the first substrate 500 by a sputtering method. Here, tungsten is used for the metal film 501, and the film thickness is 10 nm to 200 nm, preferably 50 nm to 75 nm. Note that in this embodiment, the metal film 501 is directly formed over the first substrate 500; however, the metal film is covered after the first substrate 500 is covered with an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide. 501 may be formed.

Then, after the metal film 501 is formed, the oxide film 502 is formed without being exposed to the air. Here, a silicon oxide film is formed as the oxide film 502 so as to have a thickness of 150 nm to 300 nm. Note that in the case where a sputtering method is used, film formation is also performed on an end surface of the first substrate 500. Therefore, in order to prevent the oxide film 502 from remaining on the first substrate 500 side at the time of peeling in a later process, the metal film 501 and the oxide film 502 formed on the end surface are subjected to O ₂ ashing. It is preferable to remove selectively.

When the oxide film 502 is formed, pre-sputtering is performed in which plasma is generated by blocking the target and the substrate with a shutter as a pre-sputtering step. Pre-sputtering is performed with Ar at a flow rate of 10 sccm and O ₂ at a flow rate of 30 sccm, the temperature of the first substrate 500 being 270 ° C., and the film forming power being maintained in a parallel state of 3 kW. By pre-sputtering, a very thin metal oxide film 503 having a thickness of several nm (here, 3 nm) is formed between the metal film 501 and the oxide film 502. The metal oxide film 503 is formed by oxidizing the surface of the metal film 501. Therefore, in this embodiment, the metal oxide film 503 is formed using tungsten oxide.

  Note that although the metal oxide film 503 is formed by pre-sputtering in this embodiment mode, the present invention is not limited to this. For example, oxygen or an inert gas such as Ar may be added to oxygen, and the surface of the metal film 501 may be intentionally oxidized by plasma to form the metal oxide film 503.

  Next, after an oxide film 502 is formed, a base film 504 is formed by a PCVD method. Here, a silicon oxynitride film is formed as the base film 504 so as to have a thickness of about 100 nm. Then, after the base film 504 is formed, the semiconductor film 505 is formed without being exposed to the air. The thickness of the semiconductor film 505 is 25 to 100 nm (preferably 30 to 60 nm). Note that the semiconductor film 505 may be an amorphous semiconductor or a polycrystalline semiconductor. As the semiconductor, not only silicon but also silicon germanium can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%.

  Next, as shown in FIG. 5B, the semiconductor film 505 is irradiated with first and second laser beams to be crystallized.

In this embodiment, a YLF laser having an energy of 6 W, an energy of 6 mJ / p for one pulse, an oscillation mode of TEM _00, a second harmonic (527 nm), an oscillation frequency of 1 kHz, and a pulse width of 60 ns is used as the first laser light. Note that the first beam spot formed on the surface of the semiconductor film 505 by processing the first laser beam with an optical system has a rectangular shape with a short axis of 200 μm and a long axis of 3 mm, and an energy density of 1000 mJ / cm ^2. And

In this embodiment, a YAG laser having an energy of 2 kW and a fundamental wave (1.064 μm) is used as the second laser light. Note that the second beam spot formed on the surface of the semiconductor film 505 by processing the second laser light with an optical system has a rectangular shape with a short axis of 100 μm and a long axis of 3 mm, and an energy density of 0.7 MW / cm ² .

  Then, irradiation is performed on the surface of the semiconductor film 505 so that the first beam spot and the second beam spot are overlapped with each other, and the two beams are directed toward the direction of the white arrow illustrated in FIG. Scan. By melting with the first laser light, the absorption coefficient of the fundamental wave is increased, and the energy of the second laser light is easily absorbed by the semiconductor film. Then, a region melted by irradiation with the second laser beam that is continuous oscillation moves in the semiconductor film, so that crystal grains continuously grown in the scanning direction are formed. By forming single crystal grains extending in the scanning direction, it is possible to form a semiconductor film having few crystal grain boundaries at least in the channel direction of the TFT.

  Note that laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. Thereby, roughness of the semiconductor surface due to laser light irradiation can be suppressed, and variation in threshold value caused by variation in interface state density can be suppressed.

  The laser beam spot has a linear shape, a rectangular shape, or an elliptical shape in which the ratio of the length of the major axis to the minor axis is greater than 5 in order to increase the proportion of the entire region having a uniform energy density. Is desirable.

  By irradiating the semiconductor film 505 with the laser light, the semiconductor film 506 with higher crystallinity is formed. Next, as shown in FIG. 5C, the semiconductor film 506 is patterned to form island-shaped semiconductor films 507 and 508, and various islands such as TFTs are formed using the island-shaped semiconductor films 507 and 508. A semiconductor element is formed. Note that in this embodiment mode, the base film 504 and the island-shaped semiconductor films 507 and 508 are in contact with each other. However, depending on the semiconductor element, an electrode or an electrode may be provided between the base film 504 and the island-shaped semiconductor films 507 and 508. An insulating film or the like may be formed. For example, in the case of a bottom gate TFT which is one of semiconductor elements, a gate electrode and a gate insulating film are formed between a base film 504 and island-shaped semiconductor films 507 and 508.

  In this embodiment mode, top-gate TFTs 509 and 510 are formed using island-shaped semiconductor films 507 and 508 (FIG. 5D). Specifically, a gate insulating film 511 is formed so as to cover the island-shaped semiconductor films 507 and 508. Then, a conductive film is formed over the gate insulating film 511 and patterned to form gate electrodes 512 and 513. Then, using the gate electrodes 512 and 513 or a resist film formed and patterned as a mask, an impurity imparting n-type is added to the island-shaped semiconductor films 507 and 508, and the source region, the drain region, and further LDD regions and the like are formed. Note that the TFTs 509 and 510 are n-type here, but in the case of a p-type TFT, an impurity imparting p-type conductivity is added.

  The TFTs 509 and 510 can be formed through the above series of steps. Note that a method for manufacturing a TFT is not limited to the above-described process after the island-shaped semiconductor film is formed. By using laser crystallization which is one of the features of the present invention, variations in mobility, threshold value, and on-current between elements can be suppressed.

  Next, a first interlayer insulating film 514 is formed so as to cover the TFTs 509 and 510. Then, after forming contact holes in the gate insulating film 511 and the first interlayer insulating film 514, wirings 515 to 518 connected to the TFTs 509 and 510 through the contact holes are in contact with the first interlayer insulating film 514. Form. Then, a second interlayer insulating film 519 is formed over the first interlayer insulating film 514 so as to cover the wirings 515 to 518.

  Then, a contact hole is formed in the second interlayer insulating film 519, and a pad 520 connected to the wiring 518 through the contact hole is formed on the second interlayer insulating film 519. Note that in this embodiment mode, the pad 520 is electrically connected to the TFT 510 through the wiring 518; however, the form of electrical connection between the semiconductor element and the pad 520 is not limited thereto.

  Next, a protective layer 521 is formed over the second interlayer insulating film 519 and the pad 520. The protective layer 521 can protect the surfaces of the second interlayer insulating film 519 and the pad 520 when the second substrate is attached or peeled later, and is removed after the second substrate is peeled off. Use possible materials. For example, the protective layer 521 can be formed by applying an epoxy-based, acrylate-based, or silicone-based resin soluble in water or alcohols over the entire surface and baking it.

  In this embodiment, a water-soluble resin (manufactured by Toagosei Co., Ltd .: VL-WSHL10) is applied by spin coating so as to have a film thickness of 30 μm, and after exposure for 2 minutes for temporary curing, UV light is applied from the back surface. Exposure is performed for 2.5 minutes and 10 minutes from the surface for a total of 12.5 minutes, followed by main curing to form the protective layer 521 (FIG. 5E).

In addition, when laminating | stacking several organic resin, there exists a possibility that it may melt | dissolve partially at the time of application | coating or baking with the solvent currently used between organic resins, or adhesiveness may become high too much. Therefore, when the second interlayer insulating film 519 and the protective layer 521 are both made of an organic resin soluble in the same solvent, the second interlayer insulating film is removed so that the protective layer 521 can be removed smoothly in the subsequent process. An inorganic insulating film (SiN _x film, SiN _x O _y film, AlN _x film, or AlN _x O _y film) so as to cover 519 and to be sandwiched between second interlayer insulating film 519 and pad 520 ) Is preferably formed.

  Next, the metal oxide film 503 is crystallized in order to facilitate subsequent peeling. By crystallization, the metal oxide film 503 is easily broken at the grain boundary, and brittleness can be increased. In this embodiment mode, heat treatment is performed at 420 ° C. to 550 ° C. for about 0.5 to 5 hours to perform crystallization.

  Next, treatment for partially reducing the adhesion between the metal oxide film 503 and the oxide film 502 or the adhesion between the metal oxide film 503 and the metal film 501 to form a part that triggers the start of peeling. To do. Specifically, the metal oxide film 503 is partially irradiated with laser light along the periphery of the region to be peeled off, or pressure is locally applied from the outside along the periphery of the region to be peeled off. In other words, the metal oxide film 503 may be damaged in a part of the layer or in the vicinity of the interface. In this embodiment, a hard needle such as a diamond pen is pressed perpendicularly near the end of the metal oxide film 503 and moved along the metal oxide film 503 with a load applied as it is. Preferably, a scriber device is used, the pushing amount is 0.1 mm to 2 mm, and the pressure is applied. In this way, by forming a portion with reduced adhesion that triggers the start of peeling before peeling, defects in the subsequent peeling step can be reduced, leading to improved yield. .

  Next, the second substrate 523 is attached to the protective layer 521 using the double-sided tape 522, and the third substrate 525 is attached to the first substrate 500 using the double-sided tape 524 (FIG. 6A). Note that an adhesive may be used instead of the double-sided tape. For example, by using an adhesive that is peeled off by ultraviolet rays, it is possible to reduce the burden on the semiconductor element when the second substrate is peeled off. The third substrate 525 prevents the first substrate 500 from being damaged in a subsequent peeling step. As the second substrate 523 and the third substrate 525, it is preferable to use a substrate having higher rigidity than the first substrate 500, such as a quartz substrate or a semiconductor substrate.

  Next, the metal film 501 and the oxide film 502 are physically peeled off. The peeling starts from a region where the adhesion of the metal oxide film 503 to the metal film 501 or the oxide film 502 is partially lowered in the previous step.

  A portion separated between the metal film 501 and the metal oxide film 503, a portion separated between the oxide film 502 and the metal oxide film 503, and a portion where the metal oxide film 503 itself is separated into both by peeling. Arise. Then, the semiconductor element (here, TFTs 509 and 510) is separated on the second substrate 523 side, and the first substrate 500 and the metal film 501 are separated on the third substrate 525 side, respectively. The peeling can be performed with a relatively small force (for example, a human hand, a wind pressure of a gas blown from a nozzle, an ultrasonic wave, etc.). The state after peeling is shown in FIG.

  Next, the interposer 527 is bonded to the oxide layer 502 to which the metal oxide film 503 is partially attached with an adhesive 526 (FIG. 6C). At this time, the adhesive force between the oxide layer 502 and the interposer 527 by the adhesive 526 is higher than the adhesive force between the second substrate 523 and the protective layer 521 by the double-sided tape 522. It is important to select a material for the adhesive 526.

  If the metal oxide film 503 remains on the surface of the oxide film 502, the adhesion with the interposer 527 may be deteriorated. Therefore, the metal oxide film 503 is removed by etching or the like and then adhered to the interposer. You may make it improve adhesiveness.

  As the interposer 527, a known material such as a ceramic substrate, a glass epoxy substrate, or a polyimide substrate can be used. In order to diffuse the heat generated in the chip, it is desirable to have a high thermal conductivity of about 2 to 30 W / mK.

  A package terminal 530 is provided on the interposer 527, and the terminal 530 is electrically connected to a solder ball 531 provided on the interposer 527. The solder ball 531 is provided on the surface opposite to the surface on which the terminal 530 of the interposer 527 is provided. Although only one solder ball 531 is shown here, a plurality of interposers 527 are actually provided. The pitch between the balls is generally standardized at 0.8 mm, 0.65 mm, 0.5 mm, or 0.4 mm. However, the present invention is not limited to these pitches. The size of each ball is generally standardized at about 60% of the pitch. However, the present invention is not limited to these sizes.

  The terminal 530 is formed by plating copper, solder, gold, or tin, for example. In this embodiment, a ball grid array type interposer provided with solder balls is used, but the present invention is not limited to this. It may be a lead frame type interposer in which terminals are arranged in the periphery.

  Examples of the adhesive 526 include a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and various curable adhesives such as an anaerobic adhesive. More preferably, the adhesive 526 is also provided with high thermal conductivity by including powder or filler made of silver, nickel, aluminum, aluminum nitride.

  Next, as shown in FIG. 7A, the double-sided tape 522 and the second substrate 523 are peeled from the protective layer 521 in order or simultaneously.

Then, as shown in FIG. 7B, the protective layer 521 is removed. Here, since a water-soluble resin is used for the protective layer 521, it is dissolved in water and removed. In the case where the protective layer 521 remains causes a failure, it is preferable to perform a cleaning process or an O ₂ plasma process on the surface after removal to remove a part of the remaining protective layer 521.

  Next, the pad 520 and the terminal 530 are connected by a wire 532 using a wire bonding method, and sealed by an airtight sealing method or a resin sealing method, thereby completing a package. When using the hermetic sealing method, sealing is generally performed using a case of ceramic, metal, glass, or the like. When using a resin sealing method, specifically, a mold resin or the like is used. The chip is not necessarily sealed, but the mechanical strength of the package can be increased, heat generated in the chip can be dissipated, and electromagnetic noise from adjacent circuits can be blocked.

  Note that in this embodiment mode, tungsten is used for the metal film 501, but the metal film is not limited to this material in the present invention. Any metal-containing material may be used as long as a metal oxide film 503 is formed on the surface and the substrate can be peeled off by crystallizing the metal oxide film 503. For example, W, TiN, WN, Mo, or the like can be used. Further, when these alloys are used as metal films, the optimum temperature for the heat treatment during crystallization differs depending on the composition ratio. Therefore, by adjusting the composition ratio, heat treatment can be performed at a temperature that does not interfere with the manufacturing process of the semiconductor element, and options for the process of the semiconductor element are not easily limited.

  In the present embodiment, the CSP in which one chip is mounted in one package has been described as an example, but the present invention is not limited to this. It may be an MCP on which a plurality of chips are mounted in parallel or stacked.

  The first laser light and the second laser light are not limited to the irradiation conditions described in this embodiment mode.

For example, a YAG laser having an energy of 4 W, an energy of 2 mJ / p, a TEM ₀₀ oscillation mode, a second harmonic (532 nm), an oscillation frequency of 1 kHz, and a pulse width of 30 ns may be used as the first laser light. Further, for example, a YVO ₄ laser having an energy of 5 W, an energy of 0.25 mJ / p, a TEM ₀₀ oscillation mode, a third harmonic (355 nm), an oscillation frequency of 20 kHz, and a pulse width of 30 ns is used as the first laser beam. You can also. Further, for example, as the first laser light, a YVO ₄ laser having an energy of 3.5 W, an energy of one pulse of 0.233 mJ / p, an oscillation mode of TEM _00, a fourth harmonic (266 nm), an oscillation frequency of 15 kHz, and a pulse width of 30 ns. Can also be used.

  For example, an Nd: YAG laser having an energy of 500 W and a fundamental wave (1.064 μm) can be used as the second laser light. For example, an Nd: YAG laser having an energy of 2000 W and a fundamental wave (1.064 μm) can be used as the second laser light.

  Note that the first laser beam may be continuously oscillated as long as the width of the beam spot in the direction perpendicular to the scanning direction can be secured to a degree sufficient to form a chip. When the first laser beam is not a pulse oscillation but a continuous oscillation, each chip is formed in a region that fits in a width in a direction perpendicular to the scanning direction of the beam spot of the first laser beam. Then, in order to ensure a sufficient beam spot width in the direction perpendicular to the scanning direction to form a chip, a plurality of beam spots obtained by the plurality of first laser beams are overlapped with each other, You may use as one beam spot.

  Further, a crystallization step using a catalytic element may be provided before crystallization with laser light. Nickel (Ni) is used as the catalyst element, but besides that, germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), Elements such as platinum (Pt), copper (Cu), and gold (Au) can be used. When a crystallization process using a laser beam is performed after a crystallization process using a catalytic element, the crystal formed during the crystallization using the catalytic element remains on the side closer to the substrate without being melted by the laser beam irradiation. Then, crystallization proceeds using the crystal as a crystal nucleus. Therefore, crystallization by laser light irradiation tends to progress uniformly from the substrate side toward the surface of the semiconductor film, and the crystallinity of the semiconductor film can be improved more than in the case of only the crystallization process by laser light. The surface roughness of the semiconductor film after crystallization by light can be suppressed. Accordingly, variation in characteristics of semiconductor elements formed later, typically TFTs, can be further suppressed, and off-current can be suppressed.

  Note that after the catalyst element is added and heat treatment is performed to promote crystallization, the crystallinity may be further increased by laser light irradiation, or the heat treatment step may be omitted. Specifically, after adding the catalyst element, laser light irradiation may be applied instead of the heat treatment to improve crystallinity.

In the present invention, the thickness of the chip includes not only the thickness of the semiconductor element itself, but also the thickness of the insulating film provided between the metal oxide film and the semiconductor element, and the interlayer insulating film that covers the semiconductor element after it is formed. Bumps are not included, including thickness and pad thickness.
(Embodiment 2)
The structure of a laser irradiation apparatus used in manufacturing the package of the present invention will be described with reference to FIG.

Reference numeral 201 denotes a pulse oscillation laser oscillator. In this embodiment, a 6 W Nd: YLF laser is used. The laser oscillator 201 is converted into the second harmonic by a nonlinear optical element in the TEM ₀₀ oscillation mode. Although it is not necessary to limit to the second harmonic in particular, the second harmonic is superior to the higher harmonics in terms of energy efficiency. The frequency is 1 kHz and the pulse width is about 60 ns. In the present embodiment, a solid-state laser having an output of about 6 W is used, but a large-sized laser, such as a XeCl excimer laser, whose output reaches 300 W may be used.

Nonlinear optical elements include KTP (KTiOPO ₄ ), BBO (β-BaB ₂ O ₄ ), LBO (LiB ₃ O ₅ ), CLBO (CsLiB ₆ O ₁₀ ), GdYCOB (YCa ₄ O) having relatively large nonlinear optical constants. Crystals such as (BO ₃ ) ₃ ), KDP (KD ₂ PO ₄ ), KB5, LiNbO ₃ , Ba ₂ NaNb ₅ O ₁₅ are used, and in particular, LBO, BBO, KDP, KTP, KB5, CLBO, etc. are used. Thus, the conversion efficiency from the fundamental wave to the harmonic can be increased.

  Since the laser light is normally emitted in the horizontal direction, the first laser light oscillated from the laser oscillator 201 is reflected by the reflecting mirror 202 in the direction in which the angle from the vertical direction (incident angle) is θ1. The direction of travel is changed. In the present embodiment, θ1 = 21 °. The shape of the beam spot of the first laser light whose traveling direction has been converted is processed by the lens 203, and is irradiated on the workpiece 204. In FIG. 4, the reflection mirror 202 and the lens 203 correspond to an optical system that controls the shape and position of the beam spot of the first laser beam.

  In FIG. 4, a plano-concave cylindrical lens 203a and a plano-convex cylindrical lens 203b are used as the lens 203. The plano-concave cylindrical lens 203a has a radius of curvature of 10 mm and a thickness of 2 mm, and is disposed at a position of 29 mm along the optical axis from the surface of the workpiece 204 when the traveling direction of the first laser beam is the optical axis. Has been. The bus line of the plano-concave cylindrical lens 203a and the incident surface of the first laser beam incident on the object to be processed 204 are set to be vertical.

  The plano-convex cylindrical lens 203b has a radius of curvature of 15 mm and a thickness of 2 mm, and is disposed at a position of 24 mm from the surface of the workpiece 204 along the optical axis. The generatrix of the planoconvex cylindrical lens 203b is parallel to the incident surface of the first laser beam incident on the workpiece 204.

  As a result, a first beam spot 206 having a size of 3 mm × 0.2 mm is formed on the workpiece 204.

  Reference numeral 210 denotes a continuous oscillation laser oscillator, which uses a 2 kW, fundamental wave Nd: YAG laser in this embodiment. The second laser light oscillated from the laser oscillator 210 is transmitted by the optical fiber 211 having a diameter of 300 μm. The optical fiber 211 is arranged such that the direction of the exit with respect to the vertical direction is an angle θ2. In this embodiment, θ2 = 45 °. The exit of the optical fiber 211 is disposed at a position 105 mm from the workpiece 204 along the optical axis of the second laser light emitted from the laser oscillator 210, and the optical axis is included in the incident surface. To do.

  The shape of the beam spot of the second laser light emitted from the optical fiber 211 is processed by the lens 212 and irradiated to the object 204. In FIG. 4, the optical fiber 211 and the lens 212 correspond to an optical system that controls the shape and position of the beam spot of the second laser light. In FIG. 4, a planoconvex cylindrical lens 212 a and a planoconvex cylindrical lens 212 b are used as the lens 213.

  The planoconvex cylindrical lens 212a has a radius of curvature of 15 mm and a thickness of 4 mm, and is disposed at a position of 85 mm from the surface of the workpiece 204 along the optical axis of the second laser beam. The direction of the generatrix of the planoconvex cylindrical lens 212a is perpendicular to the incident surface. The planoconvex cylindrical lens 212b has a radius of curvature of 10 mm and a thickness of 2 mm, and is arranged at a position of 25 mm from the surface of the workpiece 204 along the optical axis of the second laser beam.

  As a result, a second beam spot 205 having a size of 3 mm × 0.1 mm is formed on the workpiece 204.

  In this embodiment, a substrate over which a semiconductor film is formed as the object to be processed 204 is placed so as to be parallel to a horizontal plane. For example, the semiconductor film is formed on the surface of a glass substrate. The substrate on which the semiconductor film is formed is a glass substrate having a thickness of 0.7 mm, and is fixed to the suction stage 207 so that the substrate does not fall during laser irradiation. The suction stage 207 can be moved in the X and Y directions in a plane parallel to the workpiece 204 by a single axis robot 208 for X axis and a single axis robot 209 for Y axis.

  In the case of annealing a semiconductor film formed on a substrate that is transparent to laser light, in order to achieve uniform laser light irradiation, the plane is perpendicular to the irradiation surface, and When any one of a surface including a short side or a surface including a long side when the shape of the beam is regarded as a rectangle is defined as an incident surface, the incident angle φ of the laser beam is the short side included in the incident surface or Φ ≧ arctan (W / 2d) is satisfied when the length of the long side is W, the thickness of the substrate that is installed on the irradiation surface and has a light transmitting property to the laser beam is d. Is desirable. If multiple laser beams are used, this argument needs to hold for each laser beam. When the locus of the laser beam is not on the incident surface, the incident angle of the projection of the locus onto the incident surface is φ. When laser light is incident at this incident angle φ, the reflected light from the surface of the substrate and the reflected light from the back surface of the substrate do not interfere with each other, and uniform laser light irradiation can be performed. In the above discussion, the refractive index of the substrate was considered as 1. Actually, in many cases, the refractive index of the substrate is around 1.5, and if this value is taken into consideration, a calculated value larger than the angle calculated in the above discussion can be obtained. However, since the energy of the beam spot is attenuated as it approaches the end of the beam spot, the influence of the interference in this portion is small, and the effect of interference attenuation can be sufficiently obtained by the above calculated value. It is preferable that both the first laser beam and the second laser beam satisfy the above inequality, but this discussion is about an extremely short coherent laser such as an excimer laser. There is no problem even if the above inequality is not satisfied. The above inequality for φ is applied only when the substrate is transparent to laser light.

  Generally, a glass substrate has translucency with respect to a fundamental wave having a wavelength of about 1 μm or a green second harmonic. In order for this lens to satisfy the inequality, the plane perpendicular to the surface of the workpiece 204 including the minor axis of the beam spot is obtained by shifting the positions of the planoconvex cylindrical lens 203b and the planoconvex cylindrical lens 212b in a direction perpendicular to the incident plane. The incident angles φ1 and φ2 may be provided to satisfy the inequality. In this case, if the first beam spot 206 has an inclination of φ1 = 10 ° and the second beam spot 205 has an inclination of φ2 = 5 °, no interference occurs.

Note that the first laser beam and the second laser beam are preferably in a TEM ₀₀ mode (single mode) obtained from a stable resonator. In the case of the TEM ₀₀ mode, the laser beam has a Gaussian intensity distribution and has excellent light collecting properties, so that the beam spot can be easily processed.

  Then, the workpiece 204 (the substrate on which the semiconductor film is formed) is scanned in the short axis direction of the second beam spot 205 using the Y-axis robot 209. At this time, the outputs of the laser oscillators 201 and 202 are set to specification values. By scanning the workpiece 204, the first beam spot 206 and the second beam spot 205 are scanned relative to the surface of the workpiece 204.

  When the semiconductor film is melted in the region where the first beam spot 206 is hit, the absorption coefficient of the continuous wave second laser light into the semiconductor film is dramatically increased. Accordingly, the single crystal crystal grains grown in the scanning direction are formed in a state of being extended in the scanning direction and having a width of 1 to 2 mm corresponding to the long axis of the second beam spot 205.

  Note that in the semiconductor film, the region where the first beam spot 206 and the second beam spot 205 are overlapped with each other has a fundamental wave whose absorption coefficient is increased by the first laser beam of the second harmonic. It is maintained by a certain first laser beam. Therefore, even if the irradiation of the first laser beam of the second harmonic is interrupted, the semiconductor laser is melted and the absorption coefficient is increased by the first laser beam that is the fundamental wave thereafter. . Therefore, even after the irradiation of the first laser beam of the second harmonic is interrupted, the region where the melting coefficient and the absorption coefficient are increased can be moved in one direction to some extent by scanning. Crystal grains grown toward the surface are formed. Then, in order to continuously maintain the region with the increased absorption coefficient in the scanning process, it is desirable to re-irradiate the first laser beam of the second harmonic and replenish the energy.

  Note that the scanning speed of the first beam spot 206 and the second beam spot 205 is suitably about several cm / s to several hundred cm / s, and is set to 50 cm / s here.

  A region where crystal grains grown in the scanning direction are irradiated with the second laser light is extremely excellent in crystallinity. Therefore, by using this region as a TFT channel formation region, extremely high electric mobility and on-current can be expected. However, when there is a portion of the semiconductor film where such high crystallinity is not required, the portion may not be irradiated with laser light. Alternatively, laser light irradiation may be performed under conditions that do not provide high crystallinity, such as increasing the scanning speed. For example, when scanning is performed at a speed of about 2 m / s, the a-Si film can be crystallized, but a region that is continuously crystallized in the scanning direction as described above is difficult to form. The throughput can be further increased by partially increasing the scanning speed.

  Note that the optical system in the laser irradiation apparatus of the present invention is not limited to the structure shown in this embodiment mode.

(Embodiment 3)
In the case where a plurality of chips are manufactured on the first substrate at the same time, it is necessary to perform dicing in the middle and separate the chips before completion as a package. In this embodiment, dicing timing will be described.

  FIG. 8 corresponds to an example of a flowchart of a package manufacturing process. Note that the positions of pads that function as terminals for electrical connection to the integrated circuit are different between the wire bonding method and the flip chip method. Here, the flow of a flowchart when forming a pad after forming an element is indicated by a solid arrow, and the flow of a flowchart when forming a pad before forming an element is indicated by a broken arrow.

  A case where a pad is formed after an element is formed will be described. First, a metal film is formed on the first substrate, and then the surface of the metal film is oxidized to form a metal oxide film. Then, after an insulating film is formed on the metal oxide film, a process for forming an element (semiconductor element) is started. In the present invention, laser crystallization of the semiconductor film is performed in the step of forming the element. A detailed description of laser crystallization has already been given and is omitted here. After the elements are formed and the integrated circuit is completed, pads are formed. After that, a protective layer is formed so as to cover the element and the pad, and the second substrate is bonded to the protective layer side and the third substrate is bonded to the first substrate side. Then, the first and third substrates are peeled off so as to be peeled off from the element. Next, the element attached to the second substrate is mounted on an interposer, the second substrate and the protective layer are removed, and then bonded and sealed to complete a package.

  In this case, since the pad is on the opposite side of the interposer with the element interposed therebetween, a wire bonding method can be used for bonding between the interposer and the chip. When the wire bonding method is used, the bonding process is performed after the chip is mounted and the second substrate is removed. In this case, as shown in FIG. 9A, the dicing timing is preferably performed after the first and third substrates are peeled and before mounting.

  A case of forming a pad before forming an element will be described. First, a metal film is formed on the first substrate, and then the surface of the metal film is oxidized to form a metal oxide film. Then, after forming an insulating film on the metal oxide film, a pad is formed, and then an element (semiconductor element) is formed. A further insulating film may be provided between the element and the pad, and a contact hole may be formed to electrically connect the element and the pad, or both may be formed on the same insulating film to form a contact hole. You may connect electrically without interposing. After the element is formed and the integrated circuit is completed, a protective layer is formed so as to cover the element, and the second substrate is bonded to the protective layer side and the third substrate is bonded to the first substrate side. Then, the first and third substrates are peeled off so as to be peeled off from the element. Since the pad comes between the element and the interposer, the flip chip method can be used for bonding between the interposer and the chip. Therefore, after the insulating film is partially etched to expose the pad, bumps are formed on the pad. A marker for alignment used in this etching is preferably formed using a semiconductor film when an element is formed. Next, the element attached to the second substrate is mounted on an interposer, bonded with bumps, the second substrate and the protective layer are removed, and then sealed to complete a package.

  In this case, as shown in FIG. 9A, dicing is preferably performed after the first and third substrates are peeled and before mounting. In the case of FIG. 9A, dicing may be performed either before or after the bump is formed. Further, as shown in FIG. 9B, it may be performed after mounting and before the second substrate is peeled off, or as shown in FIG. 9C, after the second substrate is peeled off. good.

  The above description is based on the assumption that only one chip is mounted on one interposer, but the present invention is not limited to this. When stacking chips formed on the same first substrate, dicing is preferably performed before mounting as shown in FIG. Each chip is mounted after the second substrate is peeled from the lower chip in order.

  In addition, when chips formed separately on different first substrates are stacked on each other, dicing of a chip that is first mounted on the interposer is not limited to the timing shown in FIG. 9A, and FIG. It can also be performed at the timing shown in FIG. However, also in this case, each chip is mounted after the second substrate is peeled from the lower chip in order.

  Note that the step of forming a pad and the step of forming a semiconductor element cannot always be clearly separated from each other. For example, when a top gate type TFT is used as a semiconductor element and the pad is manufactured in the same process as the gate electrode of the TFT, the process of manufacturing the pad is included in the process of manufacturing the semiconductor element. In this case, when the chip is mounted on the interposer, it is determined whether the pad (or bump) is exposed toward the interposer side or the side opposite to the interposer. That is, in the former case, dicing can be performed at the same timing as when the pad is formed before the element is formed. In the latter case, dicing can be performed at the same timing as when the pad is formed after the element is formed.

(Embodiment 4)
In this embodiment mode, a method of electrical connection between an interposer and a chip will be described.

  FIG. 10A is a perspective view showing a cross-sectional structure of a package in which a chip is connected to an interposer by a wire bonding method. 301 is an interposer, 302 is a chip, and 303 is a mold resin layer. The chip 302 is mounted on the interposer 301 with a mounting adhesive 304.

  An interposer 301 shown in FIG. 10A is a ball grid array type in which solder balls 305 are provided. The solder ball 305 is provided on the side opposite to the side on which the chip 302 of the interposer 301 is mounted. The wiring 306 provided in the interposer 301 is electrically connected to the solder ball 305 through a contact hole provided in the interposer 305.

  In this embodiment mode, the wiring 306 for electrical connection between the chip 302 and the solder ball 305 is provided on the surface of the interposer 305 on which the chip is mounted. It is not limited to this. For example, the wiring may be provided in multiple layers inside the interposer.

  In FIG. 10A, the chip 302 and the wiring 306 are electrically connected by a wire 307. FIG. 10B is a cross-sectional view of the package illustrated in FIG. The chip 302 is provided with a semiconductor element 309, and a pad 308 is provided on the side of the chip 302 opposite to the side where the interposer 301 is provided. The pad 308 is electrically connected to the semiconductor element 309. The pad 308 is connected to the wiring 306 provided in the interposer 301 by the wire 307.

  Reference numeral 310 corresponds to a part of the printed wiring board, and 311 corresponds to a wiring or an electrode provided on the printed wiring board 310. The wiring 306 is connected to a wiring or electrode 311 provided on the printed wiring board 310 via a solder ball 305. Note that various methods such as thermocompression bonding, thermocompression bonding with ultrasonic vibration, and the like can be used for connection between the solder ball 305 and the wiring or electrode 311. Note that the underfill may fill the gaps between the solder balls after the pressure bonding so as to increase the mechanical strength of the connection portion and the efficiency of diffusion of heat generated in the package. The underfill is not necessarily used, but connection failure can be prevented from occurring due to a stress caused by a mismatch between the thermal expansion coefficients of the interposer and the chip. When crimping by applying ultrasonic waves, poor connection can be suppressed as compared to the case of simply thermocompression bonding. This is particularly effective when there are more than 300 bumps to be connected.

  Next, FIG. 10C shows a cross-sectional view of the package in which the chip is connected to the interposer using a flip chip method. In the package illustrated in FIG. 10C, a solder ball 327 is provided on a chip 322. The solder ball 327 is provided on the interposer 321 side of the chip 322, and is connected to a pad 328 that is also provided on the chip 322. The semiconductor element 329 provided in the chip 322 is connected to the pad 328. In the case where a TFT is used as the semiconductor element 329, the pad 328 may be formed of the same conductive film as the gate electrode of the TFT.

  The solder ball 327 is connected to the wiring 326 provided on the interposer 321. In FIG. 10C, an underfill 324 is provided so as to fill a gap between the solder balls 327. The solder ball 325 of the interposer 321 is provided on the side opposite to the side on which the chip 322 of the interposer 321 is mounted. The wiring 326 provided in the interposer 321 is electrically connected to the solder ball 325 through a contact hole provided in the interposer 325.

  In the case of the flip chip method, even if the number of pads to be connected is increased, the pitch between the pads can be relatively wide compared with the wire bonding method, so that it is suitable for connecting a chip having a large number of terminals. Yes.

  Next, FIG. 10D shows a cross-sectional view of a package in which chips are stacked using a flip chip method. In the package illustrated in FIG. 10D, two chips 330 and 331 are stacked over an interposer 333. The wiring 335 provided in the interposer 333 and the chip 330 are electrically connected using a solder ball 334. The electrical connection between the chip 330 and the chip 331 is performed using a solder ball 332.

  Note that the package shown in FIGS. 10A to 10D uses a ball grid array type interposer; however, the present invention is not limited to this. A lead frame type in which terminals are arranged in the periphery may be used. FIG. 11 is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer.

  In the package shown in FIG. 11, a chip 351 is connected to a terminal 352 on the interposer 350 by a wire bonding method. The terminal 352 is disposed on the surface on which the chip 351 of the interposer 350 is mounted. The chip 351 may be sealed with a mold resin 353, but is sealed with a part of each terminal 352 exposed.

  Next, FIG. 12A shows a cross-sectional view of a package in which stacked chips are connected by a wire bonding method. In FIG. 12A, two chips 360 and 361 are stacked on the interposer 362. The chip 360 is electrically connected to the wiring 363 provided in the interposer 362 and the wire 364. Further, the chip 361 is electrically connected to the wiring 363 provided in the interposer 362 by a wire 365.

  In FIG. 12A, the chip 360 and the chip 361 are connected to each other through wires and wires provided in the interposer 362, but the chips may be connected to each other with wires.

  Next, FIG. 12B illustrates an example in which packages are stacked. In FIG. 12B, the packages 370 and 371 mounted with chips are electrically connected using a solder ball 372 and stacked.

  Comparing the case where the chips are stacked and mounted on one interposer, and the case where the packages are stacked are used, the size of the entire package can be reduced in the former case compared to the latter case. Has a merit. On the other hand, in the latter case, unlike the former, electrical inspection is performed for each package, and only good products can be selected and stacked, so that the yield can be increased.

  Note that the package of the present invention may be bonded to a chip by combining a wire bonding method and a flip chip method. Further, instead of stacking chips, bonding may be performed so that stacked chips or single-layer chips are arranged in parallel on the interposer.

(Embodiment 5)
In this embodiment, an example of a specific chip stacking method is shown. First, in accordance with the manufacturing method shown in Embodiment Mode 1, the first chip is manufactured as mounted as shown in FIG.

  On the other hand, the second-layer chip is manufactured to the state shown in FIG. 5D according to the manufacturing method shown in Embodiment Mode 1. Then, as shown in FIG. 13A, a bump 621 is formed on the pad 620. In this embodiment mode, an example in which chips are connected to each other by applying ultrasonic vibration as well as thermocompression bonding will be described. Therefore, the bump 621 is not a sphere but has a protrusion.

  Next, as shown in FIG. 13B, an underfill 623 is applied so as to cover the pads 622 of the first layer chip, and the second layer chip shown in FIG. Is pressure-bonded so as to face the pad 622 of the chip of the first layer. At this time, in this embodiment, the bump 621 and the pad 622 are pressure-bonded while applying ultrasonic vibration to the second layer chip side. The protrusions of the bumps 621 reach the pads 622 so as to push the underfill 623 separately, and are crushed there and pressed onto the pads 622.

  And the process which hardens an underfill, specifically, heating, ultraviolet irradiation, etc. are performed and the adhesiveness of chips | tips is improved. Next, as shown in Embodiment Mode 1, the metal oxide film 624 is crystallized. By crystallization, the metal oxide film 624 is easily broken at the grain boundary, and brittleness can be increased. In this embodiment mode, heat treatment is performed at 420 ° C. to 550 ° C. for about 0.5 to 5 hours to perform crystallization.

  Next, as shown in FIG. 14A, a third substrate 627 is attached to the first substrate 626 using a double-sided tape 625. Then, as shown in FIG. 14B, the first substrate 626 is peeled off from the second layer chip 628 with the metal oxide film 624 as a boundary.

  With the above structure, the first layer chip 629 and the second layer chip 628 can be stacked so as to be electrically connected.

  A cellular phone which is one of the electronic devices of the present invention is taken as an example, and FIG. 15A shows a state where a package is actually mounted on the electronic device.

  A cellular phone module illustrated in FIG. 15A includes a printed wiring board 812, a controller 801, a CPU 802, a memory 811, a power supply circuit 803, an audio processing circuit 829, a transmission / reception circuit 804, a resistor, a buffer, a capacitor, and the like. These elements are mounted. Further, the panel 800 is mounted on the printed wiring board 812 by the FPC 808. The panel 800 includes a pixel portion 805 in which a light emitting element is provided in each pixel, a scanning line driver circuit 806 that selects a pixel included in the pixel portion 805, and a signal line driver circuit that supplies a video signal to the selected pixel. 807 is provided.

  The power supply voltage to the printed wiring board 812 and various signals input from a keyboard or the like are supplied via a printed wiring board interface (I / F) unit 809 in which a plurality of input terminals are arranged. An antenna port 810 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 812.

  In this embodiment, the printed wiring board 812 is mounted on the panel 800 using FPC, but the present invention is not necessarily limited to this configuration. The controller 801, the audio processing circuit 829, the memory 811, the CPU 802, or the power supply circuit 803 may be directly mounted on the panel 800 using a COG (Chip on Glass) method.

  Further, in the printed wiring board 812, noise may occur in a power supply voltage or a signal, or a signal may be slow to rise due to a capacitance formed between the drawn wirings, a resistance of the wiring itself, or the like. Therefore, by providing various elements such as a capacitor and a buffer on the printed wiring board 812, it is possible to prevent noise from being applied to the power supply voltage and the signal and the rise of the signal from being slowed down.

  FIG. 15B shows a block diagram of the module shown in FIG.

  In this embodiment, the memory 811 includes a VRAM 832, a DRAM 825, a flash memory 826, and the like. The VRAM 832 stores image data to be displayed on the panel, the DRAM 825 stores image data or audio data, and the flash memory stores various programs.

  The power supply circuit 803 includes a panel 800, a controller 801, a CPU 802, an audio processing circuit 829, a memory 811, and a transmission / reception circuit 804. Depending on the panel specifications, the power supply circuit 803 may be provided with a current source.

  The CPU 802 includes a control signal generation circuit 820, a decoder 821, a register 822, an arithmetic circuit 823, a RAM 824, an interface 835 for the CPU, and the like. Various signals input to the CPU 802 via the interface 835 are once held in the register 822 and then input to the arithmetic circuit 823, the decoder 821, and the like. The arithmetic circuit 823 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 821 is decoded and input to the control signal generation circuit 820. The control signal generation circuit 820 generates a signal including various instructions based on the input signal, and a location specified in the arithmetic circuit 823, specifically, a memory 811, a transmission / reception circuit 804, an audio processing circuit 829, a controller 801, and the like. Send to.

  The memory 811, the transmission / reception circuit 804, the audio processing circuit 829, and the controller 801 operate according to the received commands. The operation will be briefly described below.

  A signal input from the keyboard 831 is sent to the CPU 802 mounted on the printed wiring board 812 via the interface 809. The control signal generation circuit 820 converts the image data stored in the VRAM 832 into a predetermined format according to the signal sent from the keyboard 831, and sends it to the controller 801.

  The controller 801 performs data processing on a signal including image data sent from the CPU 802 in accordance with the specifications of the panel, and supplies the processed signal to the panel 800. The controller 801 generates an Hsync signal, a Vsync signal, a clock signal CLK, and an AC voltage (AC Cont) based on the power supply voltage input from the power supply voltage 803 and various signals input from the CPU. Supply.

  In the transmission / reception circuit 804, a signal transmitted / received as a radio wave is processed by the antenna 833. Specifically, high-frequency signals such as an isolator, a band pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun are used. Includes circuitry. A signal including audio information among signals transmitted and received in the transmission / reception circuit 804 is sent to the audio processing circuit 829 in accordance with a command from the CPU 802.

  A signal including audio information transmitted in accordance with a command from the CPU 802 is demodulated into an audio signal by the audio processing circuit 829 and is transmitted to the speaker 828. The audio signal sent from the microphone 827 is modulated by the audio processing circuit 829 and sent to the transmission / reception circuit 804 in accordance with a command from the CPU 802.

  The controller 801, the CPU 802, the power supply circuit 803, the sound processing circuit 829, and the memory 811 can be mounted as a package of the present invention. The present invention can be applied to any circuit other than a high-frequency circuit such as an isolator, a band pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun.

In the present invention, a diagram showing a scanning path of a beam spot in crystallization of a semiconductor film and a perspective view of a package on which a chip is mounted. The figure which shows the relationship between the wavelength of a laser beam, and an absorption coefficient. The figure which shows the magnitude relationship of a beam spot. The figure which shows the structure of the laser irradiation apparatus used in crystallization. 10A and 10B illustrate a method for manufacturing a package. 10A and 10B illustrate a method for manufacturing a package. 10A and 10B illustrate a method for manufacturing a package. The flowchart of the manufacturing process of a package. The figure which shows the timing of the dicing in the manufacturing process of a package. The perspective view which shows the cross-section of a package, and sectional drawing. The perspective view which shows the cross-section of a package. Sectional drawing which shows the cross-section of a package. 4A and 4B illustrate a method for manufacturing a stacked package. 4A and 4B illustrate a method for manufacturing a stacked package. 6A and 6B are a top view and a block diagram of a module of a mobile phone that is one of electronic devices according to the present invention.

Claims (20)

A metal film, a metal oxide film, an insulating film, and a semiconductor film are sequentially stacked on the front side of the first substrate,
By irradiating the semiconductor film with laser light , the semiconductor film is crystallized,
Forming a semiconductor element using the crystallized semiconductor film;
The second substrate is bonded using a first adhesive so as to face the first substrate with the semiconductor element interposed therebetween,
A third substrate is bonded to the back side of the first substrate using a second adhesive,
By separating the metal oxide film into the metal film side and the insulating film side, the first substrate and the third substrate are removed,
An interposer is bonded to the insulating film to which a part of the metal oxide film is attached using a third adhesive,
A method for manufacturing a semiconductor device, wherein the second substrate is removed by removing the first adhesive. A metal film, a metal oxide film, an insulating film, and a semiconductor film are sequentially stacked on the front side of the first substrate,
By irradiating the semiconductor film with laser light , the semiconductor film is crystallized,
Forming a semiconductor element using the crystallized semiconductor film;
The second substrate is bonded using a first adhesive so as to face the first substrate with the semiconductor element interposed therebetween,
A third substrate is bonded to the back side of the first substrate using a second adhesive,
By separating the metal oxide film into the metal film side and the insulating film side, the first substrate and the third substrate are removed,
By bonding an interposer provided with a terminal using a third adhesive to the insulating film to which a part of the metal oxide film is attached, the terminal provided in the interposer and the semiconductor element are electrically connected. Connected to
A method for manufacturing a semiconductor device, wherein the second substrate is removed by removing the first adhesive. A metal film, a metal oxide film, an insulating film, and a semiconductor film are sequentially stacked on the front side of the first substrate,
By irradiating the semiconductor film with laser light , the semiconductor film is crystallized,
Forming a semiconductor element using the crystallized semiconductor film;
The second substrate is bonded using a first adhesive so as to face the first substrate with the semiconductor element interposed therebetween,
A third substrate is bonded to the back side of the first substrate using a second adhesive,
By separating the metal oxide film into the metal film side and the insulating film side, the first substrate and the third substrate are removed,
Removing the metal oxide film partially adhered to the insulating film;
Bonding an interposer provided with terminals using a third adhesive to the insulating film,
After removing the second substrate by removing the first adhesive,
A method for manufacturing a semiconductor device, wherein the terminal provided in the interposer and the semiconductor element are electrically connected. A metal film, a metal oxide film, an insulating film, and a semiconductor film are sequentially stacked on the front side of the first substrate,
By irradiating the semiconductor film with laser light , the semiconductor film is crystallized,
Forming a semiconductor element using the crystallized semiconductor film;
The second substrate is bonded using a first adhesive so as to face the first substrate with the semiconductor element interposed therebetween,
A third substrate is bonded to the back side of the first substrate using a second adhesive,
By separating the metal oxide film into the metal film side and the insulating film side, the first substrate and the third substrate are removed,
Bonding an interposer provided with terminals using a third adhesive to the insulating film to which a part of the metal oxide film is attached,
After removing the second substrate by removing the first adhesive,
A method for manufacturing a semiconductor device, wherein the terminal provided in the interposer and the semiconductor element are electrically connected. A metal film, a metal oxide film, an insulating film, and a semiconductor film are sequentially stacked on the front side of the first substrate,
By irradiating the semiconductor film with laser light , the semiconductor film is crystallized,
Forming a semiconductor element using the crystallized semiconductor film and a pad electrically connected to the semiconductor element;
A second substrate is bonded using a first adhesive so as to face the first substrate with the semiconductor element and the pad interposed therebetween,
A third substrate is bonded to the back side of the first substrate using a second adhesive,
By separating the metal oxide film into the metal film side and the insulating film side, the first substrate and the third substrate are removed,
Bonding an interposer provided with terminals using a third adhesive to the insulating film to which a part of the metal oxide film is attached,
After removing the second substrate by removing the first adhesive,
A method for manufacturing a semiconductor device, wherein the terminal provided in the interposer and the pad are electrically connected. A metal film, a metal oxide film, an insulating film, and a semiconductor film are sequentially stacked on the front side of the first substrate,
By irradiating the semiconductor film with laser light , the semiconductor film is crystallized,
A plurality of semiconductor elements are formed using the crystallized semiconductor film,
A second substrate is bonded using a first adhesive so as to face the first substrate with the plurality of semiconductor elements interposed therebetween,
A third substrate is bonded to the back side of the first substrate using a second adhesive,
By separating the metal oxide film into the metal film side and the insulating film side, the first substrate and the third substrate are removed,
By cutting the second substrate, the plurality of semiconductor elements are divided into respective semiconductor elements,
In each of the divided semiconductor elements, an interposer is bonded to the insulating film to which a part of the metal oxide film is attached using a third adhesive,
A method for manufacturing a semiconductor device, wherein the second substrate of each of the divided semiconductor elements is removed by removing the first adhesive. A metal film, a metal oxide film, an insulating film, and a semiconductor film are sequentially stacked on the front side of the first substrate,
By irradiating the semiconductor film with laser light , the semiconductor film is crystallized,
A plurality of semiconductor elements are formed using the crystallized semiconductor film,
A second substrate is bonded using a first adhesive so as to face the first substrate with the plurality of semiconductor elements interposed therebetween,
A third substrate is bonded to the back side of the first substrate using a second adhesive,
By separating the metal oxide film into the metal film side and the insulating film side, the first substrate and the third substrate are removed,
By cutting the second substrate, the plurality of semiconductor elements are divided into respective semiconductor elements,
In each of the divided semiconductor elements, an interposer provided with terminals using a third adhesive is bonded to the insulating film to which a part of the metal oxide film is attached, thereby separating the interposer and the divided semiconductor element. Electrically connecting each of the semiconductor elements;
A method for manufacturing a semiconductor device, wherein the second substrate of each of the divided semiconductor elements is removed by removing the first adhesive. A metal film, a metal oxide film, an insulating film, and a semiconductor film are sequentially stacked on the front side of the first substrate,
By irradiating the semiconductor film with laser light , the semiconductor film is crystallized,
A plurality of semiconductor elements are formed using the crystallized semiconductor film,
A second substrate is bonded using a first adhesive so as to face the first substrate with the plurality of semiconductor elements interposed therebetween,
A third substrate is bonded to the back side of the first substrate using a second adhesive,
By separating the metal oxide film into the metal film side and the insulating film side, the first substrate and the third substrate are removed,
An interposer is bonded to the insulating film to which a part of the metal oxide film is attached using a third adhesive,
By cutting the second substrate and the interposer, the plurality of semiconductor elements are divided into respective semiconductor elements,
A method for manufacturing a semiconductor device, wherein the second substrate of each of the semiconductor elements divided by removing the first adhesive is removed. A metal film, a metal oxide film, an insulating film, and a semiconductor film are sequentially stacked on the front side of the first substrate,
By irradiating the semiconductor film with laser light , the semiconductor film is crystallized,
A plurality of semiconductor elements are formed using the crystallized semiconductor film,
A second substrate is bonded using a first adhesive so as to face the first substrate with the plurality of semiconductor elements interposed therebetween,
A third substrate is bonded to the back side of the first substrate using a second adhesive,
By separating the metal oxide film into the metal film side and the insulating film side, the first substrate and the third substrate are removed,
By bonding an interposer provided with a terminal using a third adhesive to the insulating film to which a part of the metal oxide film is adhered, the terminal provided in the interposer and the plurality of semiconductor elements are combined. Electrically connect,
By cutting the second substrate and the interposer, the plurality of semiconductor elements are divided into respective semiconductor elements,
A method for manufacturing a semiconductor device, wherein the second substrate of each of the semiconductor elements divided by removing the first adhesive is removed. A metal film, a metal oxide film, an insulating film, and a semiconductor film are sequentially stacked on the front side of the first substrate,
By irradiating the semiconductor film with laser light , the semiconductor film is crystallized,
A plurality of semiconductor elements are formed using the crystallized semiconductor film,
A second substrate is bonded using a first adhesive so as to face the first substrate with the plurality of semiconductor elements interposed therebetween,
A third substrate is bonded to the back side of the first substrate using a second adhesive,
By separating the metal oxide film into the metal film side and the insulating film side, the first substrate and the third substrate are removed,
An interposer is bonded to the insulating film to which a part of the metal oxide film is attached using a third adhesive,
After removing the second substrate by removing the first adhesive,
A method for manufacturing a semiconductor device, wherein the semiconductor element is divided into semiconductor elements by cutting the interposer. A metal film, a metal oxide film, an insulating film, and a semiconductor film are sequentially stacked on the front side of the first substrate,
By irradiating the semiconductor film with laser light , the semiconductor film is crystallized,
A plurality of semiconductor elements are formed using the crystallized semiconductor film,
A second substrate is bonded using a first adhesive so as to face the first substrate with the plurality of semiconductor elements interposed therebetween,
A third substrate is bonded to the back side of the first substrate using a second adhesive,
By separating the metal oxide film into the metal film side and the insulating film side, the first substrate and the third substrate are removed,
By bonding an interposer provided with a terminal using a third adhesive to the insulating film to which a part of the metal oxide film is adhered, the terminal provided in the interposer and the plurality of semiconductor elements are combined. Electrically connect,
After removing the second substrate by removing the first adhesive,
A method for manufacturing a semiconductor device, wherein the semiconductor element is divided into semiconductor elements by cutting the interposer. In any one of Claims 1 thru | or 11 ,
A method for manufacturing a semiconductor device, wherein the metal oxide film is crystallized by heat treatment when forming the semiconductor element. In any one of Claims 1 to 12 ,
The method for manufacturing a semiconductor device, wherein the metal oxide film is formed by oxidizing a surface of the metal film. In any one of Claims 1 thru | or 13,
When crystallizing the semiconductor film, by irradiating the semiconductor film with the pulsed first laser light and the continuously oscillated second laser light so that their irradiation regions overlap each other, A method for manufacturing a semiconductor device, wherein the semiconductor film is crystallized. In claim 14 ,
The method for manufacturing a semiconductor device, wherein the first laser light has a wavelength of an absorption coefficient of 1 × 10 ⁴ cm ⁻¹ or more for the semiconductor film. In claim 14 or 15 ,
The method for manufacturing a semiconductor device, wherein the first laser beam has a second harmonic. In any one of Claims 14 thru | or 16 ,
The method for manufacturing a semiconductor device, wherein the second laser beam has a fundamental wave. In any one of Claim 14 thru / or Claim 17 ,
In the crystallization, the irradiation region of the first laser beam and the irradiation region of the second laser beam are moved relative to the semiconductor film, and the semiconductor element is moved in the direction of the movement. A method for manufacturing a semiconductor device, wherein the semiconductor device is formed in a region that fits in a width of the irradiation region of the second laser beam in a vertical direction. In claim 18 ,
A method for manufacturing a semiconductor device, wherein a width of an irradiation region of the second laser light in a direction perpendicular to the direction of movement is 10 mm or more and 50 mm or less. In any one of claims 14 to 19 ,
2. A method for manufacturing a semiconductor device, wherein an area of a region where the first laser irradiation region and the second laser irradiation region overlap corresponds to the second laser irradiation region.

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