JP4282062B2 - DC-DC converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a DC-DC converter that controls the switching timing of a switching element and maintains an output voltage within a predetermined range. In particular, an excessive current continuously flows from a primary-side power supply due to an unexpected situation. The present invention relates to a DC-DC converter that can avoid falling into a more serious state.
[0002]
[Prior art]
For example, a chopper type DC-DC converter intermittently supplies primary side DC power to a coil by the operation of a switching element, thereby accumulating electromagnetic energy in the coil and using energy released from the coil. Thus, for example, a boosted secondary side output (converter output) is obtained. It is important that the output voltage of the DC-DC converter is stable at a predetermined voltage value determined in advance.
[0003]
As a control method for maintaining the output voltage in a stable state, typically two methods are known. One is a PWM (pulse width modulation) system, and the other is a PFM (pulse frequency modulation) system.
[0004]
By the way, in recent years, organic EL (electroluminescence) elements using an organic material as a light emitting layer have been developed, and a light emitting display panel in which the organic EL elements are arranged in a matrix has been put into practical use. In general, a DC voltage of about 12 to 20 V is required to drive the organic EL element described above. On the other hand, when this organic EL display is adopted in a portable terminal device, for example, a mobile phone, the output voltage of the primary driving power source (battery) used for this is less than 4V, and the voltage value is insufficient. To do.
[0005]
Therefore, it is necessary to boost the voltage of the drive power supply. From the viewpoint of efficiency, it is advantageous to employ a system in which the voltage is directly boosted from the battery which is the primary power supply. Therefore, a chopper type DC-DC converter using a battery as a primary power source can be suitably used as a driving power source for a display panel using the above-described EL element.
[0006]
On the other hand, in a DC-DC converter used in this type of portable device, it is an extremely important issue to improve the conversion efficiency when converting the primary power supply as the secondary output. In particular, when it is adopted in a mobile phone as described above, the quality of the conversion efficiency has a great effect on the point of extending the standby time. In view of this, some efforts have been made to improve the utilization efficiency of the primary power supply by further reducing the power consumed by the converter itself, and the applicant has already filed an application shown in Patent Document 1.
[0007]
[Patent Document 1]
JP2003-61340 (paragraphs 0040-0043, 0051-0057, FIG. 1)
[0008]
According to the DC-DC converter disclosed in the above-mentioned Patent Document 1, an effect that power utilization efficiency can be improved, especially at light load, can be obtained, and most of the time as in the mobile phone described above. In a device in which a light load state continues for a long time such as in a standby state, it is possible to contribute to further improving the power utilization efficiency.
[0009]
By the way, in the embodiment shown in Patent Document 1, a relatively high frequency clock is required to set the pulse width by logic, and the power generated by generating such a relatively high frequency clock is required. Consumption is a problem. Therefore, a DC-DC converter using a circuit for setting the pulse width of the boosting operation from the reference waveform signal and the reference voltage generated with the operation clock extremely lowered and triggered by the rise and / or fall of the operation clock. Has also been proposed by the applicant.
[0010]
FIG. 1 is a block diagram showing the configuration. The configuration shown in FIG. 1 shows an example of a chopper type DC-DC converter, and symbol E1 indicates a battery that functions as a primary power source of the converter. The cathode terminal of the battery E1 is connected to a reference potential point (ground), and the anode terminal is connected to the temporary power input terminal Vin of the converter.
[0011]
One end of a boosting coil L1 is connected to the power input terminal Vin, and the other end of the coil L1 is connected to the drain of an n-type MOS power FET Q1 as a switching element. The source of the power FET Q1 is connected to the ground, and a diode D2 is connected between the drain and source of the power FET Q1 with the polarity shown in the drawing.
[0012]
On the other hand, the anode of the diode D1 is connected to the connection point between the coil L1 and the power FET Q1, and the cathode of the diode D1 constitutes the output terminal Vout of the converter. A voltage holding capacitor C1 is connected between the output terminal Vout and the ground, and the output voltage of the converter held by the capacitor C1 is connected to the output terminal Vout (not shown). It is comprised so that it may be supplied to.
[0013]
Therefore, when the power FET Q1 is turned on, a current flows from the terminal Vin to the coil L1, and electromagnetic energy is accumulated in the coil L1. Thereafter, when the power FET Q1 is turned off, an electromotive force is generated in the coil L1 due to the energy accumulated in the coil L1, and a current flows to the output terminal Vout side through the diode D1. This realizes a step-up DC-DC converter that generates a voltage higher than the voltage at the input terminal Vin at the output terminal Vout.
[0014]
A voltage dividing circuit 11 composed of resistance elements R1 and R2 for detecting the output voltage value of the converter is connected between the output terminal Vout and the ground. The voltage, that is, the output voltage information of the converter is configured to be supplied to the switching control circuit 12 as the switching control means.
[0015]
The switching control circuit 12 is configured to generate a switching control signal by the PWM method or the PFM method based on the divided voltage generated by the voltage dividing circuit 11 and supply it to the gate of the power FET Q1. Has been. As a result, the power FET Q1 is driven according to the output voltage of the converter, that is, a switching operation, and the secondary side voltage at the output terminal Vout can be stabilized.
[0016]
On the other hand, the switching control circuit 12 is configured to be supplied with a signal from limiting signal generating means for limiting the pulse width of the boosting operation (pulse width given to the gate of the power FET Q1) in the PWM system. Has been. In the PFM system, the switching control circuit 12 is configured to be supplied with a signal from limiting signal generating means for defining the pulse width of the boosting operation. As shown in FIG. 1, the limit signal generation means includes a clock signal generation circuit 13, a reference waveform generation circuit 14, a reference voltage generation circuit 15, and a comparator 16.
[0017]
2 and 3 are timing charts for explaining the operation of the limiting signal generating means indicated by reference numerals 13 to 16 in FIG. First, as shown in FIG. 2, the clock signal generation circuit 13 generates a clock signal (a) having a long cycle. This clock signal (a) is switched by the switching control circuit 12 by, for example, the PWM method. When the drive signal is generated, it is generated in synchronization with the generation period of the PWM signal. Further, when the switching control circuit 12 generates a switching drive signal by, for example, the PFM method, the clock signal (a) is generated in synchronization with the generation timing of the PFM signal.
[0018]
The clock signal (a) is supplied to the reference waveform generation circuit 14 as shown in FIG. 1, and the reference waveform generation circuit 14 receives the clock signal (a) as shown in FIG. At the falling timing, the reference waveform signal (c) is generated. The reference waveform signal (c) constitutes a so-called sawtooth wave whose output level sequentially increases as shown in FIG. 2, and this reference waveform signal (c) is supplied from the comparator 16 as shown in FIG. It is supplied to one input terminal (inverted input terminal). Further, the other input terminal (non-inverting input terminal) of the comparator 16 is supplied with the reference voltage Vref (b) provided from the reference voltage source 15.
[0019]
The comparator 16 turns on the SW on / off signal (d) as the drive limiting signal when the level of the reference waveform signal (c) does not reach the reference voltage Vref (b) as shown in FIG. Generates an output that is a state. The comparator 16 generates an output for turning off the SW on / off signal (d) when the level of the reference waveform signal (c) exceeds the reference voltage Vref (b). The reference waveform generation circuit 14 operates to return the reference waveform signal (c) to the zero level when the level of the reference waveform signal (c) exceeds the reference voltage Vref (b).
[0020]
For example, in the case of the PWM method, the SW on / off signal (d) is supplied to the switching control circuit 12, and the switching control circuit 12 and the PWM signal generated according to the output voltage of the converter. A logical product is taken and supplied to the gate of the power FET Q1. This acts to limit the duty of the switching drive signal supplied to the gate of the power FET Q1 when a large load is applied to the output of the converter.
[0021]
In the case of the PFM method, the SW on / off signal (d) is supplied to the switching control circuit 12 and the timing of the PFM signal generated according to the output voltage of the converter in the switching control circuit 12. Thus, the power is supplied to the gate of the power FET Q1. This acts to define the duty of the switching drive signal supplied to the gate of the power FET Q1.
[0022]
Therefore, it is possible to prevent a large current from the battery E1 from continuously flowing into the coil L1 and the power FET Q1 in the overload state of the converter, and the coil L1 and the power FET Q1 are heated to be damaged. Acts to prevent.
[0023]
[Problems to be solved by the invention]
Incidentally, in the configuration shown in FIG. 1, for example, when the reference waveform generation circuit 14 fails, the sawtooth reference waveform signal (c) is not output, or as shown in FIG. When a state such as slowness occurs, the SW on / off signal that is output from the comparator 16 is continuously turned on as shown in FIG. Such a situation also occurs because the reference voltage (b) sticks to a high level even when, for example, the ground side of the voltage dividing circuit (not shown) floats due to peeling of solder or the like in the reference voltage source 15.
[0024]
For the reasons described above, when the SW on / off signal is continuously turned on and the converter is overloaded or the output terminal is short-circuited, the duty of the switching drive signal supplied to the gate of the power FET Q1 Can not be restricted. Therefore, not only is the battery E1 consumed quickly, but the coil L1 and the power FET Q1 are heated and not only are they damaged, but in the worst case, it may lead to an unexpected situation such as smoke or fire. The
[0025]
The present invention has been made by paying attention to the above-described problems, and is configured to prevent the SW on / off signal from being continuously output due to the failure of the limit signal generating means described above. It is an object of the present invention to provide a DC-DC converter that can avoid such an unexpected situation.
[0026]
[Means for Solving the Problems]
The DC-DC converter according to the present invention made to achieve the above object generates a switching drive signal corresponding to the output voltage value of the converter and supplies the switching drive signal to the switching element. Switching control means for controlling the output voltage value to a predetermined range by supplying to the switching control means, and drive restriction signal generating means for generating a drive restriction signal that is supplied to the switching control means and restricts the driving operation of the switching element. The drive limit signal generating means includes a comparator for comparing a reference waveform signal generated based on a clock signal and a reference voltage, and a drive signal detection means for generating the drive limit signal based on the comparator output and the clock signal. It is characterized in that is provided .
[0027]
DETAILED DESCRIPTION OF THE INVENTION
A preferred embodiment of a DC-DC converter according to the present invention will be described below with reference to the drawings. 4 and 5 are block diagrams showing the embodiment. In FIG. 4, portions corresponding to the components shown in FIG. 1 already described are denoted by the same reference numerals, and therefore detailed description thereof is omitted as appropriate.
[0028]
In FIG. 4, reference numeral 17 denotes a drive signal pulse end detection circuit constituting a part of the drive limit signal generation means, that is, a drive signal detection means. The pulse end detection circuit 17 is configured to be supplied with a clock signal from the clock signal generation circuit 13 and an output from the comparator 16. On the other hand, the comparator 16 is supplied with the reference voltage Vref and sawtooth reference waveform signal shown in FIGS. 6B and 6C, respectively, and the comparator output shown in FIG. 6D is generated.
[0029]
That is, this comparator output falls when the level of the reference waveform signal exceeds the reference voltage Vref. At this time, since the level of the reference waveform signal (c) is made zero, the comparator output (d) results in a signal waveform that instantaneously falls in a spike shape and immediately returns to the original level.
[0030]
FIG. 5 shows an example of the pulse end detection circuit 17, which includes a T-type flip-flop 19, a D-type flip-flop 20, and an AND gate 21. The T-type flip-flop 19 is provided with a reset terminal and an inversion reset terminal, and a clock signal shown in FIG. 6A is supplied to these reset terminals. Therefore, the T-type flip-flop 19 is reset at the rise and fall of the clock signal.
[0031]
A positive voltage “H” is supplied to the T input of the T-type flip-flop 19, and the comparator output (d) is supplied to the clock input CK. Therefore, the T-type flip-flop 19 inverts the output state of the Q terminal and the inverted Q terminal at the timing when the comparator output (d) is supplied to the clock input CK, and at the same time, by the rising and falling of the clock signal, An operation for returning to the state is performed. Accordingly, the SW on / off signal (g) as the drive signal shown in FIG. 6 is output from the inverted Q terminal of the T-type flip-flop 19, and the inverted signal (e) is output from the Q terminal.
[0032]
On the other hand, the inverted signal (e) is supplied to the D input of the D-type flip-flop 20. The D-type flip-flop 20 includes a clock input terminal CK and an inverted clock input terminal CK, and a clock signal (a) is supplied to both. Therefore, the D-type flip-flop 20 outputs the D input at the rise and fall of the clock signal (a), that is, the state of the inverted signal (e) from the Q terminal, and as a result, from the Q terminal. Outputs a boost on / off signal shown in FIG.
[0033]
Then, the boost on / off signal (f) and the SW on / off signal (g) shown in FIG. 6 are input to the AND gate 20, and the drive limit signal (h) is output from the AND gate 20.
[0034]
Thus to, in the normal operating condition as shown in FIG. 6, the same drive limiting signal SW ON / OFF signal (g) (h) is supplied to the switching control circuit 12 shown in FIG. 4 become. The drive limit signal (h) is logically ANDed with, for example, a PWM signal generated according to the output voltage of the converter, and supplied to the gate of the power FET Q1. This acts to limit the duty of the switching drive signal supplied to the gate of the power FET Q1 when a large load is applied to the output of the converter.
[0035]
By the way, when the reference waveform signal (c) having a sawtooth waveform is not output due to, for example, a failure of the reference waveform generation circuit 14 in an abnormal operation state as described above, or as shown in FIG. When a state such as being very slow occurs, the output of the comparator 16 in FIG. 4 is in the state shown in FIG.
[0036]
According to this, the SW on / off signal (g) shown in FIG. 7 is output to the ON state from the inverting Q terminal of the T-type flip-flop 19 shown in FIG. 5, but in response to the fall of the clock signal (a). Reset. On the other hand, the Q output terminal of the D-type flip-flop 20 outputs from the Q output terminal of the D-type flip-flop 20 in order to output the state of the inverted signal (e) shown in FIG. 7 when the clock signal (a) falls. As shown in FIG. 7F, the step-up on / off signal is turned from ON to OFF.
[0037]
Then, the boost on / off signal (f) and the SW on / off signal (g) shown in FIG. 7 are input to the AND gate 20, and the drive limit signal (h) is output from the AND gate 20.
[0038]
Therefore, in the state shown in the timing chart of FIG. 7, the output of the drive limiting signal (h) disappears (becomes low level) at the rising or falling timing of the clock signal (a). Since this drive limiting signal (h) is logically ANDed with, for example, a PWM signal generated according to the output voltage of the converter as described above, the switching drive signal is prevented from being supplied to the gate of the power FET Q1. The That is, the power FET Q1 is forcibly turned off, thereby stopping the conversion operation.
[0039]
Therefore, when an overload is further applied to the converter in a state where, for example, the reference waveform generation circuit 14 or the like in the abnormal operating state is faulty, the converter is in a more serious state as described above. Can be effectively avoided.
[0040]
In the embodiment described above, the drive limit signal generating means generates the reference waveform signal at both the rising and falling timings of the clock signal, and performs the logic control based on this. The clock signal cycle shown in FIG. 6A may be halved, the reference waveform signal may be generated only at the rising timing of the clock signal, and the same logic control may be performed.
[0041]
In the embodiment described above, a converter adopting a chopper type boosting type is illustrated, but a step-down type, an inverting type, and a flyback type DC in which energy is transmitted with the switching element turned off. The present invention can also be adopted for a DC converter.
[0042]
In addition, in the above-described embodiment, the output from the coil is led to the output terminal via the diode. However, a switching element such as a transistor is used instead of the diode, and the on / off timing is determined by the switching element. The present invention can also be applied to a so-called synchronous rectification method for controlling the current.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a conventional DC-DC converter.
FIG. 2 is a timing chart showing an operation in a normal state of the converter shown in FIG.
FIG. 3 is a timing chart showing an operation when the converter shown in FIG. 1 is abnormal.
FIG. 4 is a block diagram showing an embodiment of a DC-DC converter according to the present invention.
5 is a block diagram showing an example of a pulse end detection circuit that constitutes a part of limit signal generation means in the converter shown in FIG. 4; FIG.
6 is a timing chart showing an operation of the converter shown in FIG. 4 in a normal state.
7 is a timing chart showing an operation when the converter shown in FIG. 4 is abnormal. FIG.
[Explanation of symbols]
11 Voltage Dividing Circuit 12 Switching Control Circuit 13 Clock Signal Generating Circuit 14 Reference Waveform Generating Circuit 15 Reference Voltage Generating Circuit 16 Comparator 17 Pulse End Detection Circuit 19 T Type Flip Flop 20 D Type Flip Flop 21 AND Gate C1 Capacitor D1, D2 Diode E1 Battery (primary power supply)
L1 Boost coil Q1 Switching element R1, R2 Resistor element Vin Power input terminal Vout Output terminal

Claims (3)

Switching control means for generating a switching drive signal corresponding to the output voltage value of the converter, and supplying the switching drive signal to the switching element to control the output voltage value within a predetermined range; and being supplied to the switching control means, Drive limit signal generating means for generating a drive limit signal for limiting the drive operation of the switching element,
The drive limit signal generation means includes a comparator that compares a reference waveform signal generated based on a clock signal and a reference voltage, and a drive signal detection means that generates the drive limit signal based on the comparator output and the clock signal. DC-DC converter, characterized in that it is. 2. The DC-DC converter according to claim 1, wherein the drive restriction signal is generated at a timing of rising and / or falling of the clock signal. 2. The DC-DC converter according to claim 1, wherein the clock signal is synchronized with a generation timing of a switching drive signal generated in the switching control means.

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