JP2004304862A - Dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid a converter falling in a serious condition, when a trouble occurs in one part of a control circuit and that an output of a converter becomes overloaded, in addition to it. <P>SOLUTION: The output voltage of a converter is acquired by a voltage-dividing circuit 11, and it is supplied to a switching control circuit 12, whereby the drive action of a switching element Q1 is controlled. Hereby, the voltage boosted by a coil L1 is brought to an output terminal Vout. To the switching control circuit 12 a drive-limiting signal for limiting the drive action of the switching element Q1 is supplied by a pulse finish detecting circuit 17. For this drive-limiting signal, for example, AND is taken between itself and a PWM-signal generated in the switching circuit 12, and it is supplied to a gate of the power FET Q1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a DC-DC converter that controls the switching timing of a switching element to maintain an output voltage within a predetermined range, and particularly to a converter that causes an excessive current to flow from a primary-side power supply due to an unexpected situation. The present invention relates to a DC-DC converter capable of avoiding a more serious state.
[0002]
[Prior art]
For example, a chopper-type DC-DC converter supplies DC power on the primary side intermittently to a coil by the operation of a switching element, thereby accumulating electromagnetic energy in the coil and using energy released from the coil. Then, for example, a boosted secondary output (converter output) is obtained. It is important that the output voltage of this DC-DC converter be stable at a predetermined voltage value.
[0003]
As a control method for keeping the output voltage in a stable state, there are typically two control methods. One is a PWM (pulse width modulation) system, and the other is a PFM (pulse frequency modulation) system.
[0004]
By the way, in recent years, organic EL (electroluminescence) elements using an organic material for a light emitting layer have been developed, and a light emitting display panel in which the elements are arranged in a matrix has been partially used. In general, a DC voltage of about 12 to 20 V is required to drive the organic EL element for lighting. On the other hand, when this organic EL display is used in a portable terminal device, for example, a mobile phone, the output voltage of a primary-side driving power supply (battery) used for this is slightly less than 4 V, and the voltage value is insufficient. I do.
[0005]
Therefore, it is necessary to increase the voltage of the driving power supply, but from the viewpoint of efficiency, it is more advantageous to adopt a method of directly increasing the voltage from the battery which is the primary power supply. Therefore, a chopper type DC-DC converter using a battery as a primary side power supply can be suitably used as a drive power supply for a display panel using the above-described EL element.
[0006]
On the other hand, in a DC-DC converter used in this type of portable device, it is a very important task to increase the conversion efficiency when converting a primary power supply into a secondary output. In particular, in the case of adopting the above-mentioned portable telephone, the quality of the conversion efficiency has a great effect in extending the standby time. Therefore, various measures have been taken to improve the utilization efficiency of the primary side power supply by further reducing the power consumed by the converter itself, and the applicant of the present application has already filed an application shown in Patent Document 1.
[0007]
[Patent Document 1]
JP-A-2003-61340 (paragraphs 0040 to 0043, 0051 to 0057, FIG. 1)
[0008]
According to the DC-DC converter disclosed in Patent Document 1, the effect of improving the power use efficiency can be obtained, especially at a light load, and almost the same time as in the above-mentioned mobile phone. In a device in which the light load state continues for a long time as in the standby state, it can contribute to further improving the power use efficiency.
[0009]
By the way, in the embodiment shown in Patent Document 1, a clock having a relatively high frequency is required to set the pulse width by logic, and power generated by generating such a clock having a relatively high frequency is required. Consumption is a problem. Therefore, a DC-DC converter using a circuit that extremely lowers the operation clock and sets a pulse width of a boosting operation from a reference waveform signal and a reference voltage generated with the rise and / or fall of the operation clock as a trigger. Has been proposed by the present applicant.
[0010]
FIG. 1 is a block diagram showing the configuration. The configuration shown in FIG. 1 shows an example of a chopper type DC-DC converter, and reference numeral E1 indicates a battery functioning as a primary power supply of the converter. The cathode side terminal of the battery E1 is connected to a reference potential point (earth), and the anode side terminal is connected to the temporary power input terminal Vin of the converter.
[0011]
One end of a step-up coil L1 is connected to the power input terminal Vin, and the other end of the coil L1 is connected to the drain of an n-type MOS power FET Q1 as a switching element. The source of the power FET Q1 is connected to the ground, and a diode D2 is connected between the drain and the source of the power FET Q1 with the polarity shown in the figure.
[0012]
On the other hand, an anode of a diode D1 is connected to a connection point between the coil L1 and the power FET Q1, and a cathode of the diode D1 forms an output terminal Vout of the converter. A voltage holding capacitor C1 is connected between the output terminal Vout and the ground, and the output voltage of the converter held by the capacitor C1 is connected to a load (not shown) connected to the output terminal Vout. Is configured to be supplied.
[0013]
Therefore, when the power FET Q1 is turned on, a current flows from the terminal Vin to the coil L1, and electromagnetic energy is accumulated in the coil L1. Thereafter, when the power FET Q1 is turned off, an electromotive force is generated in the coil L1 by the energy stored in the coil L1, and a current flows to the output terminal Vout through the diode D1. Thus, a step-up DC-DC converter in which a voltage higher than the voltage of the input terminal Vin is generated at the output terminal Vout is realized.
[0014]
Between the output terminal Vout and the ground, a voltage dividing circuit 11 composed of resistance elements R1 and R2 for detecting the output voltage value of the converter is connected. The voltage, that is, output voltage information of the converter is configured to be supplied to a switching control circuit 12 as switching control means.
[0015]
The switching control circuit 12 generates a switching control signal based on the divided voltage generated by the voltage dividing circuit 11 according to the PWM method or the PFM method, and supplies the switching control signal to the gate of the power FET Q1. Have been. As a result, the power FET Q1 performs a driving operation in accordance with the output voltage of the converter, that is, a switching operation, so that the secondary voltage at the output terminal Vout can be stabilized.
[0016]
On the other hand, in the PWM method, the switching control circuit 12 is supplied with a signal from a limiting signal generating means for limiting the pulse width of the boosting operation (the pulse width applied to the gate of the power FET Q1) in the PWM method. Have been. Further, in the PFM system, the switching control circuit 12 is configured to be supplied with a signal from a limiting signal generation unit that defines the pulse width of the boost operation. As shown in FIG. 1, the limiting signal generating means includes a clock signal generating circuit 13, a reference waveform generating circuit 14, a reference voltage generating circuit 15, and a comparator 16.
[0017]
FIG. 2 and FIG. 3 are timing charts for explaining the operation of the restriction signal generating means indicated by reference numerals 13 to 16 in FIG. First, as shown in FIG. 2, the clock signal generation circuit 13 generates a clock signal (a) having a long cycle, and the clock signal (a) is switched by the switching control circuit 12 by, for example, a PWM method. When the drive signal is generated, the drive signal is generated in synchronization with the generation cycle of the PWM signal. When the switching control circuit 12 generates a switching drive signal by, for example, the PFM method, the clock signal (a) is generated in synchronization with the generation timing of the PFM signal.
[0018]
The clock signal (a) is supplied to the reference waveform generation circuit 14 as shown in FIG. 1, and the reference waveform generation circuit 14 receives the clock signal (a) as shown in FIG. At the falling timing, a reference waveform signal (c) is generated. The reference waveform signal (c) forms a so-called sawtooth wave whose output level sequentially increases as shown in FIG. 2, and this reference waveform signal (c) is generated by the comparator 16 as shown in FIG. It is supplied to one input terminal (inverted input terminal). The other input terminal (non-inverting input terminal) of the comparator 16 is supplied with the reference voltage Vref (b) provided from the reference voltage source 15.
[0019]
When the level of the reference waveform signal (c) does not reach the reference voltage Vref (b) as shown in FIG. 2, the comparator 16 turns on the SW on / off signal (d) as the drive restriction signal. Generate an output to state. Further, the comparator 16 generates an output that turns off the SW on / off signal (d) when the level of the reference waveform signal (c) exceeds the reference voltage Vref (b). The reference waveform generation circuit 14 operates to return the reference waveform signal (c) to a zero level when the level of the reference waveform signal (c) exceeds the reference voltage Vref (b).
[0020]
For example, in the case of the PWM method, the SW on / off signal (d) is supplied to the switching control circuit 12, and the switching on / off signal (d) is generated by the switching control circuit 12 with the PWM signal generated according to the output voltage of the converter. The logical product is taken and supplied to the gate of the power FET Q1. Thus, when a large load is applied to the output of the converter, the duty of the switching drive signal supplied to the gate of the power FET Q1 is limited.
[0021]
In the case of the PFM method, the SW on / off signal (d) is supplied to the switching control circuit 12, and the timing of the PFM signal generated in the switching control circuit 12 according to the output voltage of the converter. Thus, the power is supplied to the gate of the power FET Q1. This acts to regulate the duty of the switching drive signal supplied to the gate of the power FET Q1.
[0022]
Therefore, when the converter is overloaded, it is possible to prevent a large current from the battery E1 from continuing to flow through the coil L1 and the power FET Q1, thereby preventing the coil L1 and the power FET Q1 from being heated and causing damage. Acts to prevent.
[0023]
[Problems to be solved by the invention]
By the way, in the configuration shown in FIG. 1, when the reference waveform signal (c) of the sawtooth waveform is not output due to a failure of the reference waveform generation circuit 14, for example, as shown in FIG. When a state such as slowness occurs, the SW on / off signal output from the comparator 16 is continuously turned on as shown in FIG. Such a situation similarly occurs, for example, when the ground side of the voltage dividing circuit (not shown) in the reference voltage source 15 floats due to peeling of solder or the like, because the reference voltage (b) sticks to a high level.
[0024]
If the SW limit signal is continuously turned on for the reason described above and the converter is overloaded or the output terminal is short-circuited, the duty of the switching drive signal supplied to the gate of the power FET Q1 is limited. You can't do that. Therefore, not only is the consumption of the battery E1 accelerated, but also the coil L1 and the power FET Q1 are heated, which may cause not only the damage but also an unexpected situation such as smoke or ignition in the worst case. You.
[0025]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and is configured so as to prevent continuous output of a SW on / off signal due to a failure of the above-described limit signal generation means. It is an object of the present invention to provide a DC-DC converter capable of avoiding such an unexpected situation.
[0026]
[Means for Solving the Problems]
A DC-DC converter according to the present invention, which has been made to achieve the above object, generates a switching drive signal according to an output voltage value of the converter as described in claim 1, and supplies the drive signal to a switching element. Switching control means for controlling the output voltage value within a predetermined range by providing the switching control means, and drive restriction signal generation means for generating a drive restriction signal which is supplied to the switching control means and restricts the driving operation of the switching element. The drive limiting signal generating means uses a comparator output generated by comparing a reference waveform signal generated based on a clock signal with a reference voltage, and performs the drive by logical control of the comparator output and the clock signal. The feature is that a limit signal is generated.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of a DC-DC converter according to the present invention will be described with reference to the drawings. FIG. 4 and FIG. 5 show the embodiment by a block diagram. In FIG. 4, portions corresponding to the respective components shown in FIG. 1 already described are denoted by the same reference numerals, and therefore, detailed description thereof will be appropriately omitted.
[0028]
In FIG. 4, reference numeral 17 denotes a drive signal pulse end detection circuit constituting a part of the limit signal generation means, that is, a drive signal detection means. The pulse end detection circuit 17 is configured to be supplied with a clock signal from the clock signal generation circuit 13 and also supplied with an output from the comparator 16. On the other hand, the comparator 16 is supplied with the reference voltage Vref and the sawtooth reference waveform signal shown in FIGS. 6B and 6C, respectively, and generates a comparator output shown in FIG. 6D.
[0029]
That is, the output of the comparator falls when the level of the reference waveform signal exceeds the reference voltage Vref. At this time, since the level of the reference waveform signal (c) is set to zero level, the comparator output (d) instantaneously falls in a spike shape, and has a signal waveform immediately returning to the original level.
[0030]
FIG. 5 shows an example of the pulse end detection circuit 17, which is composed of a T-type flip-flop 19, a D-type flip-flop 20, and an AND gate 21. The T-type flip-flop 19 has a reset terminal and an inverted reset terminal, and a clock signal shown in FIG. 6A is supplied to these reset terminals. Therefore, T-type flip-flop 19 is reset at the rise and fall of the clock signal.
[0031]
The T input of the T-type flip-flop 19 is supplied with the positive voltage “H”, and the clock input CK is supplied with the comparator output (d). Therefore, at the timing when the comparator output (d) is supplied to the clock input CK, the T-type flip-flop 19 inverts the output states of the Q terminal and the inverted Q terminal, and at the same time, by the rising and falling of the clock signal, An operation for returning to the state is performed. Accordingly, the SW on / off signal (g) as a drive signal shown in FIG. 6 is output from the inverted Q terminal of the T-type flip-flop 19, and the inverted signal (e) is output from the Q terminal.
[0032]
On the other hand, the D input of the D-type flip-flop 20 is supplied with the inverted signal (e). The D-type flip-flop 20 is provided with a clock input terminal CK and an inverted clock input terminal CK, both of which are supplied with a clock signal (a). Therefore, the D-type flip-flop 20 outputs the D input at the time of rising and falling of the clock signal (a), that is, the state of the inverted signal (e) from the Q terminal. Outputs the boosting on / off signal shown in FIG.
[0033]
Then, the boosting on / off signal (f) and the SW on / off signal (g) shown in FIG. 6 are input to the AND gate 20, and the AND gate 20 outputs the drive restriction signal (h).
[0034]
Thus, as shown in FIG. 6, when the limit signal generating means is in a normal operation state, the same drive limit signal (h) as the SW on / off signal (g) is supplied to the switching control circuit 12 shown in FIG. Will be supplied. The drive limiting signal (h) is ANDed with, for example, a PWM signal generated according to the output voltage of the converter, and is supplied to the gate of the power FET Q1. Thus, when a large load is applied to the output of the converter, the duty of the switching drive signal supplied to the gate of the power FET Q1 is limited.
[0035]
By the way, as described above, when the reference waveform signal (c) in the sawtooth waveform is not output due to, for example, the failure of the reference waveform generation circuit 14 in the limit signal generation means, or as shown in FIG. When a state such as a very slow state occurs, the output of the comparator 16 in FIG. 4 becomes the state shown in FIG. 7D.
[0036]
According to this, the SW on / off signal (g) shown in FIG. 7 is output to the ON state from the inverted Q terminal of the T-type flip-flop 19 shown in FIG. 5, but due to the falling of the clock signal (a). Reset. On the other hand, the Q output terminal of the D-type flip-flop 20 is connected to the Q output terminal of the D-type flip-flop 20 to output the state of the inverted signal (e) shown in FIG. 7 when the clock signal (a) falls. Is turned from ON to OFF as shown in FIG. 7 (f).
[0037]
Then, the boost on / off signal (f) and the SW on / off signal (g) shown in FIG. 7 are input to the AND gate 20, and the AND gate 20 outputs the drive restriction signal (h).
[0038]
Therefore, in the state shown in the timing chart of FIG. 7, the output of the drive limiting signal (h) disappears (becomes low level) at the rising or falling timing of the clock signal (a). Since the drive limiting signal (h) is ANDed with, for example, a PWM signal generated according to the output voltage of the converter as described above, the supply of the switching drive signal to the gate of the power FET Q1 is prevented. You. That is, the power FET Q1 is forcibly turned off, thereby stopping the conversion operation.
[0039]
Therefore, if the converter is overloaded while a fault has occurred in, for example, the reference waveform generating circuit 14 in the above-described limited signal generating means, the converter may become in a more serious state as described above. Can be effectively avoided.
[0040]
In the embodiment described above, the limiting signal generating means generates the reference waveform signal at both the rising and falling timings of the clock signal, and performs the logic control based on the reference waveform signal. The cycle of the clock signal shown in FIG. 6A may be halved, the reference waveform signal may be generated only at the timing of the rise of the clock signal, and similar logic control may be performed.
[0041]
Further, in the above-described embodiment, the converter adopting the chopper type boosting type is exemplified. However, a step-down type, an inverting type, and a flyback type DC in which energy is transmitted when the switching element is in an off state. The present invention can be applied to a DC converter.
[0042]
In addition, in the above-described embodiment, the output of the coil is led to the output terminal via the diode, but a switching element such as a transistor is used instead of the diode, and the on / off timing is set by the switching element. The present invention can also be applied to a so-called synchronous rectification system for controlling
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a conventional DC-DC converter.
FIG. 2 is a timing chart showing a normal operation of the converter shown in FIG. 1;
FIG. 3 is a timing chart showing an operation of the converter shown in FIG. 1 at the time of abnormality.
FIG. 4 is a block diagram showing an embodiment of a DC-DC converter according to the present invention.
FIG. 5 is a block diagram showing an example of a pulse end detection circuit constituting a part of a limiting signal generation means in the converter shown in FIG.
6 is a timing chart showing an operation of the converter shown in FIG. 4 in a normal state.
FIG. 7 is a timing chart showing an operation of the converter shown in FIG. 4 when an abnormality occurs.
[Explanation of symbols]
Reference Signs List 11 voltage dividing circuit 12 switching control circuit 13 clock signal generation circuit 14 reference waveform generation circuit 15 reference voltage generation circuit 16 comparator 17 pulse end detection circuit 19 T-type flip-flop 20 D-type flip-flop 21 AND gate C1 capacitors D1, D2 diode E1 Battery (primary power supply)
L1 Boosting coil Q1 Switching element R1, R2 Resistance element Vin Power input terminal Vout Output terminal

Claims (7)

A switching control means for generating a switching drive signal corresponding to the output voltage value of the converter and providing the drive signal to a switching element to control the output voltage value within a predetermined range; Drive limiting signal generating means for generating a drive limiting signal for limiting the driving operation of the element,
The drive limiting signal generating means uses a comparator output generated by comparing a reference waveform signal generated based on a clock signal with a reference voltage, and performs the drive limiting by logical control of the comparator output and the clock signal. A DC-DC converter for generating a signal. The drive restriction signal generation means includes a drive signal detection means for detecting a drive signal, and detects the drive signal by logical control of the comparator output and the clock signal to generate the drive restriction signal. The DC-DC converter according to claim 1, wherein: 3. The DC-DC converter according to claim 1, wherein the switching element is forcibly turned off by the drive restriction signal. 3. The DC-DC converter according to claim 1, wherein the switching element is forcibly turned off by the drive restriction signal, and the conversion operation of the converter is stopped. 4. 5. The DC-DC converter according to claim 1, wherein the drive restriction signal is generated at a timing of a rise and / or a fall of the clock signal. 6. 5. The DC-DC converter according to claim 1, wherein the clock signal is synchronized with a generation timing of a switching drive signal generated by the switching control unit. By turning on the switching element, a current is supplied to the coil from the DC power supply on the primary side to perform an operation of storing electromagnetic energy, and by turning off the switching element, the energy stored in the coil is released. The DC-DC converter according to any one of claims 1 to 6, wherein the secondary-side output voltage is configured to be boosted.

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