JP4261107B2 - Substrate processing equipment - Google Patents

Description

に上記計算により得られたＣＤ値を代入することにより補正現像時間が決定される。このように求められた現像時間で上記のように現像処理することにより、所望の線幅のレジストパターンを現像することができる。
【００７４】
このように、レジストパターンを形成する際に影響を及ぼす、「露光処理終了後からポストエクスポージャーベーキングユニット（ＰＥＢ）における加熱処理が開始されるまでの時間ｘ」と、「プリベーキングユニット（ＰＡＢ）における待機時間ｙ」と、「塗布現像処理装置内の温度ｚ」と、「塗布現像処理装置内の気圧ｗ」とをパラメータとする線幅モデルを予め作成しておき、この線幅モデルに基づいて、現像処理条件の１つである現像時間ｔを制御することにより線幅を予測することができる。また、一旦、上記線幅モデルを作成しておくことにより、これに基づいて解析を行えば、実際の製品ウェハを製造する場合においても動的にフィードフォワード制御が可能となる。これにより精密な線幅の制御を行うことができ、歩留まりの向上が図れる。
【００７５】
また、複数ある現像処理条件、例えば現像時間、現像液の濃度又は現像液の温度等のうち最も制御しやすい現像時間を制御することにより、容易に線幅を制御できる。
【００７６】
また、これらパラメータのうちｘ及びｙは時間に関するパラメータであるため、このような線幅の制御はウェハごとに行うことは、本実施形態に係る枚葉処理の装置にとってはウェハごとに当該時間が異なることを考慮すると効果的である。
【００７７】
また、本実施形態においては、オーバーレイ検査装置４７、膜厚検査装置４８及び線幅検査装置４９をインラインとして主ウェハ搬送装置Ａ２により基板を搬送可能としたので、これら各検査を実際の製品ウェハの製造段階で動的に自動化して行うことができる。これにより、例えば、これらの各検査結果に基づきフィードフォワードやフィードバック等の制御が可能となる。
【００７８】
更に、上記線幅モデルは、レジストの種類、又は目標膜厚に応じて作成することにより、例えばレジストの濃度や粘度等の違いに応じて線幅モデルを作成することができるので、これらレジストの種類、又は目標膜厚に応じて現像処理条件を制御することができる。これは、次に説明する膜厚制御の場合も同様である。
【００７９】
図１６は、図１１に示した膜厚モデル格納部６５に格納されるデータを示している。この膜厚モデルは、上記気圧ｐと、カップ温度ｑと、湿度ｒとを用いて、上記線幅モデルと同様に、
膜厚モデルＴ＝ｅｐ＋ｆｑ＋ｇｒ＋ｉ（ｅ，ｆ，ｇ，ｉは定数）
と表すことができる。このようなモデル式で実際に形成されるであろう膜厚を求め、予測することができる。そして、レジスト膜形成時におけるウェハの回転数と膜厚との関係は予め実験により求められており、例えば図１７に示すような関係で表される。これにより所望のウェハの回転数が得られる。一例として、Ｔ＝４０５０Å（４０５ｎｍ）であって、目標膜厚が４０００Å（４００ｎｍ）である場合に、３５００ｒｐｍであったウェハの回転数を３７００ｒｐｍとすることにより目標膜厚４０００Å（４００ｎｍ）を達成できる。
【００８０】
このように、レジスト膜を形成する際に影響を及ぼす、「気圧ｐ」と、「カップＣＰの温度ｑ」と、「ユニット内の湿度ｒ」とをパラメータとする膜厚モデルを予め作成しておき、この膜厚モデルに基づいて、レジスト膜形成条件の１つであるウェハの回転数を制御することにより、フィードフォワード制御が可能となる。すなわち、従来においては、気圧、カップＣＰの温度及び湿度等のデータは膜厚制御には用いられていなかったが、本実施形態ではこれらのパラメータを用いて膜厚を予測することにより、精密な膜厚の制御を行うことができる。これにより歩留まりの向上にも寄与する。
【００８１】
また、複数あるレジスト膜形成条件、例えばウェハ回転数、レジスト液の温度、レジスト液の供給量又はレジストの吐出速度等のうち最も制御しやすいウェハの回転数を制御することにより、容易に膜厚を制御できる。
【００８２】
また、これらのパラメータｐ，ｑ，ｒには時間に関するものはないので、ウェハごとに膜厚を管理する必要はなく、例えばロット単位で最初にダミーウェハを処理する、いわゆるロット先行処理でよい。
【００８３】
図１８は、ポストエクスポージャーベーキングユニット（ＰＥＢ）における加熱温度と、レジストパターンの線幅との関係を示している。これにより、加熱温度が高いほど線幅が細くなる傾向にあることがわかる。これによって、図１４に示す場合と同様に、現像処理条件を制御する代わりに、上記線幅モデルを用いてポストエクスポージャーベーキングユニット（ＰＥＢ）における加熱温度を制御することにより、線幅をフィードフォワードで精密に制御できる。また、このような加熱温度の制御と現像時間の制御とを両方行うことにより、更に高精度に線幅を制御することができる。
【００８４】
図１９も同様に、プリベーキングユニット（ＰＡＢ）における加熱温度と、レジスト膜厚との関係を示している。これにより、加熱温度が高いほど膜厚が小さくなる傾向にあることがわかる。これによって、図１７に示す場合と同様に、ウェハの回転数を制御する代わりに、上記膜厚モデルを用いプリベーキングユニット（ＰＡＢ）における加熱温度を制御することにより、膜厚をフィードフォワードで精密に制御できる。また、このような加熱温度の制御とウェハ回転数の制御とを両方行うことにより、更に高精度に線幅を制御することができる。
【００８５】
更に本実施形態においては、線幅と膜厚との関連性については述べなかったが、この関連性が分かれば、更にこの関連性に基づいて線幅及び膜厚の制御を精密に行うことができる。
【００８６】
本発明は以上説明した実施形態には限定されるものではなく、種々の変形が可能である。
【００８７】
例えば、上記実施形態では、線幅制御では現像時間及び加熱温度のうち少なくとも一方を制御するようにし、膜厚制御ではウェハ回転数及び加熱温度のうち少なくとも一方を制御するようにしたが、これに限らず、ベーキングユニット（ＢＡＫＥ）、加熱ユニット（ＨＰ）１１３等における加熱処理温度、あるいは冷却処理ユニット（ＣＰＬ）、受け渡し・冷却処理ユニット（ＴＣＰ）における冷却温度等をも制御することにより更に高精度な線幅制御を行うことができる。
【００８８】
また、線幅を制御する場合に現像処理条件として現像時間を制御するだけでなく、現像液の濃度及び温度等を制御するようにしてもよい。あるいは、膜厚を制御する場合にレジスト膜形成条件としてウェハの回転数を制御するだけでなく、レジストの温度やノズルからのレジストの吐出速度等を制御するようにしてもよい。
【００８９】
更には、現像時間、ウェハ回転数及び加熱処理温度を補正する代わりに、線幅に関しては、図１３における時間ｘ，ｙや装置１内の温度ｚ、気圧ｗを補正するようにして所望の線幅が得られるようにしてもよいし、膜厚に関しては図１６に示す気圧ｐ，カップ温度ｑ，湿度ｒ等を補正するようにして所望の膜厚のレジスト膜を形成できるようにしてもよい。
【００９０】
また、図１８及び図１９に示したポストエクスポージャーベーキングユニット（ＰＥＢ）及びプリベーキングユニット（ＰＡＢ）における加熱温度の制御のみに限らず、加熱時間や昇温速度等をも制御することも可能であり、また冷却処理ユニット（ＣＰＬ）における冷却温度や冷却時間、あるいは降温速度等を制御することも可能である。
【００９１】
また、露光装置１００（図１参照）における露光処理条件をも塗布現像処理装置１側の集中制御部８で制御するようにしてもよい。この場合、例えば、露光量と線幅との関係については逆比例的な相関関係があることがわかっているので、この露光量をフィードフォワードで制御することにより、所望の線幅を有するレジストパターンを得ることができる。また、露光量だけでなく、露光フォーカス値をも制御するようにしてもよい。
【００９２】
また、例えばエッチング装置を塗布現像処理装置１に対してインライン化し、このエッチング処理条件をも集中制御部８で制御するようにしてもよい。この場合、例えば、エッチング時間と線幅との関係については逆比例的な相関関係があることがわかっているので、このエッチング時間をフィードフォワードで制御することにより、所望の線幅を有するパターンを得ることができる。
【００９３】
更に、上記実施形態では半導体ウェハを用いた場合について説明したが、これに限らず液晶ディスプレイ等に使用されるガラス基板についても本発明は適用可能である。
【００９４】
【発明の効果】
以上説明したように、本発明によれば、基板周囲の環境を考慮した、より精密な線幅制御及びレジスト膜厚制御を行うことができる。これにより、歩留まりを向上させることができる。
【図面の簡単な説明】
【図１】本発明の一実施形態に係る塗布現像処理装置の平面図である。
【図２】図１に示す塗布現像処理装置の正面図である。
【図３】図１に示す塗布現像処理装置の背面図である。
【図４】一実施形態に係る主ウェハ搬送装置を示す斜視図である。
【図５】図１に示す塗布現像処理装置の清浄空気の流れを説明するための正面図である。
【図６】一実施形態に係るレジスト塗布処理ユニットを示す平面図である。
【図７】図６に示すレジスト塗布処理ユニットを示す断面図である。
【図８】一実施形態に係る現像処理ユニットを示す断面図である。
【図９】一実施形態に係るプリベーキングユニット又はポストエクスポージャーベーキングユニットを示す平面図である。
【図１０】図９に示すユニットの断面図である。
【図１１】本発明に係る塗布現像処理装置を制御する制御系を示す構成図である
【図１２】本発明に係る塗布現像処理装置の一連の処理工程を示すフロー図である。
【図１３】線幅モデル及びその各パラメータを示す図である。
【図１４】現像時間と線幅との相関関係を示す図である。
【図１５】所望の線幅又は膜厚を得るために現像時間又は基板回転数を補正する場合のフロー図である。
【図１６】膜厚モデル及びその各パラメータを示す図である。
【図１７】ウェハの回転数と膜厚との関係を示す図である。
【図１８】ポストエクスポージャーベーキングユニットにおける加熱温度と、線幅との関係を示す図である。
【図１９】プリベーキングユニットにおける加熱温度と、膜厚との関係を示す図である。
【符号の説明】
Ｗ...半導体ウェハ
Ａ１…第１の主ウェハ搬送装置
Ａ２…第２の主ウェハ搬送装置
Ｓａ，Ｓｂ，Ｓｃ，Ｓｄ…温度・気圧センサ
Ｓ１…気圧センサ
Ｓ２…カップ温度センサ
Ｓ３…湿度センサ
ｐ，ｑ，ｒ…膜厚モデルの各パラメータ
ｘ，ｙ，ｚ…線幅モデルの各パラメータ
１…塗布現像処理装置
８…集中制御部
２８…線幅モデル格納部
２９…膜厚モデル格納部
３２…温度コントローラ
３４…回転数コントローラ
３５…制御部
６１…センサ計測データ格納部
６２…ウェハデータ格納部
６３…プロセスレシピデータ格納部
６４…線幅モデル格納部
６５…膜厚モデル格納部
１００...露光装置[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a substrate processing apparatus for forming a desired resist pattern on a semiconductor substrate in manufacturing a semiconductor device, particularly in a photolithography process.
[0002]
[Prior art]
In a photolithography process in the manufacture of a semiconductor device, a resist film is formed on the surface of a semiconductor wafer (hereinafter referred to as “wafer”), then exposed to a predetermined pattern, and further developed to obtain a desired resist. A pattern is formed.
[0003]
Conventionally, such a photolithography process has a coating and developing process including a resist coating processing unit that rotates a wafer and applies a resist solution by centrifugal force, and a development processing unit that supplies a developing solution to the wafer for development processing. This is performed by a processing apparatus and an exposure apparatus provided continuously and integrally with the apparatus. In addition, such a coating and developing treatment apparatus has a heat treatment unit or a cooling treatment unit for performing thermal treatment such as heat treatment or cooling treatment on a wafer after forming a resist film or before and after the development treatment. Furthermore, it has a transfer robot and the like for transferring wafers between these processing units.
[0004]
By the way, in recent years, miniaturization of resist patterns has further progressed. For example, it is required to manage the line width of resist patterns more precisely. Further, since the resist film thickness has a great influence on the shape of the resist pattern, it is required to precisely manage the resist film thickness.
[0005]
[Problems to be solved by the invention]
However, the line width of the resist pattern depends on the environment around the wafer in the coating / development processing apparatus, for example, the transport time until it is loaded into each processing unit, the temperature or humidity in the apparatus, or the flow of airflow in the apparatus. Can also be affected. Similarly, regarding the resist film thickness, the environment around the wafer, such as the transfer time and temperature / humidity outside the resist coating unit, may adversely affect the resist film thickness. In the conventional coating and developing apparatus, since the environment around the wafer has not been taken into consideration, it is difficult to control the line width and the resist film thickness more precisely.
[0006]
In view of the circumstances as described above, an object of the present invention is to provide a substrate processing apparatus capable of performing more precise line width control and resist film thickness control in consideration of the environment around the substrate.
[0007]
[Means for Solving the Problems]
  In order to achieve the above object, a substrate processing apparatus according to the present invention includes a resist film formation processing unit that forms a resist film on a substrate, a development processing unit that develops the substrate on which the resist film is formed, and a thermal treatment applied to the substrate. A heat treatment section for performing processing, a delivery section for delivering the substrate to the exposure apparatus side that performs exposure processing before the development processing, and a substrate between at least the resist film formation processing section, the development processing section, and the heat treatment section. In a substrate processing apparatus for forming a desired resist pattern having a transport mechanism for transporting,The thermal processing section includes a first thermal processing section that performs a first thermal process after the exposure process and before a development process, and a second thermal process that performs a second thermal process after the formation of the resist film and before the exposure process. The substrate processing apparatus includes:A function model storage unit for storing a function model created in advance based on a plurality of parameters involved in forming the resist pattern; and the function modelModel formula for resist pattern line width  Line width model CD [ nm ] = Ax + by + cz + dw + h (a, b, c, d, h are constants, x is the time from the end of the exposure process to the start of the first thermal process. [ s ] , Y is the waiting time of the substrate after the second thermal treatment [ s ] , Z is the temperature in the substrate processing apparatus [ ℃ ] , W is the pressure in the substrate processing apparatus [ hPa ] )Based onPredicting the resulting line width value;Development processing conditionsOf these, development time, developer concentration and developer temperatureAt least one ofFeed forwardControlFeed forward controlMeans.
[0008]
  In the present invention, a plurality of environmental conditions around the substrate in each of the above processes that affect the resist pattern formation are extracted, and a function model using these as parameters is created in advance. As this function model, for example, a model relating to a resist film thickness, a line width of a pattern, and the like is created. Then, at the actual product wafer manufacturing stage, at least one of the resist film formation conditions, the development processing conditions, the heat treatment conditions, and the transport conditions in the transport mechanism is controlled based on this function model. Thereby, feedforward control can be performed by predicting, for example, the line width using the function model. In addition, when the resist solution is applied by rotating the substrate at the time of resist film formation, by predicting the resist film thickness by the above function model, which cannot be precisely controlled only by monitoring the rotation speed of the substrate. Feed forward control is possible. Thus, the line width of the pattern and the resist film thickness can be controlled more precisely in response to the demand for pattern miniaturization. Furthermore, in the present invention, since the heat treatment conditions and the conveyance conditions are also controlled based on the function model, the line width and film thickness can be controlled with higher accuracy.
  Among these parameters, “the time from the end of the exposure process to the start of the first thermal process” and “the waiting time of the substrate after the second thermal process” are “time For example, when there are a plurality of processing units in the substrate processing apparatus and a single wafer processing is performed, the “time” parameter is a parameter that differs for each substrate. The width is preferably controlled for each substrate.
In particular, the line width can be controlled easily and precisely by controlling the development time that is considered to have the greatest influence on the fluctuation of the line width.
[0015]
  In particular, the line width can be controlled easily and precisely by controlling the number of rotations of the substrate that is considered to have the greatest influence on the film thickness variation.
[0016]
According to an aspect of the present invention, the apparatus further includes an inspection device that inspects the line width, the resist film thickness, or the overlay, and the transport mechanism is provided so that a substrate can be delivered to the inspection device. Thereby, each inspection by each inspection apparatus can be performed dynamically and automatically in the manufacturing stage of an actual product wafer. For example, control such as feedforward and feedback can be performed based on each inspection result.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
1 to 3 are views showing the overall configuration of a coating and developing treatment apparatus according to an embodiment of the present invention. FIG. 1 is a plan view, and FIGS. 2 and 3 are a front view and a rear view.
[0019]
In this coating and developing treatment apparatus 1, a plurality of semiconductor wafers W as wafers to be processed are carried in the wafer cassette CR in units of 25, for example, 25, from the outside to the apparatus 1 or unloaded from the apparatus 1, or the wafer W is loaded into the wafer cassette CR. A cassette station 10 as a receiving unit for carrying in and out the wafer, and various single-wafer processing units for performing predetermined processing on the wafer W one by one in the coating and developing process are arranged in multiple stages at predetermined positions. And the interface unit 14 for delivering the wafer W between the processing station 12 and the exposure apparatus 100 provided adjacent to the processing station 12 are integrally connected.
[0020]
In the cassette station 10, as shown in FIG. 1, a plurality of, for example, five wafer cassettes CR are mounted in a row in the X direction at the position of the protrusion 20 a on the cassette mounting table 20 with the respective wafer entrances facing the processing station 12 side. The wafer carrier 22 that is placed and movable in the cassette arrangement direction (X direction) and in the wafer arrangement direction (Z direction) of the wafers stored in the wafer cassette CR selectively accesses each wafer cassette CR. ing. Further, the wafer transfer body 22 is configured to be rotatable in the θ direction so that it can also access a heat treatment system unit belonging to a third processing unit section G3 having a multistage structure, which will be described later, as shown in FIG. It has become.
[0021]
Further, as shown in FIG. 2, a central control unit 8 that comprehensively controls the entire coating and developing treatment apparatus 1 is incorporated in the lower part of the cassette station 10.
[0022]
As shown in FIG. 1, the processing station 12 includes a third processing unit G3, a fourth processing unit G4, and a fifth processing unit G5 from the cassette station 10 side on the rear side of the apparatus (upper side in the drawing). A first main wafer transfer device A1 is provided between each of the third processing unit part G3 and the fourth processing unit part G4. As will be described later, in the first main wafer transfer device A1, the first main wafer transfer body 16 includes a first processing unit unit G1, a third processing unit unit G3, a fourth processing unit unit G4, and the like. It is installed so that it can be selectively accessed. Further, a second main wafer transfer device A2 is provided between the fourth processing unit G4 and the fifth processing unit G5, and the second main wafer transfer device A2 is similar to the first, The second main wafer carrier 17 is installed so as to selectively access the second processing unit part G2, the fourth processing unit part G4, the fifth processing unit part G5, and the like.
[0023]
In addition, a heat treatment unit is installed on the back side of the first main wafer transfer apparatus A1, for example, an adhesion unit (AD) 110 for hydrophobizing the wafer W, a heating unit (for heating the wafer W) ( HP) 113 is stacked in two steps from the bottom as shown in FIG. The adhesion unit (AD) may further include a mechanism for adjusting the temperature of the wafer W. On the back side of the second main wafer transfer device A2, a peripheral exposure device (WEE) 120 that selectively exposes only the edge portion of the wafer W, an overlay inspection device 47 that inspects the overlay of the pattern, and coating on the wafer W A film thickness inspection device 48 for inspecting the resist film thickness and a line width inspection device 49 for inspecting the line width of the resist pattern are provided in multiple stages, and the second main wafer transfer device A2 is included in these inspection devices. On the other hand, the wafer can be delivered. In addition, a heat treatment unit (HP) 113 may be arranged on the back side of the second main wafer transfer device A2 similarly to the back side of the first main wafer transfer device A1.
[0024]
As shown in FIG. 3, in the third processing unit G3, an oven-type processing unit that performs a predetermined process by placing the wafer W on a mounting table, for example, a high-temperature heat processing unit that performs a predetermined heat process on the wafer W (BAKE), a cooling processing unit (CPL) that cools the wafer W with accurate temperature control, a transition unit (TRS) that serves as a transfer unit of the wafer W from the wafer transport body 22 to the main wafer transport body 16, Delivery / delivery / cooling processing units (TCP), which are separately provided in the upper and lower two stages, respectively, are divided into, for example, 10 stages in order from the top. In the third processing unit G3, in the present embodiment, the third stage from the bottom is provided as a spare space.
[0025]
Also in the fourth processing unit G4, for example, a post-baking unit (POST), a transition unit (TRS) serving as a wafer transfer unit, and a pre-baking unit that heat-treats the wafer W after forming a resist film as a second thermal processing. (PAB), similarly, cooling processing units (CPL) as the second thermal processing are stacked in, for example, 10 stages in order from the top. Further, in the fifth processing unit G5, for example, a post-exposure baking unit (PEB) for performing heat treatment on the exposed wafer W as a first heat treatment unit, and a cooling processing unit (also a first heat treatment unit ( CPL) and transition units (TRS) serving as a transfer part of the wafer W are stacked in, for example, 10 stages in order from the top.
[0026]
In FIG. 1, a first processing unit part G1 and a second processing unit part G2 are provided side by side in the Y direction on the apparatus front side of the processing station 12 (downward in the drawing). Between the first processing unit part G1 and the cassette station 10 and between the second processing unit part G2 and the interface part 14, it is used for temperature control of the processing liquid supplied by the processing unit parts G1 and G2. Liquid temperature control pumps 24 and 25 are provided, respectively, and clean air from an air conditioner (not shown) provided outside the coating and developing treatment apparatus 1 is supplied into the processing units G1 to G5. Ducts 31 and 32 are provided.
[0027]
As shown in FIG. 2, in the first processing unit G1, five spinner type processing units that perform predetermined processing by placing the wafer W on a spin chuck in a cup CP, for example, resist as a resist film forming unit. The coating processing unit (COT) has three stages, and a bottom coating unit (BARC) for forming an antireflection film for preventing reflection of light during exposure is superposed in two stages and five stages in order from the bottom. Similarly, in the second processing unit G2, five spinner type processing units, for example, development processing units (DEV) as development processing units are stacked in five stages. In the resist coating processing unit (COT), the drainage of the resist solution is troublesome both in terms of mechanism and maintenance, and thus is preferably arranged in the lower stage. However, it can be arranged in the upper stage as required.
[0028]
In addition, chemical chambers (CHM) 26 and 27 for supplying the above-described predetermined processing liquid to the respective processing unit units G1 and G2 are provided at the lowermost stages of the first and second processing unit units G1 and G2, respectively. Yes.
[0029]
Further, the processing station 12 is provided with, for example, four temperature / atmospheric pressure sensors Sa, Sb, Sc, and Sd that measure the temperature and pressure in the processing station 12. For example, by taking, for example, an average value of the measurement results obtained by the four temperature / atmospheric pressure sensors Sa, Sb, Sc, and Sd, the temperature and the atmospheric pressure can be managed with higher accuracy.
[0030]
A portable pickup cassette CR and a stationary buffer cassette BR are arranged in two stages on the front surface of the interface section 14, and a wafer carrier 27 is provided in the center. The wafer carrier 27 moves in the X and Z directions to access both cassettes CR and BR. Further, the wafer carrier 27 is configured to be rotatable in the θ direction, and can also access the fifth processing unit G5. Further, as shown in FIG. 3, a plurality of high-precision cooling processing units (CPL) are provided on the back surface of the interface unit 14, for example, in two upper and lower stages. The wafer carrier 27 can also access this cooling processing unit (CPL).
[0031]
FIG. 4 is a perspective view showing a first main wafer transfer device A1 according to an embodiment of the present invention. Since the second main wafer transfer device A2 is the same as the first main wafer transfer device A1, its description is omitted.
[0032]
As shown in FIG. 1, the main wafer transfer device A1 is surrounded by a casing 41 to prevent particles from entering. In FIG. 4, the casing 41 is not shown for easy understanding.
[0033]
As shown in FIG. 4, poles 33 are suspended from both ends of the main wafer transfer device A1, and the main wafer transfer body 16 (17) can move in the vertical direction (Z direction) along the pole 33. Is arranged. The transfer base 55 in the main wafer transfer body 16 is provided with three tweezers 7 a to 7 c for holding the wafer W, and these tweezers 7 a to 7 c are horizontally mounted by a drive mechanism (not shown) built in the transfer base 55. It is configured to be movable in the direction. A support portion 45 that supports the transport base 55 is connected to a lower portion of the transport base 55 via a rotating member 46 that can rotate in the θ direction. Thereby, the wafer carrier 16 can be rotated in the θ direction. A flange portion 45 a is formed in the support portion 45, the flange portion 45 a is slidably engaged with a groove 33 a provided in the pole 33, and can be slid by a belt driving mechanism built in the pole 33. Is provided. Thereby, the main wafer transfer body 16 can move in the vertical direction along the pole 33.
[0034]
For example, four fans 36 for controlling the pressure and temperature / humidity inside the transfer device A1 are provided at the bottom of the main wafer transfer device A1.
[0035]
FIG. 5 shows the flow of clean air in the coating and developing treatment apparatus 1. In FIG. 5, air supply chambers 10a, 12a, 14a are provided above the cassette station 10, the processing station 12, and the interface unit 14, and a filter with a dustproof function, for example, ULPA is provided on the lower surface of the air supply chambers 10a, 12a, 14a. Filters 101, 102, and 103 are attached. Air that is cleaner than the ULPA filters 101, 102, and 103 in each air supply chamber is supplied to each of the units 10, 12, and 14 by downflow, and supplied from the air supply chamber to the processing unit by downflow. This downflow air is supplied in the arrow direction (upward) from the ducts 31 and 32 described above.
[0036]
Further, in each of the units of the liquid supply system units (G1, G2), a fan / filter unit F is attached above them, and an atmospheric pressure sensor S1 for measuring the atmospheric pressure is provided. The fan / filter unit F has, for example, a ULPA filter and a small fan (not shown). On the other hand, although not shown, each sensor in the third to fifth processing unit sections G3 to G5 and the first and second main wafer transfer apparatuses A1 and A2 are provided with similar sensors.
[0037]
6 and 7 are a plan view and a cross-sectional view showing a resist coating unit (COT) according to an embodiment of the present invention.
[0038]
In this unit, as described above, the fan / filter unit F is attached above the casing 41 ′, and below the annular cup near the center of the unit bottom plate 151 smaller than the width in the Y direction of the casing 41 ′. A CP is disposed, and a spin chuck 142 is disposed inside thereof. The spin chuck 142 is configured to rotate by the rotational driving force of the drive motor 143 while the wafer W is fixedly held by vacuum suction. The rotation speed of the drive motor 143 is controlled by the rotation speed controller 34.
[0039]
In the cup CP, pins 148 for transferring the wafer W are provided so as to be moved up and down by the driving device 147. Accordingly, the wafer can be transferred to and from the tweezers 7a through the opening 41′a while the shutter 43 provided to be openable and closable is open. Also, a drain port 145 for waste liquid is provided at the bottom of the cup CP. A waste liquid pipe 141 is connected to the drain port 145, and the waste liquid pipe 141 communicates with a waste liquid port (not shown) below using a space N between the unit bottom plate 151 and the casing 41 '.
[0040]
As shown in FIG. 6, a nozzle 135 for supplying a resist to the surface of the wafer W is connected to a liquid supply mechanism (not shown) in a chemical chamber (CHM) 26 (FIG. 2) via a supply pipe 134. Has been. The nozzle 135 is detachably attached to the tip of the nozzle scan arm 136 by a nozzle standby unit 146 disposed outside the cup CP, and is transferred to a predetermined resist discharge position set above the spin chuck 142. It is like that. The nozzle scan arm 136 is attached to the upper end of a vertical support member 149 that can move horizontally on a guide rail 144 laid in one direction (Y direction) on the unit bottom plate 151, and is not shown in the figure. Accordingly, the vertical support member 149 and the vertical support member 149 move together in the Y direction.
[0041]
The nozzle scan arm 136 is also movable in the X direction perpendicular to the Y direction in order to selectively attach the nozzle 135 according to the type of resist by the nozzle standby unit 146, and is moved in the X direction by an X direction drive mechanism (not shown). Also comes to move. Here, the types of resist differ depending on differences in resist concentration, viscosity, and the like.
[0042]
Further, a drain cup 138 is provided between the cup CP and the nozzle standby unit 146, and the nozzle 135 is cleaned at this position prior to the supply of the resist to the wafer W.
[0043]
On the guide rail 144, not only the vertical support member 149 that supports the nozzle scan arm 136 described above, but also a vertical support member that supports the rinse nozzle scan arm 139 and is movable in the Y direction. A rinse nozzle 140 for side rinse is attached to the tip of the rinse nozzle scan arm 139. The rinse nozzle scan arm 139 and the rinse nozzle 140 are moved by a Y-direction drive mechanism (not shown) so that the nozzle standby position set on the side of the cup CP and the peripheral edge portion of the wafer W placed on the spin chuck 142 are It moves between the rinse liquid discharge positions set above.
[0044]
In the resist coating unit (COT), the atmospheric pressure sensor S1 for measuring the atmospheric pressure p [hPa] is provided as described above, and the cup temperature sensor S2 for measuring the cup temperature q [° C.] and A humidity sensor S3 for measuring the humidity r [%] in the unit is provided (see FIG. 16).
[0045]
FIG. 8 is a cross-sectional view showing a development processing unit (DEV) according to an embodiment of the present invention. Since this development processing unit (DEV) has a configuration similar to that of the resist coating processing unit (COT), the same components as those in the resist coating processing unit (COT) in FIG. Reference numerals will be attached and description thereof will be omitted.
[0046]
The nozzle 153 for supplying the developer to the surface of the wafer W has substantially the same length as the diameter of the wafer W, and a plurality of holes for discharging the developer are formed, although not shown. Alternatively, a nozzle having a slit-like discharge port may be used. A rinse nozzle (not shown) is also provided on the wafer W so as to be movable.
[0047]
9 and 10 are a plan view and a cross-sectional view of a pre-baking unit (PAB) and a post-exposure baking unit (PEB) for performing thermal processing on the wafer W according to an embodiment of the present invention. These baking units are different only in processes such as processing temperature.
[0048]
These units are surrounded by a casing 75, and a heating plate for placing the wafer W on the back side in the processing chamber 30 under the control of the temperature controller 32 and performing a heat treatment, for example, at about 100 ° C. 86 is provided, and on the front side, a temperature control plate 71 for controlling the temperature by placing the wafer W is provided. The heating plate 86 is supported by a support 88, and lift pins 85 for supporting the wafer W from below the support 88 are provided by a lift cylinder 82 so as to be lifted and lowered. A cover member (not shown) that covers the heating plate 86 during the heat treatment is disposed on the upper portion of the heating plate 86.
[0049]
As a temperature adjustment mechanism of the temperature control plate 71, for example, the temperature control is performed by adjusting the temperature of the wafer W to a predetermined temperature, for example, around 40 ° C. by using cooling water, a Peltier element or the like. As shown in FIG. 9, the temperature control plate 71 is formed with a notch 71 a, and an elevating pin 84 buried under the temperature control plate 71 can appear and disappear from the surface of the temperature control plate by the elevating cylinder 81. It has become. The temperature control plate 71 can be moved along the rail 77 by a motor 79a, for example, so that the wafer is delivered to the heating plate 86 while the temperature of the wafer is controlled. It has become.
[0050]
The pre-baking unit (PAB) and the post-exposure baking unit (PEB) have an air flow path 75c for controlling the atmospheric pressure, and the air from the flow path 75c is processed through the fan 87a. It flows into the chamber 30. The air in the processing chamber 30 is exhausted from the exhaust port 75d by the fans 87b provided on both wall surfaces.
[0051]
Further, on one side surface portion of the casing 75 on the temperature control plate 71 side, for example, with respect to the fourth processing unit G4, the wafer W is transferred to and from the first main wafer transfer device A1. , An opening 75a is provided, and an opening 75b is provided on the other side surface so as to face the opening on the second main wafer transfer apparatus A2 side. The openings 75a and 75b are respectively provided with shutters 76a and 76b that can be opened and closed by a driving unit (not shown).
[0052]
Although not shown, the cooling processing unit (CPL) includes a cooling plate on which, for example, the wafer W is placed and the wafer subjected to each heat treatment is subjected to a cooling treatment at around 23 ° C. A Peltier element or the like is used as the cooling mechanism.
[0053]
FIG. 11 is a configuration diagram showing a control system of the coating and developing treatment apparatus 1. The coating and developing apparatus 1 includes a transfer system such as the above-described resist coating unit (COT), development unit (DEV), pre-baking unit (PAB), post-exposure baking unit (PEB), and main wafer transfer unit A1. These devices and sensors Sa to Sd are connected to the bus 5. Although not shown, all other units such as a post baking unit (POST) and a cooling processing unit (CPL) are connected to the bus 5 in the same manner.
[0054]
The central control unit 8 is connected to the bus 5, and the central control unit 8 includes, for example, each sensor measurement data storage unit 61, wafer data storage unit 62, process recipe data storage unit 63, and line width model storage unit 64. The film thickness model storage unit 65, the development time / line width model storage unit 56, the heating temperature / line width model storage unit 57, and the rotation speed / film thickness model storage unit 58 are connected to each other.
[0055]
Each sensor measurement data storage unit 61 stores the measurement results of the sensors S1 to S3 and the sensors Sa to Sd in the resist coating unit (COT). The wafer data storage unit 62 stores, for example, an identifier assigned to each wafer, and in which unit in the coating and developing treatment apparatus 1 these wafers are present, and what processing is performed in what time. It is memorized for every wafer whether it was done. For example, the identifiers can be given in the order of wafers stored in multiple stages in the wafer cassette CR, for example, from the top in the cassette CR. The process recipe data storage unit 63 stores the processing process requested by the host. The line width model storage unit 64 stores a plurality of data collected to obtain a line width of a desired resist pattern as mathematical expressions. Similarly, the film thickness model storage unit 65 stores a plurality of data collected to obtain a desired resist film thickness as mathematical expressions.
[0056]
The development time-line width model storage unit 56 stores the correlation between the development time and the line width of the pattern, for example, as an equation. Similarly, the heating temperature-line width model storage unit 57 stores the correlation between the heating temperature and the line width by the post-exposure baking unit (PEB) as mathematical expressions. Similarly, the rotational speed-film thickness model storage unit 59 stores the correlation between the rotational speed of the wafer and the resist film thickness at the time of forming the resist film as, for example, an equation.
[0057]
Next, a series of processing steps of the coating and developing treatment apparatus 1 described above will be described with reference to the flow shown in FIG.
[0058]
First, in the cassette station 10, the wafer carrier 22 accesses the cassette CR containing the unprocessed wafer W on the cassette mounting table 20, and takes out one wafer W from the cassette CR. Then, the wafer W is transferred to the first main transfer apparatus A1 via the transfer / cooling processing unit (TCP) and transferred to the bottom coating unit (BARC). Here, an antireflection film is formed in order to prevent reflection of exposure light from the wafer during exposure (step 12-1). Next, the wafer W is transferred to a baking processing unit in the third processing unit section G3, where a predetermined heat treatment is performed at 120 ° C., for example (step 12-2), and a predetermined cooling is performed in the cooling processing unit (CPL). After the processing is performed (step 12-3), a desired resist film is formed on the wafer W in the resist coating processing unit (COT) (step 12-4).
[0059]
In this resist coating unit (COT), when the wafer W is transferred to a position directly above the cup CP, first, the pins 148 are raised and lowered after receiving the wafer W, and the wafer W is moved onto the spin chuck 142. It is mounted on and vacuum-adsorbed. Then, the nozzle 135 waiting in the nozzle standby portion moves to above the center position of the wafer W. Then, after a predetermined resist solution is discharged at the center of the wafer W, the resist film is applied to the entire surface of the wafer W by rotating the drive motor 143 at, for example, 100 rpm to 5000 rpm, and diffusing the resist solution over the entire surface of the wafer W. Complete.
[0060]
There is a correlation between the number of rotations of the wafer W and the thickness of the resist film when the resist film is formed. For example, as shown in FIG. 17, the film thickness decreases as the number of rotations increases.
[0061]
When the resist film is formed, the wafer W is transferred to the pre-baking unit (PAB) by the first main transfer device A1. Here, first, the wafer W is placed on the temperature control plate 71 shown in FIG. 9, and the wafer W is moved to the heating plate 86 side while being temperature controlled. Then, the wafer W is placed on the heating plate 86, and a predetermined heat treatment is performed at about 100 ° C., for example. When this heat treatment is completed, the temperature control plate 71 again accesses the heating plate 86 side, and the wafer W is transferred to the temperature control plate 71. The temperature control plate 71 moves to the original position as shown in FIG. The wafer W waits until it is taken out by the first main transfer device A1 (step 12-5). The waiting time y [second] in the pre-baking unit (PAB) is defined as the time from the end of the heat treatment by the heating plate 86 to the removal by the first main transport device A1. Since this waiting time y has a different value for each wafer W under the single wafer processing of the coating and developing treatment apparatus 1 according to this embodiment, the wafer data storage unit 62 is provided for each wafer to which an identifier is attached. Are sequentially stored.
[0062]
Next, the wafer W is cooled at a predetermined temperature by a cooling processing unit (CPL) (step 12-6). Thereafter, the wafer W is taken out by the second main transfer device A2 and transferred to the film thickness inspection device 119, where a predetermined resist film thickness may be measured. Then, the wafer W is transferred to the exposure apparatus 100 via the transition unit (TRS) and the interface unit 14 in the fifth processing unit unit G5 and subjected to exposure processing (step 12-7).
[0063]
Next, the wafer W is transferred to the second main transfer device A2 via the interface unit 14 and the transition unit (TRS) in the fifth processing unit G5, and then transferred to the post-exposure baking unit (PEB). The After the exposure process, the wafer W may be temporarily stored in the buffer cassette BR in the interface unit 14.
[0064]
In the post-exposure baking unit (PEB), predetermined heat treatment and temperature adjustment processing are performed by the same operation as that in the pre-baking unit (PAB) (step 12-8). Here, the time from the completion of the exposure process until the heating process is started after being carried into the post-exposure baking unit (PEB) is defined as x [seconds]. Since this time x has a different value for each wafer W under the single wafer processing of the coating and developing treatment apparatus 1 according to this embodiment, the time x is stored in the wafer data storage unit 62 for each wafer with an identifier. Stored sequentially.
[0065]
Next, the wafer W is transferred to a development processing unit (DEV) and subjected to development processing (step 12-9). In this development processing unit (DEV), when the wafer W is transferred to a position immediately above the cup CP, first, the pins 148 are raised and lowered after receiving the wafer W, and the wafer W is placed on the spin chuck 142. It is placed and vacuum-sucked. Then, the nozzle 135 waiting in the nozzle standby portion moves to above the peripheral position of the wafer W. Subsequently, the wafer W is rotated by, for example, 10 rpm to 100 rpm by the drive motor 143, and the nozzle 135 is applied in the Y direction from the periphery of the wafer W, and a predetermined developer is applied by a centrifugal force of rotation. The development process proceeds by leaving it to stand. There is a correlation between the development time t and the line width in this development processing. For example, as shown in FIG. 14, the longer the development time, the smaller the line width. Thereafter, a rinse solution is supplied onto the wafer, the developer is washed away, and the wafer is rotated to perform a shake-off drying process.
[0066]
Thereafter, a predetermined cooling process is performed by the cooling process unit (CPL) (step 12-10).
[0067]
Next, the wafer W is taken out by the second main transfer device A2, and the transition unit (TRS) in the fourth processing unit unit G4, the first main transfer device A1, and the transition unit (TRS in the third processing unit unit). ) And the wafer cassette CR in the cassette station 10 via the wafer carrier 22.
[0068]
Note that after the development process, a predetermined heat treatment may be performed by a post-baking unit (POST). Further, after the development processing, the line width inspection device 49 or the overlay inspection device 47 may perform a line width inspection or an overlay inspection, respectively.
[0069]
FIG. 13 shows data stored in the line width model storage unit 64 shown in FIG. FIG. 14 is a model formula for correcting the development time to obtain the target line width. Further, FIG. 15 is a flowchart showing a correction process performed to obtain a development time target line width. The line width model shown in FIG. 13 includes the times x and y, the temperature z [° C.] in the coating and developing apparatus, and the atmospheric pressure w [hPa] in the coating and developing apparatus (the temperature z and the atmospheric pressure w are as described above. And obtained by each of the sensors Sa to Sd shown in FIG.
Line width model CD [nm] = ax + by + cz + dw + h (a, b, c, d, h are constants)
For example,
Line width model CD [nm] = 0.02x + 0.03y + 0, 54z + 0.65w
-466.608
It can be expressed by the model formula This model formula was created by experiment.
[0070]
Then, referring to FIG. 15, first, one or a plurality of inspection wafers are processed by, for example, the flow shown in FIG. 12, and the actual development processing is performed. Sensor data, time data, etc. regarding the processed wafers are obtained. Collect for each wafer (step 15-1). Next, these data are analyzed (step 15-2), and the line width that will actually be formed by the above-described line width model formula is obtained before development processing. That is, by creating this model formula in advance, the line width after the development processing can be predicted before the development processing.
[0071]
When the line width is predicted, it is determined whether or not the line width value is within a predetermined range (for example, within a range of ± 5 nm) (step 15-3). If the line width value is within a predetermined range, the process is continued with the actual product wafer as it is (step 15-4), and the development process is performed. Thereby, a resist pattern having a desired line width is actually obtained.
[0072]
On the other hand, if it is not within the predetermined range, the development time is corrected as follows (step 15-5). The relationship between the development time t and the line width is obtained in advance by experiments, and is represented by the relationship as shown in FIG. 14, for example, so that such a correlation is used.
[0073]
When the development time is actually corrected, for example, a target line width (desired line width) is input, and the expression shown in FIG.

The corrected development time is determined by substituting the CD value obtained by the above calculation into. A resist pattern having a desired line width can be developed by performing the development processing as described above for the development time thus obtained.
[0074]
As described above, the “time x from the end of the exposure process to the start of the heat treatment in the post-exposure baking unit (PEB)”, which affects the formation of the resist pattern, and “in the pre-baking unit (PAB)” A line width model having parameters of “waiting time y”, “temperature z in the coating and developing treatment apparatus”, and “atmospheric pressure w in the coating and developing treatment apparatus” is created in advance, and based on this line width model. The line width can be predicted by controlling the development time t, which is one of the development processing conditions. In addition, once the line width model is created, if analysis is performed based on the model, feedforward control can be dynamically performed even when an actual product wafer is manufactured. Thus, precise line width control can be performed, and the yield can be improved.
[0075]
Further, the line width can be easily controlled by controlling the development time that is most easily controlled among a plurality of development processing conditions such as the development time, the concentration of the developer, or the temperature of the developer.
[0076]
In addition, since x and y are parameters related to time among these parameters, such a line width control is performed for each wafer. For the single wafer processing apparatus according to the present embodiment, the time is determined for each wafer. It is effective considering different things.
[0077]
In the present embodiment, since the overlay inspection apparatus 47, the film thickness inspection apparatus 48, and the line width inspection apparatus 49 are in-line and the substrate can be transferred by the main wafer transfer apparatus A2, these inspections are performed on the actual product wafer. It can be performed dynamically and automatically at the manufacturing stage. Thereby, for example, control such as feedforward and feedback can be performed based on each inspection result.
[0078]
Furthermore, by creating the line width model according to the type of resist or the target film thickness, for example, a line width model can be created according to differences in resist concentration, viscosity, etc. Development processing conditions can be controlled according to the type or target film thickness. The same applies to the film thickness control described below.
[0079]
FIG. 16 shows data stored in the film thickness model storage unit 65 shown in FIG. This film thickness model uses the atmospheric pressure p, the cup temperature q, and the humidity r, similarly to the line width model,
Film thickness model T = ep + fq + gr + i (e, f, g, i are constants)
It can be expressed as. The film thickness that will actually be formed can be obtained and predicted by such a model formula. The relationship between the number of rotations of the wafer and the film thickness during the formation of the resist film has been obtained in advance by experiments, and is represented by the relationship shown in FIG. 17, for example. Thereby, the desired number of rotations of the wafer can be obtained. As an example, when T = 4050 mm (405 nm) and the target film thickness is 4000 mm (400 nm), the target film thickness of 4000 mm (400 nm) can be achieved by setting the rotation speed of the wafer, which was 3500 rpm, to 3700 rpm. .
[0080]
In this way, a film thickness model having parameters of “pressure p”, “temperature CP of cup CP”, and “humidity r in unit” that affect the formation of the resist film is prepared in advance. In addition, based on this film thickness model, feedforward control can be performed by controlling the number of rotations of the wafer, which is one of the resist film formation conditions. That is, conventionally, data such as atmospheric pressure, cup CP temperature, and humidity have not been used for film thickness control, but in this embodiment, by predicting the film thickness using these parameters, accurate data can be obtained. The film thickness can be controlled. This also contributes to improved yield.
[0081]
In addition, the film thickness can be easily controlled by controlling the number of resist film formation conditions, for example, wafer rotation speed, resist solution temperature, resist solution supply amount, resist discharge speed, etc. Can be controlled.
[0082]
Further, since these parameters p, q, and r do not relate to time, it is not necessary to manage the film thickness for each wafer. For example, a so-called lot advance process in which a dummy wafer is first processed in units of lots may be used.
[0083]
FIG. 18 shows the relationship between the heating temperature in the post-exposure baking unit (PEB) and the line width of the resist pattern. Thereby, it turns out that there exists a tendency for line | wire width to become thin, so that heating temperature is high. Thus, as in the case shown in FIG. 14, instead of controlling the development processing conditions, the line width can be fed forward by controlling the heating temperature in the post-exposure baking unit (PEB) using the line width model. It can be controlled precisely. Further, by performing both the control of the heating temperature and the control of the development time, the line width can be controlled with higher accuracy.
[0084]
Similarly, FIG. 19 shows the relationship between the heating temperature in the pre-baking unit (PAB) and the resist film thickness. Thereby, it turns out that there exists a tendency for a film thickness to become small, so that heating temperature is high. Thus, as in the case shown in FIG. 17, instead of controlling the number of rotations of the wafer, the film thickness can be controlled in a feed-forward manner by controlling the heating temperature in the pre-baking unit (PAB) using the film thickness model. Can be controlled. Further, by performing both the control of the heating temperature and the control of the number of rotations of the wafer, the line width can be controlled with higher accuracy.
[0085]
Further, in the present embodiment, the relationship between the line width and the film thickness has not been described, but if this relationship is known, the line width and the film thickness can be controlled more precisely based on this relationship. it can.
[0086]
The present invention is not limited to the embodiments described above, and various modifications are possible.
[0087]
For example, in the above embodiment, at least one of the development time and the heating temperature is controlled in the line width control, and at least one of the wafer rotation speed and the heating temperature is controlled in the film thickness control. Not only, but also higher accuracy by controlling the heat treatment temperature in the baking unit (BAKE), the heating unit (HP) 113, etc., or the cooling temperature in the cooling processing unit (CPL), the delivery / cooling processing unit (TCP), etc. Line width control can be performed.
[0088]
In addition, when controlling the line width, not only the development time is controlled as a development processing condition, but also the concentration and temperature of the developer may be controlled. Alternatively, when controlling the film thickness, not only the rotation speed of the wafer is controlled as a resist film formation condition, but also the resist temperature, the resist discharge speed from the nozzle, and the like may be controlled.
[0089]
Furthermore, instead of correcting the development time, the wafer rotation speed, and the heat treatment temperature, with respect to the line width, the desired line is corrected by correcting the time x, y in FIG. A width may be obtained, and with respect to the film thickness, a resist film having a desired film thickness may be formed by correcting the pressure p, the cup temperature q, the humidity r, etc. shown in FIG. .
[0090]
Moreover, it is possible to control not only the heating temperature in the post-exposure baking unit (PEB) and the pre-baking unit (PAB) shown in FIGS. 18 and 19, but also the heating time, the heating rate, and the like. It is also possible to control the cooling temperature, cooling time, cooling rate, etc. in the cooling processing unit (CPL).
[0091]
Further, the exposure processing conditions in the exposure apparatus 100 (see FIG. 1) may also be controlled by the central control unit 8 on the coating and developing processing apparatus 1 side. In this case, for example, since it is known that there is an inversely proportional relationship between the exposure amount and the line width, a resist pattern having a desired line width can be obtained by controlling the exposure amount by feedforward. Can be obtained. Further, not only the exposure amount but also the exposure focus value may be controlled.
[0092]
Further, for example, the etching apparatus may be in-line with respect to the coating and developing treatment apparatus 1, and the etching process conditions may be controlled by the central control unit 8. In this case, for example, it is known that there is an inversely proportional correlation between the etching time and the line width. Therefore, by controlling the etching time by feedforward, a pattern having a desired line width can be obtained. Obtainable.
[0093]
Furthermore, although the case where the semiconductor wafer was used was demonstrated in the said embodiment, this invention is applicable not only to this but the glass substrate used for a liquid crystal display etc.
[0094]
【The invention's effect】
As described above, according to the present invention, more precise line width control and resist film thickness control can be performed in consideration of the environment around the substrate. Thereby, a yield can be improved.
[Brief description of the drawings]
FIG. 1 is a plan view of a coating and developing treatment apparatus according to an embodiment of the present invention.
FIG. 2 is a front view of the coating and developing treatment apparatus shown in FIG.
FIG. 3 is a rear view of the coating and developing treatment apparatus shown in FIG.
FIG. 4 is a perspective view showing a main wafer transfer device according to an embodiment.
FIG. 5 is a front view for explaining the flow of clean air in the coating and developing treatment apparatus shown in FIG. 1;
FIG. 6 is a plan view showing a resist coating unit according to one embodiment.
7 is a cross-sectional view showing the resist coating unit shown in FIG. 6;
FIG. 8 is a cross-sectional view showing a development processing unit according to an embodiment.
FIG. 9 is a plan view showing a pre-baking unit or a post-exposure baking unit according to one embodiment.
10 is a cross-sectional view of the unit shown in FIG.
FIG. 11 is a block diagram showing a control system for controlling the coating and developing treatment apparatus according to the present invention.
FIG. 12 is a flowchart showing a series of processing steps of the coating and developing treatment apparatus according to the present invention.
FIG. 13 is a diagram showing a line width model and its parameters.
FIG. 14 is a diagram illustrating a correlation between development time and line width.
FIG. 15 is a flowchart for correcting the development time or the number of substrate rotations in order to obtain a desired line width or film thickness.
FIG. 16 is a diagram showing a film thickness model and its parameters.
FIG. 17 is a diagram showing the relationship between the number of rotations of a wafer and the film thickness.
FIG. 18 is a diagram showing the relationship between the heating temperature and the line width in the post-exposure baking unit.
FIG. 19 is a diagram showing a relationship between a heating temperature and a film thickness in a pre-baking unit.
[Explanation of symbols]
W ... Semiconductor wafer
A1: First main wafer transfer device
A2 ... Second main wafer transfer device
Sa, Sb, Sc, Sd ... temperature / barometric pressure sensor
S1 ... Barometric pressure sensor
S2 ... Cup temperature sensor
S3 ... Humidity sensor
p, q, r ... Parameters of the film thickness model
x, y, z ... parameters of the line width model
1 ... coating and developing treatment apparatus
8 ... Central control unit
28: Line width model storage unit
29 ... Film thickness model storage
32 ... Temperature controller
34 ... Rotation speed controller
35. Control unit
61 ... Sensor measurement data storage
62: Wafer data storage unit
63 ... Process recipe data storage section
64: Line width model storage unit
65 ... Film thickness model storage
100 ... Exposure equipment

Claims (3)

A resist film formation processing unit that forms a resist film on the substrate, a development processing unit that develops the substrate on which the resist film is formed, a heat treatment unit that performs thermal processing on the substrate, and an exposure process before the development processing Forming a desired resist pattern having a transfer portion for transferring the substrate to the exposure apparatus side and a transfer mechanism for transferring the substrate between at least the resist film formation processing portion, the development processing portion, and the heat treatment portion. In a substrate processing apparatus for
The thermal processing section includes a first thermal processing section that performs a first thermal process after the exposure process and before a development process, and a second thermal process that performs a second thermal process after the formation of the resist film and before the exposure process. Including
The substrate processing apparatus
A function model storage unit for storing a function model created in advance based on a plurality of parameters involved in forming the resist pattern;
Among the function models, a model formula relating to the line width of the resist pattern Line width model CD [nm] = ax + by + cz + dw + h
(A, b, c, d, h are constants, x is the time [s] from the end of the exposure process until the first thermal process is started, and y is the time after the second thermal process. The substrate standby time [s], z is the temperature [° C.] in the substrate processing apparatus, and w is the atmospheric pressure [hPa] in the substrate processing apparatus)
Feedforward control means for predicting the value of the line width obtained based on the above, and feedforward controlling at least one of the development time, the concentration of the developer, and the temperature of the developer among the development processing conditions; A substrate processing apparatus. The substrate processing apparatus according to claim 1,
The function model is created for each type of resist or target film thickness. The substrate processing apparatus according to claim 1,
Further comprising an inspection device for inspecting the line width, resist film thickness, or overlay;
The substrate processing apparatus, wherein the transport mechanism is provided so that a substrate can be delivered to the inspection apparatus.

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