JP4258458B2 - Load drive circuit - Google Patents

Description

  The present invention relates to a load driving circuit that controls a plurality of transistors to drive a load.

  Conventionally, there is a load driving circuit as a circuit for driving a load such as a relay or a motor. The overall configuration of a conventional load driving circuit is shown in FIG. The load drive circuit is configured by a CPU 30 and a diode built-in transistor 10 having an NPN transistor 11, a Zener diode 12 and a resistor 13, and drives a relay 40 as a load connected via an output terminal a.

  When a high level control signal is output from the CPU 30, the NPN transistor 11 is turned on, and a current flows from the power supply terminal VCC to the NPN transistor 11 via the relay 40. Further, when a low-level control signal is output from the CPU 30, the NPN transistor 11 is turned off and no current flows through the relay 40.

  As described above, the NPN transistor 11 drives the relay 40 as a load in accordance with the control signal input from the CPU 30 via the resistor 31.

  When the load drive circuit stops driving an inductive load such as a relay, a surge is input from the load to the collector of the NPN transistor 11.

  FIG. 3 shows waveforms of the control signal and surge voltage. As shown in the figure, when the control signal changes from the high level to the low level, the surge voltage having the waveform shown in the figure is applied from the load to the collector of the NPN transistor 11 for a predetermined period (for example, several tens of milliseconds).

  In order to protect the NPN transistor 11 from such a surge, a Zener diode 12 is provided. That is, when a surge is input to the collector of the NPN transistor 11 and the voltage between the collector and the base of the NPN transistor 11 becomes larger than the Zener voltage of the Zener diode 12, a current flows through the Zener diode 12. Then, a current flows from the Zener diode 12 to the base of the NPN transistor 11, the NPN transistor 11 is turned on, and a surge current flows as a collector current of the NPN transistor 11. In this way, surge energy is absorbed and the NPN transistor 11 is protected.

  However, in the above-described circuit configuration, for example, when the NPN transistor 11 fails in the short mode, a current flows into the NPN transistor 11 from the power supply terminal VCC via the relay 40.

  FIG. 4 shows a circuit configuration studied by the inventors in order to avoid such a state. As shown in the figure, a diode built-in transistor 20 is connected in series with the diode built-in transistor 10.

  The load drive circuit is configured by the diode built-in transistor 10, the diode built-in transistor 20, and the CPU 30, and drives the relay 40 as a load connected via the output terminal a.

  The diode built-in transistor 20 includes an NPN transistor 21, a surge protection Zener diode 22 and a resistor 23, and has the same configuration as the diode built-in transistor 10.

  A control signal from the CPU 30 is input to the base of the NPN transistor 11 of the diode built-in transistor 10 via the resistor 31, and the base of the NPN transistor 21 of the diode built-in transistor 20 is input from the CPU 30 via the resistor 32. A control signal is input.

  In such a configuration, when driving the relay 40 is started, a high level control signal is simultaneously output from the CPU 30 to each base of the NPN transistors 11 and 21. As a result, the NPN transistors 11 and 12 are turned on, and a current flows from the power supply terminal VCC to the NPN transistor 11 via the relay 40.

  When the driving of the relay 40 is stopped, a low level control signal is simultaneously output from the CPU 30 to each base of the NPN transistors 11 and 21. As a result, the NPN transistors 11 and 12 are turned off and no current flows through the relay 40.

  In this case, since the NPN transistors 11 and 21 are connected in series, even if one of the NPN transistors 11 and 21 fails in the short mode, the other transistor is turned off and the current flowing through the relay 40 is Blocked.

  Even in such a configuration, when the drive of the relay 40 is stopped, a surge is input from the relay 40 to the collector of the NPN transistor 11. At this time, the NPN transistor 11 is turned on by the Zener diode 12, but since the NPN transistor 21 is turned off, the emitter of the NPN transistor 11 is in an open state, and a surge current flows from the NPN transistor 11 to the NPN transistor 21. Not flowing. For this reason, there arises a problem that the protection function of the NPN transistor 11 by the Zener diode 12 does not function normally.

  The present invention has been made in view of the above problems, and it is an object of the present invention to avoid a state in which a load current remains flowing and to cause a transistor protection function by a Zener diode to function normally.

  In order to achieve the above object, according to the first and second aspects of the present invention, a first transistor connected to a load and driving the load, and a first transistor connected in series with the first transistor and driving the load together with the first transistor. And a control circuit for controlling on / off of the first transistor and the second transistor, wherein the first transistor has a Zener diode, and the Zener diode When a surge is input from the load to the first transistor, the first transistor is turned on and a surge current flows from the first transistor to the second transistor. The control circuit drives the load. Is stopped, the first transistor is turned off while the second transistor is turned on, and a predetermined period or more has elapsed. After, it is characterized in that for turning off the second transistor.

  Thus, when stopping the drive of the load, the control circuit turns off the first transistor while turning on the second transistor, and turns off the second transistor after a predetermined period or more has elapsed. A surge current can flow from the first transistor to the second transistor within the predetermined period, and a state in which the load current remains flowing can be avoided and the transistor protection function by the Zener diode can be normally functioned. it can.

  The load driving circuit according to the present embodiment is configured by a diode built-in transistor 10 (first transistor), a diode built-in transistor 20 (second transistor), and a CPU 30 (control circuit), as shown in FIG. ing. In the above configuration, when the driving of the relay 40 is stopped, an example in which a low-level control signal is simultaneously output from the CPU 30 to each base of the NPN transistors 11 and 21 has been described. The timings of the control signals output to the type transistors 11 and 21 are different.

  Next, a time chart of control signals output from the CPU 30 is shown with reference to FIG. The CPU 30 includes a memory (not shown), and outputs a control signal shown in FIG. 1 based on a program stored in advance in the memory.

First, a time chart of control signals output from the CPU 30 is shown with reference to FIG.
(1) When driving of the relay 40 is started The CPU 30 simultaneously outputs a high-level control signal to the bases of the NPN transistors 11 and 21. As a result, the NPN transistors 11 and 12 are simultaneously turned on, and a current flows from the power supply terminal VCC to the NPN transistor 11 via the relay 40.
(2) When driving the relay 40 is stopped The CPU 30 outputs a low level control signal to the base of the NPN transistor 11 while outputting a high level control signal to the base of the NPN transistor 21. That is, the NPN transistor 11 is turned off while the NPN transistor 21 is turned on.

  At this time, no current flows through the relay 40, and a surge is input to the collector of the NPN transistor 11. When the voltage between the collector and the base of the NPN transistor 11 becomes larger than the Zener voltage of the Zener diode 12, a current flows from the Zener diode 12 to the base of the NPN transistor 11. As a result, the NPN transistor 11 is turned on, and a surge current flows as the collector current of the NPN transistor 11. In this way, surge energy is absorbed and the NPN transistor 11 is protected.

  Then, after the NPN transistor 11 is turned off and after a predetermined period (for example, several tens of msec) or more has passed since the surge current has passed from the NPN transistor 11 to the NPN transistor 21, the CPU 30 A low-level control signal is output to each base 21 to turn off both NPN transistors 11 and 21.

  Next, processing of the CPU 30 when stopping driving of the relay 40 will be described. The CPU 30 determines whether or not to stop driving of the relay 40 based on a program stored in the memory, and performs the following process when determining to stop driving of the relay 40.

  First, the NPN transistor 11 is turned off while the NPN transistor 21 is turned on, and it is determined whether or not a predetermined period or longer has elapsed for the NPN transistor 11 to finish supplying a surge current to the NPN transistor 21. Then, when it is determined that a predetermined period or more in which the surge current has finished flowing has elapsed, the NPN transistor 21 is turned off together with the NPN transistor 11.

  As described above, when stopping the driving of the relay 40, the CPU 30 turns off the NPN transistor 11 while turning on the NPN transistor 21, and turns off the NPN transistor 11 while the CPU 30 turns on the NPN transistor 21. Since the NPN transistor 21 is turned off after a lapse of a predetermined period in which the NPN transistor 11 finishes flowing the surge current to the NPN transistor 21 after turning off, the state where the load current remains flowing is avoided, and The protection function of the transistor by the Zener diode can be normally functioned.

  In addition, this invention is not limited to the said embodiment, Based on the meaning of this invention, it can implement with a various form.

  Although the example which drives the relay 40 as load was shown in the said embodiment, it is not limited to a relay, For example, it can apply to the circuit which drives loads, such as a motor and a solenoid. In this case, since the surge waveform varies depending on the load, the period from when the NPN transistor 11 is turned off to when the NPN transistor 21 is turned off when driving the load is appropriately set in consideration of the surge waveform. do it.

  In the above-described embodiment, the predetermined period is a fixed period in which the CPU 30 turns off the NPN transistor 11 while the NPN transistor 21 is turned on and then the NPN transistor 11 finishes flowing the surge current to the NPN transistor 21. Although described, for example, it may be configured to change according to the current value of the surge current or the like.

  In the above embodiment, the example in which the NPN transistors 11 and 21 are controlled by the control signal output from the CPU 30 based on the program stored in the memory of the CPU 30 has been described. For example, hardware such as a counter is used. The control signal for controlling the NPN transistors 11 and 21 may be generated.

  Moreover, although the example which comprised the load drive circuit using the NPN type transistor was shown in the said embodiment, it is not limited to an NPN type transistor, For example, it applies to the case where it comprises using N channel MOSFET. Also good.

  In the above embodiment, the load driving circuit is configured by connecting two transistors in series. However, three or more transistors may be connected in series. In this case, when stopping the driving of the load, the CPU 30 turns off the transistors connected to the load, and then turns off all other transistors after a predetermined period of time during which the transistor finishes flowing the surge current. Control may be performed.

  Moreover, although the example which controls NPN type transistors 11 and 21 from CPU30 was shown in the said embodiment, you may comprise so that NPN type transistors 11 and 21 may be controlled from two different CPU, respectively.

  Moreover, although the example which comprises a load drive circuit using two diode built-in transistors was shown in the said embodiment, you may comprise a Zener diode and a transistor as another components.

It is a time chart which shows control of the load drive circuit concerning one embodiment of the present invention. It is a figure which shows the whole structure of the conventional load drive circuit. It is a figure which shows the waveform of a control signal and a surge voltage. It is a figure showing the whole load drive circuit composition concerning one embodiment of the present invention.

Explanation of symbols

10 ... Transistor with built-in diode (first transistor),
20 ... Transistor with built-in diode (second transistor),
11, 21 ... NPN transistor,
12, 22 ... Zener diode, 13, 23 ... Resistance,
30 ... CPU (control circuit), 40 ... relay (load).

Claims (2)

A first transistor connected to and driving the load;
A second transistor connected in series with the first transistor and driving the load together with the first transistor;
A load driving circuit comprising: a control circuit that controls on / off of the first transistor and the second transistor;
The first transistor includes a Zener diode, and the Zener diode turns on the first transistor when a surge is input from the load to the first transistor, and the first transistor is turned on from the first transistor. The surge current is made to flow to transistor 2
When stopping driving the load, the control circuit turns off the first transistor while turning on the second transistor, and turns off the second transistor after a predetermined period or more has elapsed. A load driving circuit. The predetermined period is a period from when the control circuit turns off the first transistor with the second transistor turned on to when the first transistor finishes supplying a surge current to the second transistor. The load driving circuit according to claim 1, wherein:

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