WO2018174267A1

WO2018174267A1 - Load drive circuit, system using same, and method for controlling drive circuit

Info

Publication number: WO2018174267A1
Application number: PCT/JP2018/011851
Authority: WO
Inventors: 裕樹菅本
Original assignee: ローム株式会社
Priority date: 2017-03-24
Filing date: 2018-03-23
Publication date: 2018-09-27

Abstract

Two control input pins INA, INB receive two control input signals from the outside. Corresponding to the two control input signals INA, INB, a logic circuit 110 generates an internal signal SINT that instructs the state of an H bridge circuit 130. A pre-driver 120 drives the H bridge circuit 130 on the basis of the internal signal SINT. When the two control input signals INA, INB are held in a predetermined state for a predetermined determining time, a standby circuit 160 shifts a drive circuit 100 to be in standby mode.

Description

Load drive circuit, system using the same, and drive circuit control method

The present invention relates to a drive circuit for driving a load such as a motor.

FIG. 1 is a block diagram of a DC motor drive circuit. The drive circuit 100R includes a logic circuit 110, a pre-driver 120, and an H bridge circuit 130. The drive target motor 202 is connected to the output terminals (pins) OUTA and OUTB of the drive circuit 100R. Driving circuit 100R receives the control instruction _{S 1} from an external controller 204 drives the motor 202 in response to the control instruction _{S 1.}

In this driving circuit 100R, the control instruction S ₁ is the torque command and speed command, rather than such position command includes data indicating the state of the H-bridge circuit 130.

The H bridge circuit 130 can take _four states φ ₁ to φ ₄ . H represents a high voltage, L represents a low voltage, and Z represents a high impedance state.
φ ₁ OUTA = Z, OUTB = Z
φ ₂ OUTA = H, OUTB = L
φ ₃ OUTA = L, OUTB = H
φ ₄ OUTA = L, OUTB = L
phi ₄ is a short-circuit braking state may be OUTA = OUTB = H.

For example, the drive circuit 100R includes, in addition to the two output pins OUTA and OUTB, a power supply pin VM and a ground pin PGND of the H bridge circuit 130, a power supply pin VCC for the previous circuit (110 and 120), and a ground pin GND. If you want to accommodate the drive circuit 100R in 8-pin package, the reception of the control command _{S CNT} from the controller 204, two control pins INA, it is possible to assign the INB. When each control pin can be controlled in the high and low 2 states, the four states φ ₁ to φ ₄ can be switched using the two control pins INA and INB.

JP 2008-263733 A

Many ICs (Integrated Circuit) are equipped with a standby mode to reduce power consumption. A general IC includes an enable pin, and is configured to shift to a standby mode by setting the enable pin to a predetermined state.

However, in applications where miniaturization of ICs is prioritized, it is difficult to increase the number of package pins, and standby mode cannot be implemented.

The present invention has been made in view of these problems, and one of the exemplary purposes of an aspect thereof is to provide a drive circuit that can be set to a standby mode without increasing the number of pins.

One embodiment of the present invention relates to a load drive circuit. The drive circuit has an H bridge circuit, one or two control input pins for receiving one or two control input signals indicating the state of the H bridge circuit from the outside, and one or two control input signals. And a logic circuit that generates an internal signal that indicates the state of the transistors that constitute the H-bridge circuit, and a pre-driver that drives the H-bridge circuit based on the internal signal. The drive circuit shifts to the standby mode when one or two control input signals maintain a predetermined state for a predetermined determination time.

According to this aspect, it is possible to switch between a plurality of states of the H-bridge circuit and the standby mode by using one or two control input pins.

The predetermined state may correspond to a high impedance state of the H bridge circuit.

The predetermined state may correspond to a short brake state of the H bridge circuit.

The determination time may be longer than 50 μs. When PWM drive is performed using this drive circuit, the state of the control input pin changes in the PWM cycle. Alternatively, when the stepping motor is driven, the state of the control input pin changes with the frequency (cycle) of the control pulse that defines the rotation speed. In order to suppress noise in the audible band, the PWM frequency and the frequency of the control pulse (that is, the frequency of state change of the control input pin) are set outside the audio band, that is, 20 kHz or more. Therefore, by defining the determination time longer than 50 μs, it is possible to distinguish between an intentional transition instruction to the standby state and a specific state during PWM drive or stepping motor control.

Another aspect of the present invention relates to a method for controlling a drive circuit including an H bridge circuit connected to a motor. The control method includes a step in which the processor changes one or two control input signals that specify the state of the H-bridge circuit in a time shorter than a predetermined period in order to rotate the motor, and one or two controls. Controlling the H-bridge circuit in response to the input signal; and fixing the one or two control input signals to a predetermined state for a predetermined time in order for the processor to shift the drive circuit to a standby mode; A step of transitioning the drive circuit to a standby mode when it is detected that one or two control input signals have maintained the predetermined state for a predetermined time in the drive circuit.

It should be noted that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention that are mutually replaced between methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

According to an aspect of the present invention, it is possible to provide a drive circuit that can be set to the standby mode without increasing the number of pins.

It is a block diagram of the drive circuit of a DC motor. 1 is a circuit diagram of a system including a drive circuit according to a first embodiment. FIG. 3 is a diagram illustrating an example of correspondence between states of control input pins INA and INB, and internal and output states of the drive circuit in the drive circuit of FIG. 2. FIG. 3 is an operation waveform diagram of the drive circuit of FIG. 2. It is a circuit diagram of a system provided with the drive circuit which concerns on 2nd Example. It is a circuit diagram of a system provided with the drive circuit which concerns on 3rd Example. FIGS. 7A to 7C are diagrams showing some examples of correspondence between the state of the control input pin IN in the drive circuit of FIG. 6 and the internal and output states of the drive circuit. It is a circuit diagram of the system which concerns on 4th Example. It is a circuit diagram of a system provided with the drive circuit which concerns on 5th Example. 10 is a time chart showing an example of the operation of the system of FIG. 9. 14 is a circuit diagram of a drive circuit according to Modification 4. FIG. 14 is a circuit diagram of a drive circuit according to Modification 4. FIG. FIG. 10 is a circuit diagram of a system including a drive circuit according to Modification Example 5. FIGS. 14A to 14H are views showing the appearance of the package of the drive circuit.

Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected to each other in addition to the case where the member A and the member B are physically directly connected. It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

<First embodiment>
FIG. 2 is a circuit diagram of a system 200 including the drive circuit 100 according to the first embodiment. The drive circuit 100 includes two control input pins INA and INB, and two control input signals are supplied from the external controller 204 to the control input pins INA and INB. The drive circuit 100 drives a load (for example, the motor 202) connected to the two output terminals OUTA and OUTB according to the two control input signals INA and INB.

The drive circuit 100 includes a logic circuit 110, a pre-driver 120, an H bridge circuit 130, a BGR (bandgap reference) circuit 140, a protection circuit 150, and a standby circuit 160, and is accommodated in one package. The drive circuit 100 may be a functional IC integrated on one semiconductor substrate. Alternatively, the H bridge circuit 130 may be integrated on a separate chip from the other blocks (110, 120, 140, 150, 160).

The H bridge circuit 130 can take _four states φ ₁ to φ ₄ according to the control input pins INA and INB.
φ ₁ OUTA = Z, OUTB = Z
φ ₂ OUTA = H, OUTB = L
φ ₃ OUTA = L, OUTB = H
φ ₄ OUTA = L, OUTB = L

The logic circuit 110 monitors the states (control input signals) of the control input pins INA and INB, and determines which of the states φ ₁ to φ ₄ is in effect. Then, an internal signal S _INT corresponding to the determined state is generated. The internal signal S _INT may be a signal instructing on / off of each of the four transistors M1 to M4 constituting the H-bridge circuit 130. The pre-driver 120 controls the gate voltages of the transistors M1 to M4 of the H bridge circuit 130 based on the internal signal S _INT .

The BGR circuit 140 generates a reference voltage. The protection circuit 150 includes a thermal shutdown (TSD) circuit, an undervoltage lockout (UVLO) circuit, and the like. The protection circuit 150 includes a voltage comparator.

The standby circuit 160 shifts the drive circuit 100 to the standby mode when the two control input signals INA and INB maintain the predetermined state φ for the predetermined determination time τ. In the standby mode, supply of the bias current, bias voltage, and power supply voltage to other circuit blocks other than the logic circuit 110 is stopped, and the current consumption of the drive circuit 100 is reduced to a level of several μA. In FIG. 2, the standby circuit 160 is shown outside the logic circuit 110, but the function of the standby circuit 160 can actually be implemented as a part of the logic circuit 110.

FIG. 3 is a diagram showing an example of the correspondence between the states of the control input pins INA and INB and the internal and output states of the drive circuit 100.

In the first embodiment, the predetermined state φ is the high impedance state φ ₁ of the H bridge circuit 130. Returning to FIG. Standby circuit 160 measures the time that the logic circuit 110 detects a high impedance state phi _1, reaches the determination time tau, to shift the driving circuit 100 to the standby mode. The determination time τ is preferably defined to be longer than 50 μs, for example, set between 50 and 500 μs.

The above is the configuration of the driving circuit 100. Next, the operation will be described. FIG. 4 is an operation waveform diagram of the drive circuit 100 of FIG. The power supply voltage VCC and VM stand up to time _{t 0.} Immediately after startup, the standby mode is set, and the operating current I _CC is very small.

At time _{t 1,} the control input signal INA, the INB changes, the transition to the normal mode. In the normal mode, the state transitions sequentially to the states φ ₃ , φ ₄ , and φ ₂ corresponding to the levels of the control input signals INA and INB. When a transition to state phi ₁ to time t _2, the output is high impedance. When the state φ ₄ continues for the determination time τ at time t ₃ , the standby mode is entered and the operating current I _CC decreases.

Time _{t 4} the control input signal INA, the INB changes, the transition to the normal mode. In the normal mode, the state transitions sequentially to states φ ₂ , φ ₃ , φ ₂ , and φ ₃ corresponding to the levels of the control input signals INA and INB. Supply voltage _{V CC} is below the threshold UVLO circuit at time _{t 5,} becomes undervoltage lockout, the output of the H-bridge circuit 130 becomes a high impedance.

When the power supply voltage _{V CC} at time _{t 6} exceeds the threshold UVLO circuit, undervoltage lockout state is canceled, the control input signal INA, the state of the H-bridge circuit 130 depending on the INB continue to transition.

The above is the operation of the drive circuit 100. According to the drive circuit 100, the four states of the H-bridge circuit 130 are controlled from the outside by using only the two control input pins INA and INB without adding an enable pin, and further shifted to the standby mode. Can do.

In a drive circuit in which a torque command or a speed command is a control input, there is a state in which the control input explicitly instructs the motor stop. For example, a torque command (speed command) of zero is understood as an explicit instruction to stop the motor. Therefore, after waiting for the time required for the motor to completely stop after the torque command (speed command) becomes zero, it is sufficient to shift to the standby mode.

On the other hand, there is no explicit stop instruction in the form of receiving the control input signals INA and INB for instructing the state of the H bridge circuit 130 as in the drive circuit 100 in the present embodiment. This is because in a PWM drive application, a high impedance state repeatedly occurs, and thus the generation of a high impedance state is not necessarily a stop instruction. The same applies to the control of the stepping motor.

Generally, a frequency outside the audible band is used for DC motor PWM drive or stepping motor drive. Therefore, by setting the determination time τ longer than the pulse period (50 μs at the longest), the high impedance state generated during the PWM driving of the DC motor or the driving of the stepping motor is distinguished from the instruction to shift to standby. be able to. In other words, it can be said that the drive circuit 100 supports pulse driving with a cycle shorter than the determination time τ.

Further according to this system 200, the controller 204, a phi ₁ and phi _4, by switching alternately shorter than the determination time τ period, while the motor 202 is stopped, without migrating the driving circuit 100 in the standby mode It is also possible to continue to maintain the normal mode. Such control cannot be realized by a drive circuit that receives a torque command or a speed command.

In standby mode, the bias circuit stops, so it takes a few μs to return to normal mode. On the other hand, in PWM drive, there is a case where the output voltage of the H bridge circuit is desired to be changed at a slew rate of several tens ns. If control that shifts to standby immediately when a high-impedance control input is detected, the rounding of the waveform of the output voltage of the H-bridge circuit during PWM driving becomes large, and the usable applications are limited. In the embodiment, since the waveform of the output voltage of the H-bridge circuit does not occur, it can be applied to a wide range of applications.

<Second embodiment>
FIG. 5 is a circuit diagram of a system 200A including a drive circuit 100A according to the second embodiment. The drive circuit 100A includes a PWM (Pulse Width Modulation) circuit 170 for switching the drive signal during the energization period to the motor. A shunt resistor Rs is provided on the path of the drive current, specifically between the PGND pin and the external ground, and a voltage drop (current detection signal) Vs corresponding to the drive current flowing through the motor 202 is provided in the shunt resistor Rs. Will occur. The shunt resistor Rs may be built in the drive circuit 100A.

The PWM circuit 170 is a pulse-by-pulse current limiting circuit, and generates the PWM signal S _PWM based on the current detection signal Vs. The PWM circuit 170 operates in synchronization with the clock generated by the oscillator 172. For example, the PWM circuit 170 changes the PWM signal S _PWM to the first level (for example, high) in response to the positive edge of the clock CK generated by the oscillator 172. The PWM circuit 170 compares the current detection signal Vs with a limit value V _CL that defines the upper limit of the drive current, and detects V _S > V _CL , that is, when the drive current reaches the limit value, the PWM signal S _PWM To the second level (eg, low).

The PWM signal S _PWM is supplied to the pre-driver 120. The pre-driver 120 logically synthesizes the PWM signal S _PWM with the internal signal S _INT and controls the H bridge circuit 130. The logic synthesis function may be implemented in the logic circuit 110.

The standby circuit 160 may stop the PWM circuit 170 in the standby state. Specifically, current consumption can be reduced by cutting off the current of the comparator included in the PWM circuit 170. Further, the oscillator 172 that generates the clock CK may be stopped in the standby state. This can further reduce current consumption.

<Third embodiment>
FIG. 6 is a circuit diagram of a system 200B including a drive circuit 100B according to the third embodiment. The drive circuit 100B includes one control pin IN. A high / low binary control input signal IN is input to the control pin IN. The logic circuit 110 transitions the state of the bridge circuit 130 in response to the transition of the state of the control input pin IN. Further, when the control input pin IN remains in a predetermined state for a predetermined time, the standby circuit 160 shifts the drive circuit 100B to the standby state.

FIGS. 7A to 7C are diagrams showing some examples of the correspondence between the state of the control input pin IN in the drive circuit 100B of FIG. 6 and the internal and output states of the drive circuit. The H bridge circuit 130 can take _two states φ ₁ and φ ₂ according to the control input pin IN.
φ ₁ OUT1 = L, OUT2 = H
φ ₂ OUT1 = H, OUT2 = L

The logic circuit 110 monitors the state (control input signal) of the control input pin IN, and determines whether the state is φ ₁ or φ ₂ . Then, an internal signal S _INT corresponding to the determined state is generated.

The standby circuit 160 shifts the drive circuit 100B to the standby mode when the first state φ ₁ (that is, the IN pin is low) lasts for a predetermined time. In the standby mode, the logic circuit 110 changes the internal signal S _INT so that the H bridge circuit 130 is in a state φs (short brake state) different from the first state φ ₁ and the second state φ ₃ . Thereby, the motor 202 can be fixed in the standby mode.

In the example of FIG. 7A, the state φs is a short brake state with the output low fixed (OUT1 = L, OUT2 = L), the transistors M2 and M4 are on, and M1 and M3 are off.

In the example of FIG. 7B, the state φs is a short brake state in which the output is fixed high (OUT1 = H, OUT2 = H), the transistors M2 and M4 are off, and M1 and M3 are on.

In the example of FIG. 7C, the state φs is a high impedance state of OUT1 = Z and OUT2 = Z, and the transistors M1 to M4 are off.

In FIGS. 7A to 7C, the continuation of the second state φ ₂ (IN = H) for a predetermined time may be a condition for shifting to the standby mode.

It is also possible to select the output state φs in the standby mode. That is, when one of the first state φ ₁ and the second state φ ₂ lasts for a predetermined time, φs is set to the short brake state, and the other of the first state φ ₁ and the second state φ ₂ lasts for a predetermined time , Φs may be in a high impedance state.

<Fourth embodiment>
The drive circuit 100B in FIG. 6 can be used for driving a stepping motor. FIG. 8 is a circuit diagram of a system 200C according to the fourth embodiment. The system 200C includes two drive circuits 100B shown in FIG. The output of one drive circuit 100B_A is connected to one coil of the stepping motor 202C, and the output of the other drive circuit 100B_B is connected to the other coil of the stepping motor 202C. The controller 204 controls the stepping motor 202C by supplying the control input signal INA to the drive circuit 100B_A and the control input signal INB to the drive circuit 100B_B. The waveforms of the control input signals INA and INB are selected according to the driving method of the stepping motor (one-phase example, 1-2-phase excitation, 2-phase excitation, etc.).

<Fifth embodiment>
FIG. 9 is a circuit diagram of a system 200D including a drive circuit 100D according to the fifth embodiment. The drive circuit 100D can be understood as a circuit in which the drive circuits 100B_A and 100B_B in FIG. 8 are integrated. The outputs OUTA and OUTB can take four states φ ₁₁ to φ ₁₄ depending on the combination of INA and INB.
・ Φ ₁₁ INA = L, INB = L
OUTA1 = L, OUTA2 = H, OUTB1 = L, OUTB2 = H
_{· Φ 12 INA = H, INB} = L
OUTA1 = H, OUTA2 = L, OUTB1 = L, OUTB2 = H
_{· Φ 13 INA = L, INB} = H
OUTA1 = L, OUTA2 = H, OUTB1 = H, OUTB2 = L
_{· Φ 14 INA = H, INB} = H
OUTA1 = H, OUTA2 = L, OUTB1 = H, OUTB2 = L

FIG. 10 is a time chart showing an example of the operation of the system 200D of FIG. Here, 1-2 phase excitation is taken as an example. The standby circuit 160 of the drive circuit 100D monitors all edges of the two control input signals INA and INB. When the edge interval exceeds a predetermined determination time τ, the standby mode is entered. In other words, when any one of the four states φ ₁₁ to φ _{14 is} maintained for a predetermined time, the standby mode is entered. During the standby mode, the

bridge circuits

130A and 130B are fixed to a predetermined state φs (for example, a high impedance state or a short brake state). Alternatively, the predetermined state φs may be the immediately preceding state (φ _{13 in} the example of FIG. 10).

When the next edge is detected in the standby mode, the standby mode is canceled, and then the state transitions to the states φ ₁₁ and φ ₁₂ corresponding to the two control inputs INA and INB.

The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications may exist in each of those constituent elements, each processing process, and a combination thereof. Hereinafter, such modifications will be described.

(Modification 1)
Standby circuit 160 in the embodiment is a high impedance state phi ₁ is not limited thereto but was triggered the transition to the standby mode, the short brake state phi _4, may be used as a trigger for transition to the standby mode. That is, when the control input signal which instructs the short brake state phi ₄ that (INA = INB = H) has a duration determined tau, may be shifted to the standby mode.

(Modification 2)
In the embodiment, a single-phase DC motor is used as a load. The present invention is also applicable to a three-phase inverter and a stepping motor drive circuit.

(Modification 3)
Furthermore, the load is not limited to the motor, and the drive circuit 100 may be a part of a flyback converter, a forward converter, a DC / DC converter, or the like.

(Modification 4)
Although the power supply / ground of the H bridge circuit 130 is separated from the power supply / ground of the logic circuit 110 and the pre-driver 120 in the embodiment, they may be shared. FIG. 11 is a circuit diagram of a drive circuit 100E according to the fourth modification. The drive circuit 100E has two power supply pins common to the drive circuit 100 of FIG. 2, and two ground pins.

FIG. 12 is a circuit diagram of the drive circuit 100F according to the fourth modification. The drive circuit 100F is obtained by sharing the two power pins of the drive circuit 100B of FIG. 6 and sharing the two ground pins.

(Modification 5)
FIG. 13 is a circuit diagram of a system 200G including a drive circuit 100G according to Modification 5. The drive circuit 100G includes a half-bridge circuit 130G at its output stage instead of the H-bridge circuit 130. There is one control input pin IN. The output pin of the half bridge circuit 130G is connected to one end of a motor 130G (coil), and a predetermined voltage (power supply voltage or ground voltage) is applied to the other end of the motor 130G.

Finally, an example of a package of the drive circuit 100 is shown. 14A to 14H are views showing the appearance of the package of the drive circuit 100. FIG. FIG. 14A shows an 8-pin package. For example, the drive circuit 100 of FIG. 2 can be accommodated in this package. Each pin of the drive circuit 100 in FIG. 2 may be arranged as follows.
Name Pin number VM 2
PGND 8
VCC 4
GND 5
INA 3
INB 6
OUTA 1
OUTB 7

FIG. 14B shows a 6-pin package. For example, the drive circuit 100E of FIG. 11 can be accommodated in this package. Each pin of the drive circuit 100E of FIG. 11 may be arranged as follows.
Name Pin No. VCC 2
GND 5
INA 3
INB 4
OUTA 1
OUTB 6

FIG. 14C shows a 5-pin package. For example, the drive circuit 100F of FIG. 12 can be accommodated in this package. Each pin of the drive circuit 100F may be arranged as follows.
Name Pin number VM 5
PGND 2
IN 4
OUTA 1
OUTB 3

FIG. 14 (d) shows a 4-pin package. For example, the drive circuit 100G of FIG. 13 can be accommodated in this package. Each pin of the drive circuit 100G may be arranged as follows.
Name Pin No. VCC 1
GND 2
IN 3
OUT 4

FIGS. 14E to 14F show 8-pin, 6-pin, 5-pin, and 4-pin CSP (Chip Size Package).

Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Drive circuit, 110 ... Logic circuit, 120 ... Pre-driver, 130 ... H bridge circuit, 140 ... BGR circuit, 150 ... Protection circuit, 160 ... Standby circuit

The present invention can be used for motor driving technology.

Claims

A load drive circuit,
A bridge circuit;
One control input pin for receiving one control input signal for instructing the state of the bridge circuit from the outside;
In response to the one control input signal, a logic circuit that generates an internal signal that indicates a state of a transistor constituting the bridge circuit;
A pre-driver for driving the bridge circuit based on the internal signal;
With
The drive circuit, wherein the one control input signal is configured to shift to a standby mode when a predetermined state is maintained for a predetermined determination time.
A load drive circuit,
A bridge circuit;
Two control input pins for receiving two control input signals indicating the state of the bridge circuit from the outside;
In response to the two control input signals, a logic circuit that generates an internal signal that indicates a state of a transistor constituting the bridge circuit;
A pre-driver for driving the bridge circuit based on the internal signal;
With
The drive circuit, wherein the two control input signals are configured to shift to a standby mode when a predetermined state is maintained for a predetermined determination time.
3. The drive circuit according to claim 1, wherein the predetermined state corresponds to a high impedance state of the bridge circuit.
3. The drive circuit according to claim 1, wherein the predetermined state corresponds to a short brake state of the bridge circuit.
5. The driving circuit according to claim 1, wherein the determination time is longer than 50 μs.
6. The driving circuit according to claim 1, wherein the load is a motor.
A processor;
A motor,
The drive circuit according to any one of claims 1 to 6, wherein the motor is driven in response to one or two control input signals from the processor;
With
The processor fixes the one or two control input signals to a predetermined state for a predetermined time or more when the drive circuit is shifted to a standby mode.
A method for controlling a drive circuit including a bridge circuit connected to a motor,
A processor changing one or two control input signals specifying the state of the bridge circuit in a time shorter than a predetermined period in order to rotate the motor;
Controlling the bridge circuit in response to the one or two control input signals;
The processor fixing the one or two control input signals to a predetermined state for a predetermined time in order to shift the driving circuit to a standby mode;
In the driving circuit, when it is detected that the one or two control input signals maintain the predetermined state for the predetermined time, the driving circuit transits to a standby mode;
A control method comprising: