JP4232589B2 - Duplex controller and its equalization mode decision method - Google Patents

Description

  The present invention relates to an equalization process and the like in a duplex controller (programmable controller) having a duplex configuration of standby redundancy.

  Currently, in plants, factories, etc., FA (factory automation) is realized by using many controllers such as programmable controllers for sequence control of machines such as machine tools and measuring devices.

  In such a programmable controller system, in order to improve reliability, the CPU module (controller body) may have a standby redundant dual configuration. The redundant redundant configuration of standby redundancy consists of two CPU modules as one set, one as the active system and the other as the standby system. If a switching factor such as this occurs, the standby CPU module is switched to the active system.

FIG. 7 shows a general system configuration of the controller which is duplicated to provide redundancy.
The duplex controller system shown in the figure includes an I / O unit including a CPU module 101-1, a CPU module 101-2, and a plurality of I / O units 102-1 to 102-n for inputting / outputting data to / from each control target device. The O group 102 is configured. Here, a case where the CPU module 101-1 is an active system and the CPU module 101-2 is a standby system will be described as an example.

  The CPU module 101 which is an active system executes each of the I / O units 102-1 to 102-102 by executing a program stored therein (usually a program executed at regular intervals; a regular cycle program). Control data is output to n (or a sensor measurement value or the like is read from each I / O unit) to control each control target device.

  On the other hand, the standby CPU module 101-2 monitors the active CPU module 101-1, and if any switching factor such as a failure occurs in the active CPU module 101-1, the active / standby CPU module 101-1 is activated. By executing the switching process, the CPU module 101-2 becomes the active system, and the process performed by the CPU module 101-1 is taken over.

  The CPU module 101-1 and the CPU module 101-2 store a plurality of fixed-cycle programs that are activated and executed at a fixed cycle (here, three fixed-cycle programs A, B, and C). Only the CPU module 101-1 in the active system executes these periodic programs to perform control processing of the I / O device, and the CPU module 101-2 in the standby system executes these periodic programs. Is not executed. These fixed-cycle programs have priority levels (priority level: A> B> C). When the startup cycle of a fixed-cycle program with a high priority level is reached, the fixed-cycle program being executed with a low priority level is interrupted. The fixed-cycle program with a high priority level is preferentially executed.

  The CPU module 101-1, the CPU module 101-2 and the I / O group 102 are connected by a system bus 103, and the active system CPU module 101-1 is connected to each I / O unit 102-1 via the system bus 103. Output data (control data) to 102-n, and input data such as measured values from connected control target devices is received from the I / O units 102-1 to 102-n. Yes.

  Further, an equalization bus 104 is provided between the duplicated CPU module 101-1 and CPU module 101-2 so that the control data is consistent when switching between the active system and the standby system occurs. Therefore, the equalization processing is performed by transmitting control data from the active CPU module 101-1 to the standby CPU module 101-2 via the equalization bus 104.

  As shown in FIG. 8, in the conventional duplex controller, when the periodic programs A, B, and C are executed by the active system CPU module 101-1, processing by the other periodic programs is completed and fixed. Then, the processing returns to the fixed cycle program C having the lowest priority level, and after the calculation processing by the fixed cycle program C is completed, equalization is performed on all control data used in the fixed cycle programs A, B, and C. Therefore, the execution order of each process performed in the periodic programs A, B, and C is input processing → program calculation → output processing, and the periodic program C having the lowest priority level is subjected to equalization processing. The execution order is input processing → program operation → control data equalization → output processing. In the figure, “ON” means input processing, “Den” means program calculation, “etc.” means control data equalization, and “OUT” means output processing.

  FIG. 9 is a diagram showing a program execution state when the active / standby CPU is switched during execution of the fixed cycle program. In FIG. 9, there are five fixed-cycle programs A to E, but it does not matter how many fixed-cycle programs are present (if there are two or more, this problem occurs).

  When an active / standby system switching factor occurs during the calculation of each periodic program of the active system CPU module 101-1, the CPU module 101-2 that has newly become an active system by switching the active / standby system In order to guarantee the consistency of the control data, the fixed-cycle program is executed in the form of taking over the process from the state at the time t1 in FIG. 9 where the control data is finally equalized.

  For example, when a CPU switching factor occurs at time t2 in FIG. 9, the CPU module 101-2 that newly becomes an active system executes the program from the state at time t1. However, in this case, since the periodic programs A, B, and C have already transmitted output data to the I / O unit at the time t2, the control data and the output state from the I / O unit are inconsistent. There is a case. In addition, since the control data is finally returned to the equalized state and the process is taken over, the return time may be increased.

  Further, in the conventional controller, when the active / standby CPU is switched, there is a problem that the execution cycle time of the fixed cycle program and the execution order of the fixed cycle programs cannot be maintained in the processing after the switching.

  In the conventional controller, when the active / standby CPU module is switched, there is a problem that the execution cycle time of the fixed cycle program and the execution order of the fixed cycle programs cannot be maintained in the processing after the switching.

The related art described above is described in, for example, Patent Document 1, Non-Patent Document 1, and the like.
JP 2002-149212 A "Control function of the control station of the integrated control system MICREX-IX"; Fuji Time Report Vol. 67 NO. 6, 1994, pages 345-348

The applicant of the present application has already proposed the invention of Japanese Patent Application No. 2002-104380 (hereinafter referred to as a prior application) for the problems described above.
Although not specifically shown here, the dual controller system of the prior application has a CPU module a and a CPU module b (not shown), and is equalized between the CPU module a and the CPU module b as in the configuration of FIG. It is assumed that a bus is provided and equalization is performed via the equalization bus. In the following description, it is assumed that the CPU module a is an active system and the CPU module b is a standby system.

  As shown in FIG. 10, in the duplex controller of the prior application, when the periodic program A, B, C (priority level: A> B> C) is executed in the active system CPU module a, The processing execution order is input processing → program operation → control data equalization → output processing. That is, every time each of the periodic programs A, B, and C is executed, control data equalization processing is performed (hereinafter, such equalization is referred to as “multi-equalization”. The equalization is called “single equalization”). By performing such multi-equalization, when operation / standby switching occurs, consistency between the equalized data and output data to the I / O unit can be ensured, and at the time of operation / standby switching. The effect that the overhead can be reduced is obtained.

  Further, in the conventional single equalization process, user data used by the user is equalized, whereas in the multi-equalization process of the prior application, a system such as program interrupt information and program execution schedule information is further provided. Information is also equalized.

11 shows an example of program interrupt information, and FIG. 12 shows an example of program execution schedule information.
In FIG. 11, the program counter, various flags, register values, and the like are equalized as program interrupt information for all the periodic programs installed as the periodic programs A, B, and C. In FIG. 11, the information for all installed periodic programs is equalized as program interrupt information. However, a program that has been saved as an interrupt at the time of equalization processing is required. Only the information for the program may be equalized. The program counter indicates the last executed program (row) for each fixed cycle program.

  The CPU module b that has been switched to active / standby and becomes a new active system uses the program interrupt information that has been equalized to continue the program execution that was interrupted from the state at the time of interruption. Can be done.

  The program execution schedule information shown in FIG. 12 includes, for each fixed-cycle program, a fixed-cycle setting time that is the execution cycle of the fixed-cycle program, and an execution cycle that indicates an elapsed time after the previous fixed-cycle program is executed. Elapsed time etc.

  In the duplexed controller system of the above-mentioned prior application, when the operation / standby switching occurs, as shown in FIG. 13, the CPU module b which has newly become the active system is based on the equalized system information. Control can be continued by continuing the interrupted fixed-cycle programs B and C from the state at the time of suspension. In the example shown in the figure, the operation / standby switching was performed because some abnormality occurred during the execution of the periodic program B. However, since the system information is equalized in the above-mentioned prior application, the operation is newly started. The CPU module b that has become a system can continuously execute the program from the point of interruption of the periodic program B.

  However, such control is based on the precondition that the fixed cycle program held by the CPU module a matches the fixed cycle program held by the CPU module b.

  If the fixed cycle program held by the active CPU module a is not the same as the fixed cycle program held by the standby CPU module b, for example, as shown in FIG. The program B and the standby CPU module b operate / standby while holding the periodic program B ′ (B ′ is a modified version of B, ie, a modified version, an upgraded version, etc.) When switching occurs, for example, the fixed cycle program B ′ is executed without matching the program counters, and there is a problem that control cannot be continued.

The case where the periodic program is not the same between the active system and the standby system may occur, for example, in the situation described below.
In other words, at the operation site of the programmable controller, there is a case where the fixed-cycle program is partially modified locally, and at that time, it is desired to check whether the fixed-cycle program after the modification can operate normally without stopping the system. There is a case. In this case, the modified periodic program is downloaded only to the standby CPU module b while the active CPU module a is executing the periodic program. Thereafter, the operation / standby switching is performed, and the fixed-cycle program after remodeling is executed in the CPU module b which has newly become an active system, and it is confirmed whether or not normal operation is performed. If an abnormal operation occurs, the operation / standby switching is performed again, and the CPU module a that has become active again returns to the state in which the fixed-cycle program before modification is executed, and the CPU module that has become standby. Return the periodic program of b to the state before the modification. On the other hand, if it can be confirmed that the operation is normal, the fixed-cycle program after the modification is downloaded to the CPU module a (in the standby system) without switching the operation / standby again.

In the situation described above, there is a time zone in which the fixed-cycle program does not match between the active CPU module and the standby CPU module.
Or, if one of the CPU modules fails, etc., and the CPU module is replaced (if the active CPU module fails, the standby CPU module becomes a new active system, , Manually replace the failed CPU module with another one), the replaced CPU module should originally contain the same periodic program as the paired CPU, but due to human error, for example, A different periodic program may be stored. It should be noted that “different periodic program” mentioned here does not mean that it is completely different. As described above, each periodic program is usually remodeled (upgrade) at any time, and here, it means that the versions are different.

  Alternatively, when constructing a new system, the newly installed active / standby CPU modules should store the same periodic program. However, due to human error, for example, There may be cases where different periodic programs are stored. For example, there may be a case in which a new version is stored on one side and an old version of the periodic program is stored on the other side by mistake.

The situation described above is an example, but anyway, for some reason, the fixed-cycle program of the active CPU module and the fixed-cycle program of the standby CPU module that should be the same may not be the same. If the operation / standby switching occurs in such a state, the above-described problem occurs.

An object of the present invention is a duplex controller system for performing multi-equalization in which control data equalization processing is performed for each execution of a fixed-cycle program during control data equalization processing of a fixed-cycle program, To provide a duplex controller system capable of performing control after operation / standby switching without problems even if the periodic programs differ between the active system and the standby system, and a method thereof.

  The duplex controller system according to the present invention has an active system and a standby system controller, and in a duplex controller system that executes a plurality of fixed-cycle programs, the active system controller and the standby system controller are respectively connected to the active system. Each time each periodic program is executed in the system controller, the equalization processing means for executing the multi-equalization process for equalizing the system information and the other controller's fixed period program are read from each other, and Equalization that switches to equalization processing in a single equalization mode that does not require system information when it is determined that there is a mismatch by the collation means for collating whether or not it matches the periodic program And mode switching means.

  In the duplexed controller system having the above-described configuration, since the multi-equalization process is performed in the normal state, the multi-equalization process for performing the equalization process for each execution of the fixed-cycle program is executed as in the prior application. Consistency with the output data to the unit can be ensured and overhead during switching between operation and standby can be reduced. Furthermore, since the system information is also equalized in this multi-equalization process, if an operation / standby switching factor occurs, the newly active controller will continue to program from the point at which the periodic program is interrupted. Can be executed.

  However, if the periodic programs held by each controller are different from each other (for example, when only one version is upgraded), there is a problem when trying to continue executing the program using equalized system information. Arise.

  Therefore, when it is determined that the program does not match by the checking means, the mode is temporarily switched to the single equalization mode (conventional equalization method). In the single equalization mode, since the program cannot be continuously executed from the point of interruption of the fixed cycle program, the above problem does not occur. It should be noted that after the operator or the like later performs an operation for matching the fixed period programs of the two controllers, the multi-equalization mode is restored.

The collation process by the collation means is executed at the time of system initialization, for example.
Or, for example, when the standby controller is activated while the active controller is in operation, the verification process by the verification unit is executed in the standby controller along with the activation, and is activated in the active controller. It is executed in response to a check request issued from the standby controller.

  Alternatively, the collating process by the collating means is executed when the fixed-cycle program of one controller is changed while both the active / standby controllers are in operation, in accordance with the program change. The other controller is executed in response to a check request issued from the one controller.

  Either the single equalization or the multi-equalization uses the same check request because the data to be equalized is different (as described above, the system information is also equalized in the multi-equalization). Only one controller changes the equalization mode because of a problem.

  Further, for example, during the collation processing by the collation means, the equalization processing by the single equalization mode is executed regardless of the coincidence / non-coincidence of the periodic programs based on the fail-safe concept.

  According to the duplex controller system and the program unit equalization method of the present invention, in the equalization processing of the fixed cycle program, the data equalization processing including the system information is performed for each execution of the fixed cycle program. The effect of the prior application, that is, the consistency between the equalized data and the output data to the I / O unit can be secured, the overhead at the time of switching between operation and standby can be reduced, and the program can be continuously executed from the middle of the interruption. If there is a possibility that the periodic program is different between the active system and the standby system, check whether the regular program is the same between the active system and the standby system. If they are not the same, it is possible to switch to single equalization mode, so that even if the periodic program is different, there is no problem after switching between operation and standby. Control can be performed.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a configuration block diagram of a programmable controller main body (CPU module) in a duplex controller system according to the present embodiment.

  The duplex controller system shown in FIG. 1 includes a CPU module 1 and a CPU module 2, and the CPU module 1, the CPU module 2, and various I / O groups (not shown) are connected via a system bus 4. ing. Further, an equalization bus 3 is provided between the CPU module 1 and the CPU module 2. In the following description, it is assumed that the CPU module 1 is an active system and the CPU module 2 is a standby system.

The CPU modules 1 and 2 are programmable controller bodies, but only the configuration relating to the description of this example is shown here, and the other configurations are omitted.
In FIG. 1, the active CPU module 1 includes a program RAM 11, a data RAM 12, an equalization bus control unit 13, a reception buffer RAM 14, a control unit 15, and the like. Other configurations are omitted because they are not particularly relevant to the description here, as described above.

  The program RAM 11 stores a user program 11a. The user program 11a is, for example, the above periodic program. In the system of this example, the program RAM 11 further stores an application program for realizing the processing on the CPU module 1 side shown in FIGS.

  The data RAM 12 has a user data area 12a. For example, equalization data (user data) corresponding to each fixed cycle program is stored in the user data area 12a.

  The equalization bus control unit 13 is a configuration dedicated to equalization processing for performing equalization via the equalization bus 3. When data to be equalized is passed from the control unit 15, In conjunction with the equalization bus controller 23, the equalization data is stored in the reception buffer RAM 24 on the standby side. The equalization bus control unit 13 corresponds to “SGM (Sameness data Gather Memory control)” described in Non-Patent Document 1, for example.

  The control unit 15 is a central processing unit (CPU chip or the like) that controls the entire CPU module 1, and normally uses multi-equalization similar to that of the prior application by using an application program stored in the program RAM 11. In a situation where it is necessary to execute equalization processing and confirm the coincidence / non-coincidence of the periodic programs, the CPU module 1 side processing shown in FIGS. The process shifts to the equalization process. That is, the control unit 15 performs equalization for each execution of each periodic program, and performs an equalization processing function for executing multi-equalization processing so that the equalized data includes system information, and standby The periodic function of the CPU module 2 of the system is read, and a collation function for collating whether or not it coincides with the regular period program of its own CPU module; An equalization mode switching function for switching the processing to an equalization process in a single equalization mode that does not require system information is realized. Further, the control unit 15 holds the system information in its internal memory.

  The standby CPU module 2 includes a program RAM 21, a data RAM 22, an equalization bus control unit 23, a reception buffer RAM 24, a control unit 25, and the like. Since this configuration itself is the same as that of the active CPU module 1, although not specifically described, the control unit 25 uses an application program stored in the program RAM 21 to perform the CPU shown in FIGS. The process on the module 2 side is executed. Further, unlike the control unit 15, the control unit 25 does not execute each periodic program. However, this is a story when the CPU module 2 is a standby system, and when it is an active system, the control unit 25 also executes each periodic program.

  2, 3, and 4 show specific examples of the equalization mode determination process executed by the control unit 15 and the control unit 25. The processes in FIGS. 2 to 4 are basically the same, and are shown in FIGS. 2, 3, and 4, respectively, according to various situations described in the above “problem to be solved by the invention”. In such a case, it is checked whether or not the fixed cycle programs match between the active system and the standby system, and if necessary, the mode is temporarily shifted to the single equalization mode. Note that commands and programs between the CPU module 1 and the CPU module 2 in FIGS. 2 to 4 may be transmitted / received via the equalization bus 3 or the system bus 4.

FIG. 2 is a flowchart of the equalization mode determination process according to the first embodiment.
In the first embodiment, the equalization mode determination process is executed when both the active system / standby system CPU modules are activated almost together. This assumes, for example, the above-mentioned case “when an active / standby CPU module is newly installed”.

  As shown in FIG. 2, when the controller 15 of the active CPU module 1 issues a collation request for an application program (fixed cycle program) at the time of system initialization (step S11), first, the equalization mode up to that time is first Regardless of what is, the single equalization mode is forcibly set (step S12). In other words, the equalization process in the single equalization mode is executed during the equalization mode determination process according to the fail-safe concept. Next, a program read command is transmitted to the standby CPU module 2, and the standby CPU module 2 side returned in response to the processing of step S23 on the standby CPU module 2 side to be described later. Are stored in a buffer (not shown), for example (step S13).

  In addition, when a program read command is sent from the standby CPU module 2 side by the processing in step S24 on the standby CPU module 2 side, which will be described later, an application program on the active CPU module 1 side Is returned to the standby CPU module 2 (step S14).

  Next, the active CPU module 1 collates the application program on the standby CPU module 2 side received and stored in step S13 with its own application program, and determines whether or not they match. (Step S15). For this collation / coincidence determination, an existing method may be used. For example, each program is compared line by line to determine coincidence / non-coincidence. In addition, here, it is not assumed that the program mismatch is completely different. For example, it is assumed that the same periodic program A has different versions. Therefore, for example, the collation compares and collates the fixed cycle program A of the active CPU module 1 with the fixed cycle program A of the standby CPU module 2. Of course, other periodic programs B, C, etc. are similarly compared and verified. When all the fixed cycle programs match, it is determined that they match.

  If it is determined that they match, the equalization processing is changed to the multi-equalization mode (because the processing in step S12 is in the single equalization mode), and if it is determined that they do not match, The equalization process remains in the single equalization mode (step S16).

  The multi-equalization mode is, as described above, equalization processing of the above-mentioned prior application, that is, equalization is performed every execution of each periodic program, and the equalization data includes system information. In this mode, the equalization process is executed. In addition, as described above, the single equalization mode is used for all the controls used in all the periodic programs after the conventional equalization process, that is, the computation process of the periodic program with the lowest priority level is completed. In this mode, equalization processing is performed on data. In this mode, system information does not need to be equalized.

  On the other hand, the equalization mode determination process on the standby CPU module 2 side in FIG. 2 is almost the same as that of the active CPU module 1. That is, when the control unit 25 issues a verification request for an application program (fixed cycle program) at the time of system initialization (step S21), first, regardless of what the previous equalization mode is, a forced single The equalization mode is set (step S22). In other words, the equalization process in the single equalization mode is executed during the equalization mode determination process according to the fail-safe concept. Next, the application program on the active CPU module 1 side is read (step S24).

  Further, when a program read command is sent from the active CPU module 1 side by the processing of step S13 on the active CPU module 1, the application program on the standby CPU module 2 side is executed. A reply is sent to the CPU module 1 (step S23).

  Then, the own application program and the application program of the active CPU module 1 are collated (step S25), and the equalization mode is determined according to the coincidence / mismatch as in step S16 (step S26). .

FIG. 3 is a flowchart of the equalization mode determination process according to the second embodiment.
The second embodiment is an equalization mode determination process when the active CPU module 1 is already in operation and the standby CPU module 2 starts up. This assumes, for example, “when one CPU module has been replaced because it has failed or the like”.

In FIG. 3, processes that are substantially the same as the processes in FIG. 2 are given the same step numbers. Here, only parts different from the processing of FIG. 2 will be described.
In the process of FIG. 3, when the standby CPU module 2 is activated by the initial process, the standby CPU module 2 checks whether or not the active CPU module 1 is in operation. In addition to issuing an application program (fixed cycle program) verification request and starting the equalization mode determination process, an application program verification request command is issued to the active CPU module 1 (step S31). If the result of the check indicates that the system is not in operation, the processing of FIG. 2 is performed.

  When the active CPU module 1 receives the application program verification request command, it starts the equalization mode determination process (step S41). That is, compared with the first embodiment, in the case of the second embodiment, the active CPU module 1 is in operation and the initial process that triggers the start of the equalization mode determination process is not performed. In the method of this example, since there is no meaning unless the active CPU module 1 and the standby CPU module 2 are in the same equalization mode, the equalization mode determination process is also performed in the active CPU module 1. Therefore, the application program verification request command is issued. The subsequent steps S12 to S17 on the active CPU module 1 side and steps S22 to S27 on the standby CPU module 2 side are substantially the same as the processing in FIG.

FIG. 4 is a flowchart of the equalization mode determination process according to the third embodiment.
In the third embodiment, for example, as described above, when an application program of one of the CPU modules (here, the active CPU module 1) is changed, the other CPU module is not changed. Therefore, the equalization mode determination process is performed.

In FIG. 4, the same step number is attached | subjected about the process substantially the same as the process of FIG. Here, only parts different from the processing of FIG. 2 will be described.
First, although not specifically shown in FIG. 1, a programmable controller support device 5 is usually connected to each of the CPU modules 1 and 2 via, for example, some dedicated line. Download the modified version, upgraded version, etc.

In the case shown in the figure, as an example, a modified version C ′ of an existing application program C is downloaded.
When the CPU module 1 of the active system receives the above-mentioned changed version of the application program C ′ from the programmable controller support device 5 together with the change command (step S51), first, the existing application program held in the memory or the like. A process of replacing C with the modified version of the application program C ′ is executed (step S52), and subsequently, a request for collation of the application program (fixed period program) is issued to start the equalization mode determination process. In addition, an application program verification request command is issued to the standby CPU 2 (step S53).

  When receiving the application program collation request command, the standby CPU module 2 starts the equalization mode determination process (step S61). That is, as compared with the first embodiment, in the second embodiment, the standby CPU module 2 does not perform the initial process that triggers the start of the equalization mode determination process. Since there is no meaning unless the active CPU module 1 and the standby CPU module 2 are in the same equalization mode, the standby CPU module 2 also performs the equalization mode determination process in the above-described case. Issue an application program verification request command. The subsequent steps S12 to S17 on the active CPU module 1 side and steps S22 to S27 on the standby CPU module 2 side are substantially the same as the processing in FIG.

  When the application program does not match between the active CPU module 1 and the standby CPU module 2 by the equalization mode determination process of the first to third embodiments described above, the system information as shown in FIG. By changing to the mode for performing equalization at the minimum level fixed period program end that does not require continuation of the program, that is, the single equalization mode, as shown in FIG. Even if an operation / standby switching factor such as an abnormality occurs, the CPU module 2 that newly becomes an active system re-executes the process from the beginning (the process is not resumed from the middle of the calculation using the system information). Therefore, after the operation / standby switching, the periodic program execution process can be continued without any problem.

  Further, from the concept of fail-safe, the single equalization mode is switched during the equalization mode determination process.

It is a block diagram of the programmable controller main body (CPU module) in the dual controller system of this example. It is a flowchart figure of the equalization mode determination process by a 1st Example. It is a flowchart figure of the equalization mode determination process by a 2nd Example. It is a flowchart figure of the equalization mode determination process by a 3rd Example. It is a figure which shows the program execution state at the time of single equalization mode. It is a figure which shows the program execution state at the time of operation / standby switching generation | occurrence | production in single equalization mode. FIG. 2 is a general system configuration diagram of a controller that is duplicated to provide redundancy. It is a figure which shows an example of the conventional fixed-cycle program execution state. It is a figure which shows the execution state of a program when switching of active system / standby system CPU generate | occur | produces during the fixed-cycle program execution in the conventional system. It is a figure which shows an example of the fixed period program execution state by the multi-equalization process of a prior application. It is a figure which shows an example of program interruption information. It is a figure which shows an example of program execution schedule information. It is a figure which shows a mode that arithmetic processing is continued from the middle of interruption by the equalized system information in the case of operation / standby switching. It is a figure for demonstrating the problem which arises when a fixed period program differs in the process of FIG.

Explanation of symbols

1 CPU module (working system)
2 CPU module (standby system)
3 Equalization bus 4 System bus 11 Program RAM
12 Data RAM
13 Equalization bus controller 14 Receive buffer RAM
15 Control unit 21 Program RAM
22 Data RAM
23 Equalization bus controller 24 Receive buffer RAM
25 Control unit

Claims (7)

It has active and standby controllers, and the active controllers execute multiple fixed-cycle programs each with a priority level, and the priority level is higher than this fixed-cycle program during execution of any fixed-cycle program When the start cycle of the fixed cycle program comes, the fixed cycle program being executed is interrupted, the fixed cycle program having the higher priority level is executed, and then the interrupted fixed cycle program is executed from the point of interruption. In the controller system
The active system controller and the standby system controller are respectively
A multi-equalization mode for performing equalization processing of control data each time each fixed-cycle program is executed in the operating system controller and equalizing system information including a program counter value at that time, and the operating system When the execution of the periodic program with a low priority level is completed in the controller, the control data of the periodic program and the control data of all the periodic programs executed by interrupting the periodic program are equalized. Equalization processing is performed in any one of the single equalization modes, and the equalization processing is performed in the multi-equalization mode in normal times. Means,
A collation means for reading out the fixed cycle program of the other controller from each other and checking whether or not it matches the fixed cycle program of the own controller;
An equalization mode switching means for switching the mode in the equalization processing means to the single equalization mode when the matching means determines that there is a mismatch;
A duplex controller system characterized by comprising:   2. The duplex controller system according to claim 1, wherein the collating process by the collating unit is executed at the time of system initialization.   The verification process by the verification unit is executed when the standby controller is activated while the active controller is in operation, and is executed along with the activation in the standby controller, and from the activated standby controller in the active controller 2. The duplex controller system according to claim 1, wherein the controller is executed in response to a check request issued.   The collating process by the collating means is executed in accordance with the program change in the one controller when the fixed cycle program of one controller is changed while both the active / standby controllers are in operation. 2. The duplex controller system according to claim 1, wherein the other controller is executed in response to a check request issued from the one controller.   5. The equalization process in the single equalization mode is executed during execution of the collation process by the collation unit regardless of whether the periodic programs match or not. Duplex controller system. It has active and standby controllers, and the active controllers execute multiple fixed-cycle programs each with a priority level, and the priority level is higher than this fixed-cycle program during execution of any fixed-cycle program When the start cycle of the fixed cycle program comes, the fixed cycle program being executed is interrupted, the fixed cycle program having the higher priority level is executed, and then the interrupted fixed cycle program is executed from the point of interruption. An equalization mode determination method in a generalized controller system,
The operating system controller and the standby system controller perform equalization processing of control data every time each periodic program is executed in the operating system controller, and system information including a program counter value is also obtained at that time. The multi-equalization mode for equalization and when the execution of the fixed period program having the low priority level is completed in the active system controller, the control data of the fixed period program and the fixed period program are interrupted and executed. Perform equalization processing of control data of all fixed-cycle programs, perform equalization processing in any of the single equalization modes that do not perform equalization of the system information, and normally use the multi etc. Having equalization processing means for performing equalization processing in the valueization mode;
At least at the time of initializing one of the active / standby systems or at the time of changing one of the fixed-cycle programs,
Read the fixed cycle program of the other controller from each other, determine whether it matches the fixed cycle program of its own controller,
If it is determined that the discrepancy in the determination, the equalization mode determination method characterized by switching a mode in the equalization processing section to the single equalization mode. It has active and standby controllers, and the active controllers execute multiple fixed-cycle programs each with a priority level, and the priority level is higher than this fixed-cycle program during execution of any fixed-cycle program When the start cycle of the fixed cycle program comes, the fixed cycle program being executed is interrupted, the fixed cycle program having the higher priority level is executed, and then the interrupted fixed cycle program is executed from the point of interruption. In the program that makes the controller system function,
  A multi-equalization mode for equalizing system information including program counter values while performing equalization processing of control data every time each fixed-cycle program of the active system controller is executed, and When the execution of the fixed cycle program having a low priority level is completed, the control data of the fixed cycle program and the control data of all the fixed cycle programs executed by interrupting the fixed cycle program are equalized. Performing equalization processing in any of the single equalization modes that do not perform equalization of system information, and performing equalization processing in the multi-equalization mode in normal times;
  Reading each other's fixed-cycle program of the other controller and checking whether or not it matches the fixed-cycle program of its own controller;
  If it is determined by the collation that there is a mismatch, the step of switching the multi-equalization mode to the single equalization mode;
  A program having

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