JP5034584B2 - Duplex controller system, its active / standby controller - Google Patents

Description

  The present invention relates to a user data equalization method in a duplex controller (programmable controller) capable of equalization at a plurality of fixed-cycle program ends.

  In the programmable controller system, in order to improve reliability, the CPU module (programmable controller main body) may have a standby redundant dual configuration. Such a dual controller system has, for example, two CPU modules as one set, one as an active system and the other as a standby system. The standby CPU module monitors the active CPU module, and the active CPU module If a switching factor such as a failure occurs in the standby CPU module, the standby CPU module is switched to the active system.

FIG. 5 and FIG. 6 show configuration examples of the conventional dual controller system.
Such a duplex controller system is disclosed in, for example, Patent Documents 1 and 2.

FIG. 5 shows a schematic configuration of the entire duplex controller system.
The duplex controller system shown in the figure is composed of an I / O group including a CPU module 101-1, a CPU module 101-2, and a plurality of I / O units 102 for inputting / outputting data to / from each control target device. Yes. Here, a case where the CPU module 101-1 is an active system and the CPU module 101-2 is a standby system will be described as an example.

  The CPU module 101-1 that is an active system executes a program (usually a program that is executed at a fixed period; a fixed period program) stored in the CPU module 101-1 to each I / O unit 102. Control data is output (or a sensor measurement value or the like is read from each I / O unit) to control each control target device.

  On the other hand, the standby CPU module 101-2 monitors the active CPU module 101-1, and if any switching factor such as a failure occurs in the active CPU module 101-1, the active / standby CPU module 101-1 is activated. The switching process is executed, and the CPU module 101-2 becomes an active system, and the process performed by the CPU module 101-1 is taken over.

  The CPU module 101-1, the CPU module 101-2, and each I / O unit 102 are connected by a system bus 103. The active system CPU module 101-1 is connected to each I / O unit 102 via the system bus 103. Output data (control data) is transmitted to the I / O unit 102, and data such as measurement values from a control target device (not shown) connected to the unit 102 is received.

  Also, an equalization bus 104 is provided between the duplicated CPU module 101-1 and CPU module 101-2 so that user data such as control data can be stored when the active / standby system is switched. In order to provide consistency, user data (global variables, local variables, etc.) is transmitted from the active CPU module 101-1 to the standby CPU module 101-2 via the equalization bus 104 to perform equalization processing. It is carried out.

FIG. 6 shows a detailed configuration example of the CPU module 101-1 and the CPU module 101-2 in the duplex controller system shown in FIG.
The CPU modules 101-1 and 101-2 are programmable controller bodies, but only the configuration related to the equalization processing is shown here, and other configurations are omitted.

  In FIG. 6, the CPU module 101-1 includes a program RAM 111, a data RAM 112, an equalization bus control unit 113, a reception buffer RAM 114, a microprocessor 115, and the like.

  The program RAM 111 stores a user program 111a. The user program 111a is, for example, the above periodic program. Furthermore, an application program for realizing equalization processing is also stored.

The data RAM 112 stores a user data area 112a and equalized data transfer information 112b.
In the user data area 112a, as described in Patent Document 2 and the like, local variables corresponding to each fixed cycle program and global variables are stored in a mixed manner.

The equalized data transfer information 112b is information (mapping information in Patent Document 2) indicating the storage position of each local variable and global variable in the user data area 112a.
The equalization bus control unit 113 is a configuration dedicated to data transfer processing mainly for performing equalization via the equalization bus 104, and data to be equalized from the microprocessor 115 (local variables, global variables). Etc.) has a function of storing the equalized data in the standby-side reception buffer RAM 124 in conjunction with the standby-side equalization bus control unit 123. The equalization bus control unit 113 corresponds to “SGM (Sameness data Gather Memory control)” described in Patent Document 2, for example.

  The microprocessor 115 is a central processing unit (CPU chip or the like) that controls the entire CPU module 101-1, and executes, for example, an equalization process every time each periodic program is executed. The equalization process includes an equalization process on the operating side and an equalization process on the standby side. Here, a part of the equalization process on the operation side is executed. That is, the equalized data (local variables and global variables corresponding to the executed fixed-cycle program) is collected from the user data area 112a and passed to the equalized bus control unit 113 together with the program number and the like. As described above, the equalization bus control unit 113 transfers the equalized data to the CPU module 101-2 and stores it.

  The standby CPU module 101-2 includes a program RAM 121, a data RAM 122, an equalization bus control unit 123, a reception buffer RAM 124, a microprocessor 125, and the like. This configuration itself is the same as that of the active CPU module 101-1. Then, equalization processing on the standby side is performed. That is, after the equalized data is stored in the reception buffer RAM 124 as described above, the microprocessor 125 performs the equalized data stored in the reception buffer RAM 124 according to the equalized data transfer information (mapping information). Are distributed and stored in the user data area 122a of the data RAM 122.

  FIG. 7 shows how the equalized data is transferred and stored in the conventional equalization process. In other words, a data configuration of equalized data transferred via the equalization bus 104, a data storage example of the reception buffer RAM 124, and a data storage example of the user data area 122a are shown.

  First, the equalized data frame shown on the left side of the figure consists of a header part and a data part. The equalized data is transmitted at the completion of each periodic program execution, the number of the executed periodic program is stored in the header part, and the local part related to the executed periodic program is stored in the data part. Stores global variables.

  As shown in the figure, the reception buffer RAM 124 is provided with a storage area for equalized data for each fixed cycle program. The equalized bus control unit 123 is based on the executed fixed cycle program number. The data of the data part is stored in the corresponding storage area.

  Similar to the user data area 112a, global variables and local variables are stored in the user data area 122a, and equalization processing is performed so that the same data as the user data area 112a is stored.

  Here, as described above, the microprocessor 125 stores the equalized data stored in the reception buffer RAM 124 in the corresponding area of the user data area 122a. In this case, each local variable corresponds to the user data area 122a. The global variable is updated only when the periodic program to be executed is executed, whereas the global variable is updated (overwritten) each time since it is shared by all the periodic programs. For this reason, the problem described below with reference to FIGS. 8 and 9 may occur.

  8 and 9 show an example of a schedule when the fixed cycle program is executed. Although there are a plurality of fixed-cycle programs, it is assumed here that there are only two fixed-cycle programs A and B for simplicity.

  In the example shown in FIG. 8, a start request for the fixed cycle program A is generated during the calculation of the fixed cycle program B, the fixed cycle program B is interrupted, and the fixed cycle program A is executed. Then, the equalized data collection / transfer (equalization process on the operating side) is executed / completed at the program end of the periodic program A, and the standby system distributes the equalized data (described above). The standby side equalization process) has been executed and completed. Thereafter, equalization data collection / transfer is executed / completed at the program end of the periodic program B, and the standby system executes / completes distribution of the transferred equalization data.

  The equalized data is stored in the reception buffer RAM 124 on the standby side by the execution / completion of the equalized data collection / transfer, and the equalized data stored in the reception buffer RAM 124 is By the distribution process, the data is stored in the user data area 122a of the data RAM 122. At that time, as shown in FIG. 7, global variables and local variables are respectively stored in predetermined storage areas in the user data area 122a.

  There is no problem if it is interrupted during computation as in the example shown in FIG. 8, but there may be a problem if it is interrupted during equalization processing as in the example shown in FIG. This causes a problem particularly when interrupted after collecting the equalized data and before executing the distribution process.

FIG. 9 shows an example of a scale when the periodic programs A and B are executed when the timing of the periodic program execution request is different from that in FIG.
In this example, during the equalization processing at the end of the fixed cycle program B (after collecting the equalized data and before executing the distribution processing as described above), a start request for the fixed cycle program A is generated and interrupted. The fixed cycle program B is interrupted and the fixed cycle program A is executed. The equalized data collection / transfer is executed / completed at the end of the periodic program A, and the standby system executes / completes the distribution of the transferred equalized data. Thereafter, the equalization processing of the interrupted periodic program B is resumed and executed and completed, and the standby system executes and completes the distribution of the transferred equalized data.

Here, for example, it is assumed that the global variable means the total number of executions of all the periodic programs. Then, it is assumed that the program has been executed 1233 times in total for all fixed-cycle programs before the execution of the processing of FIG. 8 or FIG. In this case, naturally, global variable = 1233 is stored. In this case, since the periodic program is executed twice by the process of FIG. 8 or FIG. 9, naturally, the global variable = 1235 at the end of the process of FIG. 8 or FIG. The value of the global variable stored in the area 122a must also be 1235.

  For example, when the global variable is updated at the end of the arithmetic processing, in the example of FIG. 8, the periodic program B is first calculated and executed, but is interrupted before the global variable is updated, and the periodic program A When the calculation is executed, the global variable = 1233 is read and incremented by +1, so that the global variable = 1234 is changed.

  As a result of the equalization processing, the value of the global variable stored in the standby user data area 122a also becomes 1234. After that, the execution of the fixed-cycle program B, which was interrupted, is changed to global variable = 1235, and the value of the global variable stored in the standby user data area 122a becomes 1235 by the equalization processing. Therefore, no problem occurs in this case.

  Note that this does not cause a problem even if, for example, a global variable is updated at the beginning of the arithmetic processing. That is, in this case, first, the global variable = 1234 is changed by the execution of the periodic program B, and then the global variable = by the execution of the periodic program A without performing the equalization process by the interruption of the calculation. By changing to 1235, the value of the global variable stored in the standby user data area 122a by the equalization processing also becomes 1235. Thereafter, when the processing of the periodic program B is resumed and the equalization processing is executed, the value of the global variable stored in the predetermined storage area is read and transferred to the standby system side. Since global variable = 1235, the value remains 1235 even if the global variable stored in the standby user data area 122a is updated by the equalization process.

  On the other hand, when the processing at the timing shown in FIG. 9 is performed, first, the global variable = 1234 is changed by execution of the periodic program B, and further, equalization data is collected by executing the equalization processing (local Variables, global variable values, etc. are read from a predetermined storage area in the user data area 112a) and transferred to the standby system side. After this equalized data is read and temporarily stored, A problem occurs when the distribution process is interrupted before execution (for example, before the equalized data is transferred to the standby side or when the transfer is completed but the distribution process is not yet executed). . That is, in this case, the fixed cycle program B shifts to the fixed cycle program A in a state where the value “1234” of the global variable has already been collected, and the user of the standby system performs the calculation and equalization processing of the fixed cycle program A. The value of the global variable stored in the data area 122a is updated to “1235”. After that, when the periodic program B is resumed, the value of the global variable '1234' is transferred to the standby system side, so that the value of the global variable stored in the user data area 122a is updated to 1234. Problems arise (old data is stored).

  Therefore, when the operating system / standby system is switched after this, the user program is calculated based on user data that is not up-to-date, which affects the operation of the controller system.

In the above description, for the sake of simplicity, the global variable has been described as meaning the total number of executions. Therefore, if the value of the global variable is compared on the standby side, “1234” <“1235”. , '1235' is a newer value, but global variables do not always have this meaning, so it is not always possible to make a new / old judgment by comparing global variable values. .
JP 2003-296133 A JP 2005-92520 A

  The above-described conventional configuration, that is, the active system CPU module executes a plurality of fixed-cycle programs, performs equalization at each fixed-cycle program end, and interrupts of a higher-level fixed-cycle program occur during execution of user data equalization. In a configuration that may occur, it is necessary to ensure that the equalization data at each fixed-cycle program end is the latest when the active / standby system is switched.

  The problem of the present invention is that, in a duplex controller system that is composed of active and standby CPU modules and executes a plurality of fixed-cycle programs, the data equalization processing of the fixed-cycle programs is particularly global. To provide a duplex controller system that can prevent old values from being stored on the standby side and can guarantee that the equalized data is the latest when the active / standby system is switched. It is.

  The duplex controller system of the present invention is a duplex controller system having an active controller that executes a plurality of fixed-cycle programs and a standby controller, and the active controller includes the fixed-cycle controllers. Each local variable corresponding to a program, first variable storage means for storing global variables shared by all fixed-cycle programs, first serial number storage means for storing serial numbers, and each of the fixed-cycle programs Each time the computation is completed, the serial number stored in the first serial number storage unit is acquired, the serial number is updated, and the updated serial number is stored in the first serial number storage unit And set in an equalized data frame, the local variable corresponding to the executed periodic program and the An operation side equalization processing means for collecting a global variable from the first variable storage means, storing it in the equalization data frame, and transferring the equalization data frame to the standby controller; The standby controller includes a second variable storage means for storing each local variable corresponding to each fixed-cycle program, a global variable shared by all the fixed-cycle programs, and a second number for storing a serial number. By comparing the serial number storage means of the serial number stored in the transferred equalized data frame with the serial number stored in the second serial number storage means. When it is determined as normal, the serial number in the equalized data frame is stored in the second serial number storage means and the equalized data frame is stored. The local and global variables stored in the arm, and a waiting-side equalization processing means for storing in said second variable storage means.

For example, if the standby side equalization processing means determines that there is an abnormality, the serial number stored in the second serial number storage means is not updated, and the equalization data frame is not updated. together with the local variables stored is stored in the second variable storage means, said global variables stored in the equalization data frame, so as not stored in said second variable storage means.

On the active system controller side, local variables and global variables in the first variable storage means are updated by the execution of the operation, and these local variables and global variables are collected in the subsequent equalization process. The serial number is updated, and the updated serial number is set in the equalized data frame. Then, the equalized data frame is transferred to the standby controller. If, for example, the interrupted program is interrupted and another fixed-cycle program is executed before that, the first variable storage is executed by executing the calculation. The local variables and global variables of the means are further updated and the equalization process is performed. The serial number is further updated and then notified to the standby side and stored in the second serial number storage means. Therefore, after the interrupted equalization process is restarted and the equalized data frame is transferred to the standby side, the standby side determines whether the serial number is abnormal (the global variable is old) or not. Therefore, if it is abnormal, the global variable in the second variable storage means is not updated. Thus, the above problem can be solved.

  In addition, for example, the process of updating the serial number stored in the first serial number storage unit is a process of incrementing the serial number, and the standby side equalization processing unit includes the equalization data When the serial number in the frame is larger than the serial number stored in the second serial number storage means, it is determined as normal.

  According to the duplexing controller system of the present invention, in the duplexing controller system that is composed of active and standby CPU modules and executes a plurality of periodic programs, an equal value is obtained during the data equalization processing of the periodic program. It is possible to prevent an old value from being stored on the standby side, particularly for global variables in the equalization data, and to ensure that the equalization data is the latest when the active / standby system is switched.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a configuration example of the CPU module 1 and the CPU module 2 in the duplex controller system of this example. The overall configuration of the duplex controller system of this example may be the same as that shown in FIG.

  The CPU modules 1 and 2 are programmable controller bodies, but only the configuration related to the equalization processing is shown here, and the other configurations are omitted. Here, it is assumed that the CPU module 1 is an active system and the CPU module 2 is a standby system.

  In FIG. 1, a CPU module 1 includes a program RAM 11, a data RAM 12, an equalization bus control unit 13, a reception buffer RAM 14, a microprocessor 15, and a serial NO. A holding memory 16 or the like is included.

  The program RAM 11 stores a user program 11a. The user program 11a is, for example, each of the above periodic programs. In the system of this example, the program RAM 11 further stores an application program for realizing the operation side equalization processing including the processing shown in FIG.

The data RAM 12 has a user data area 12a and stores equalized data transfer information 12b.
In the user data area 12a, as described in Patent Document 2 and the like, local variables corresponding to each fixed cycle program and global variables common to all fixed cycle programs are stored in a mixed manner. Yes.

  The equalized data transfer information 12b corresponds to the mapping information in Patent Document 2, and is information indicating the storage positions of the local variables and global variables in the user data area 12a.

The equalization bus control unit 13 is a configuration dedicated to data transfer processing mainly for performing equalization via the equalization bus 3, and data to be equalized from the microprocessor 15 (equivalent values described later). When the equalized data frame is transferred, the equalized data is stored in the standby-side reception buffer RAM 24 in conjunction with the equalization bus control unit 23 on the standby side. The equalization bus controller 13 corresponds to, for example, the above “SGM (Sameness data Gather Memory control)”.

  The microprocessor 15 is a central processing unit (CPU chip or the like) that controls the entire CPU module 1, and basically uses the user program 11a and the application program stored in the program RAM 11 and basically uses the above-mentioned Patent Document 2. Conventionally performed arithmetic processing and operation side equalization processing, such as the above, are executed, but the processing shown in FIG. 3A is further executed during operation side equalization processing. At that time, serial NO. The serial number stored in the holding memory 16. Is used. Details will be described later.

  The standby CPU module 2 includes a program RAM 21, a data RAM 22, an equalization bus control unit 23, a reception buffer RAM 24, a microprocessor 25, and a serial NO. A holding memory 26 and the like are included. Since this configuration itself is the same as that of the active CPU module 1, it will not be described in particular. However, the microprocessor 25 basically uses the application program stored in the program RAM 21 to The standby side equalization process that has been conventionally performed is executed, and the process shown in FIG. 3B is further executed during the standby side equalization process. At that time, serial NO. The serial number stored in the holding memory 26. Is used. Details will be described later.

  FIG. 2 shows how the equalized data is transferred and stored in the equalization process. In FIG. 2, the description of the components that are substantially the same as those in FIG. 7 is omitted. 2 differs from FIG. 7 in that the transmission serial No. is added to the header portion of the equalized data frame. Is also stored, and this transmission serial number. Is stored in the reception buffer RAM 24 on the standby side together with the equalized data, and the microprocessor 25 transmits the transmission serial number. The equalized data storage processing in the user data area 12a is performed with reference to the above.

  More specifically, first, as shown in FIG. A holding memory 16 is newly provided. Further, as shown in FIG. 2, a transmission serial number field is defined in the header portion of the equalized data frame. Also in the reception buffer RAM 24, the transmission serial No. is stored in the equalized data storage area for each fixed cycle program. Is also defined to be stored.

  First, as shown in FIG. 3A, in the equalized data transmission process of the active system CPU module 1, the microprocessor 15 performs serial NO. The transmission serial number stored in the holding memory 16 is acquired in the work variable TMP1 (step S11), and the value of TMP1 is updated (for example, incremented (for example, +1)) (step S12). (Step S13), and the updated value of TMP1 is set to the serial number. The data is stored in the holding memory 16 (the serial number and the transmission serial number in the holding memory 16 are updated) (step S14). The increment process is not limited to +1, but may be +2, +3, or the like. That is, a predetermined value may be added. Alternatively, it is not limited to increment, but may be decrement such as -1, -2, -3, etc. (However, in this case, the processing in step S23 described later becomes "TMP1 <TMP2?").

Although not shown, the equalization execution fixed cycle program number is also set in the header portion of the equalization data frame, and the equalization data (local variable and global variable corresponding to the executed fixed cycle program, etc.) ) Is extracted from the user data area 12a with reference to the equalized data transfer information 12b (mapping information) and set in the data portion of the equalized data frame. Then, the equalized data frame is transferred to the standby CPU module side. The equalization execution fixed cycle program number is a fixed cycle program number of a fixed cycle program related to the equalization processing.

  In this transfer process, the equalization bus control unit 13 and the equalization bus control unit 23 are linked via the equalization bus 3 as described above, and the equalized data frame is transferred to the standby side reception buffer. The data is stored in the RAM 24. Here, in this example, the reception buffer RAM 24 is provided with a storage area for each fixed-cycle program, and at the time of this transfer processing, as shown in FIG. The equalized data frame is stored (assigned) in the corresponding storage area based on the equalization execution fixed cycle program number. For example, in the case of the equalization processing related to the fixed cycle program A, since the equalized execution fixed cycle program number = A, this equalized data frame is for the fixed cycle program A in the reception buffer RAM 24. Store in the storage area.

  On the other hand, in the standby CPU module 2, when the process of storing the equalized data frame in the reception buffer RAM 24 is completed as described above, the microprocessor 25 first transmits the transmission serial number stored in the reception buffer RAM 24. Is acquired in the work variable TMP1 (step S21), and the serial No. The serial number stored in the holding memory 26. Is acquired in TMP2 which is a work variable (step S22).

  Then, the value of TMP1 is compared with the value of TMP2. If TMP1> TMP2 is satisfied (step S23, YES), it is determined that it is the latest equalized data (that is, determined to be normal). , The value of TMP1 is changed to serial NO. While being set in the holding memory 26 (step S24), an equalized data distribution process (a process for storing the equalized data stored in the reception buffer RAM 24 in the corresponding area in the user data area 22a) is executed (step S24). Step S25). This equalized data distribution processing itself is performed in the same way as in the above-mentioned Patent Document 2, referring to the equalized data transfer information 22b (mapping information), and each of the local variable and the global variable in the corresponding area in the user data area 22a. To store.

  On the other hand, when TMP1> TMP2 is not satisfied (step S23, NO), it is determined that the data is not the latest equalized data (that is, determined to be abnormal), and the serial NO. The update of the holding memory 26 and the equalized data distribution process are not executed (however, although not shown in the figure, only the global variables do not perform the distribution process, and the local variables and the like perform the distribution process). This process is terminated.

FIG. 4 shows the serial No. when the fixed cycle program is executed in the schedule example shown in FIG. And global variable update status.
As described with reference to FIG. 9, on the active CPU module side, first, the periodic program B is executed and global variable = 1234 is obtained by the arithmetic processing, and the equalization processing is started after the arithmetic processing is completed. The serial number stored in the holding memory 16. = “N” is read out, and “n + 1” is set in the equalized data frame by the processing in steps S12 to S14, and the serial number. Store (overwrite) in the memory 16. Also, the equalized data collection is performed as in the conventional case, and the equalized data frame transfer process is performed. Assume that the periodic program A, which is a higher level, is started by an interrupt after at least the global variable = 1234 is collected and held and before the equalization process on the standby side is executed.

In this case, the global variable = 1235 is obtained by the arithmetic processing of the periodic program A, and the equalization processing is started after the arithmetic processing is completed. “N + 1” stored in the holding memory 16 is read, and “n + 2” is set in the equalized data frame by the processing of steps S12 to S14, and the serial NO. Store in the memory 16. Also,
Equivalent data collection (acquisition of global variable = 1235, etc.) is performed as before, the collected data is set in the equalized data frame (retained), transferred to the standby side, and the standby side equivalent By executing and completing the process, the latest global variable value (= 1235) is stored in the global variable storage area in the user data area 22a.

  In other words, in the equalization process on the standby side in this case, that is, the distribution process of the equalized data of the fixed cycle program A, the serial No. stored in the RAM 24 is processed by the process of FIG. = "N + 2" and serial No. As a result of the comparison check with “n” stored in the holding memory 26, the determination in step S23 is YES, so that the processing in steps S24 and S25 is executed. That is, updating the global variable in the user data area 22a (of course, updating the local variable), serial NO. The serial number of the holding memory 26. Is updated. Therefore, the global variable = 1235 of the user data area 22a, the serial No. The serial number of the holding memory 26. = "N + 2".

  Thereafter, the equalization processing of the fixed cycle program B is resumed, and when the equalization processing on the standby side is executed, the transmission serial No. is stored in the equalized data storage area of the fixed cycle program B in the RAM 24. = “N + 1”, global variable = 1234, and the like are stored.

  Therefore, in the equalization processing on the standby side in this case (distribution processing of the equalized data of the fixed cycle program B), the serial No. stored in the RAM 24 is stored. = "N + 1" and serial No. The serial number of the holding memory 26. = “N + 2” is compared and checked, so the determination in step S23 is NO, and the processing in steps S24 and S25 is not executed (however, as described above, the local variable in the user data area 22a is updated). ) Therefore, the global variable = 1235 of the user data area 22a, the serial No. The serial number of the holding memory 26. = “N + 2” remains, and the global variable stored on the standby CPU module side is the latest data (that is, the same value for operation and standby). If this happens, there will be no problem. Serial No. The serial numbers stored in the holding memories 16 and 26. Are both “n + 2” (the same value is obtained during operation and standby).

  In this way, the serial number is stored in each equalization frame transmitted from the active system CPU module, the serial number is checked by the standby CPU module, and only when there is no abnormality (the latest equalization data If the global variable is distributed, it can be guaranteed that the program is executed with the latest user data when the active / standby system is switched.

  As described above, according to the duplex controller system of this example, it is possible to execute a plurality of fixed-cycle programs, and perform equalization of user data when equalization is performed at each fixed-cycle program end. Even when an interrupt of the upper level fixed cycle program occurs, the program can be executed with the latest user data when the active system / standby system is switched.

It is a structural example of a CPU module in the duplex controller system of this example. It is a figure which shows the mode of transfer of an equalization data accompanying an equalization process, and a storage. (A) is an equalization data transmission process, (b) is a flowchart figure which shows an equalization data reception process. It is a figure which shows the update state of a global variable etc. when a fixed cycle program is performed by the example of a schedule shown in FIG. It is a figure which shows schematic structure of the whole duplex controller system. It is a structural example of each CPU module in the duplex controller system shown in FIG. It is a figure which shows the mode of transfer of the equalization data accompanying the conventional equalization process, and a storage. It is a schedule example (the 1) in case a periodic program is performed. It is a schedule example (the 2) in case a periodic program is performed.

Explanation of symbols

1 CPU module (working system)
2 CPU module (standby system)
11 Program RAM
11a User program 12 Data RAM
12a User data area 12b Equalized data transfer information 13 Equalized bus control unit 14 Receive buffer RAM
15 Microprocessor 16 Serial No. Retention memory 21 Program RAM
21a User program 22 Data RAM
22a User data area 22b Equalized data transfer information 23 Equalized bus control unit 24 Receive buffer RAM
25 Microprocessor 26 Serial No. Holding memory

Claims (2)

A duplex controller system having an active controller for executing a plurality of fixed-cycle programs and a standby controller,
The active controller is:
First variable storage means for storing each local variable corresponding to each periodic program and a global variable shared by all the periodic programs;
First serial number storage means for storing a serial number;
Each time the execution of each periodic program is completed, the serial number stored in the first serial number storage means is acquired, the serial number is updated, and the updated serial number is updated to the first serial number. The equalized data frame is stored in the serial number storage means and set in an equalized data frame, and the local variable and the global variable corresponding to the executed periodic program are collected from the first variable storage means. An operation side equalization processing means for storing the frame in a frame and transferring the equalized data frame to the standby controller;
The standby controller is:
Second variable storage means for storing each local variable corresponding to each periodic program and a global variable shared by all the periodic programs;
Second serial number storage means for storing a serial number;
When normal / abnormal is determined by comparing the serial number in the transferred equalized data frame with the serial number stored in the second serial number storage means, and when normal Storing the serial number in the equalized data frame in the second serial number storage means, and the local variable and global variable stored in the equalized data frame as the second serial number. Standby side equalization processing means for storing in the variable storage means,
When the standby side equalization processing means determines that there is an abnormality, the serial number stored in the second serial number storage means is not updated, but is stored in the equalization data frame. The local variable is stored in the second variable storage unit, and the global variable stored in the equalized data frame is not stored in the second variable storage unit,
The process of updating the serial number stored in the first serial number storage means is a process of incrementing the serial number,
The standby-side equalization processing unit determines that the serial number in the equalization data frame is normal when the serial number in the equalization data frame is greater than the serial number stored in the second serial number storage unit. Duplex controller system. A standby controller in a duplex controller system having an active controller for executing a plurality of periodic programs and a standby controller,
Second variable storage means for storing each local variable corresponding to each periodic program and a global variable shared by all the periodic programs;
Second serial number storage means for storing a serial number;
By comparing the serial number in the equalized data frame transferred from the operating system controller with the serial number stored in the second serial number storage means, it is determined whether it is normal or abnormal. If determined, the serial number in the equalized data frame is stored in the second serial number storage means, and the local and global variables stored in the equalized data frame are Standby side equalization processing means for storing in the second variable storage means,
If the standby side equalization processing means determines that there is an abnormality, the serial number stored in the second serial number storage means is not updated, but is stored at least in the equalization data frame. The global variable is not stored in the second variable storage means,
The standby-side equalization processing unit determines that the serial number in the equalization data frame is normal when the serial number in the equalization data frame is greater than the serial number stored in the second serial number storage unit. Standby system controller.