JP4232317B2 - Differential amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a differential amplifier having two input terminals and amplifying a signal applied between the two input terminals.
[0002]
[Prior art]
Conventionally, an example of this type of differential amplifier is shown in FIG.
[0003]
In this differential amplifier, as shown in FIG. 2, the output side of an operational amplifier 1 constituting a differential amplifier circuit is connected to the input side of a first inverter 3 composed of a CMOS inverter or the like via an output line 2. . The output line 2 is connected in parallel to a second inverter 4 made of a CMOS inverter or the like and a switch SW2 made of a MOS transistor connected in series. Further, the power supply voltage VDD is supplied to the output line 2 via a switch SW1 made of a MOS transistor. The output side of the first inverter 3 is connected to the input side of the third inverter 5, the output terminal 6 is connected to the output side of the third inverter 5, and the output OUT is taken out from the output terminal 6.
[0004]
In the conventional differential amplifier having such a configuration, when the operational amplifier 1 is in operation, the switch SW2 is turned on and the second inverter 4 is in an operating state. As a result, when the input signal INP and the input signal INN of the operational amplifier 1 are balanced, the potential of the node A becomes VDD / 2 which is the threshold value of the first inverter by the action of the second inverter 4.
[0005]
Then, when the balance between the input signal INP and the input signal INN of the operational amplifier 1 is lost and the potential of the node A is slightly lower than VDD / 2, the output of the first inverter 3 immediately becomes “H” level. When the potential of the node A slightly rises above VDD / 2, the output of the first inverter 3 immediately becomes “L” level. The output of the first inverter 3 is inverted by the third inverter 5 and the “H” level or “L” level is output from the output terminal 6.
[0006]
On the other hand, when the operation of the operational amplifier 1 is stopped, the switch SW2 is turned off to stop the operation of the second inverter 4, thereby reducing the power consumption of the second inverter 4. At the same time, the switch SW1 is turned on, the power supply voltage VDD is supplied to the input of the first inverter 3, and the output of the third inverter 5 is fixed to “H” to stabilize the operation.
[0007]
[Problems to be solved by the invention]
By the way, the conventional differential amplifier includes the pull-up switch SW1 of the first inverter 3 and the switch SW2 for turning on / off the driving of the second inverter 4 according to the driving of the operational amplifier 1 as described above. . The switches SW1 and SW2 are composed of MOS transistors, and one end thereof is connected to the output line 2 of the operational amplifier 1. Since the switches SW1 and SW2 made of MOS transistors have parasitic capacitances, the parasitic capacitances exist on the output line 2.
[0008]
As a result, due to these parasitic capacitances, the output of the operational amplifier 1 takes time to rise or fall, and when high speed operation is required, the operation of the first inverter 3 becomes unstable or malfunctions. There is a risk of it happening.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to eliminate a parasitic capacitance existing in an output line of an operational amplifier, and to provide a differential amplifier that operates stably and reliably even when the operational amplifier requires high-speed operation.
[0010]
[Means for Solving the Problems]
To solve the above problems and to achieve the object of the present invention was constructed as follows.
[0011]
In the present invention, a differential amplifier circuit that performs differential amplification of an input signal, a first inverter that inverts an output of the differential amplifier circuit, and an input and an output are connected to an output line of the differential amplifier circuit. painting Bei a second inverter, at least the second inverter constituted by clocked inverters, the potential of the output of said differential amplifier circuit when said input signal during operation of the differential amplifier is balanced The second inverter is configured to have a threshold value of the first inverter .
[0012]
The present invention also provides the differential amplifier, is characterized in that so as to constitute the first inverter clocked inverter.
[0013]
Furthermore, the present invention is, in the differential amplifier, said third inverter connected to the output side of the first inverter, when the output is high impedance of the first inverter, a fixed input side of said third inverter to a predetermined voltage It is characterized by doing so.
[0014]
Thus, according to the present invention, at least the second inverter is configured by a clocked inverter including a switching element, and preferably, the first inverter and the second inverter are configured by a clocked inverter including a switching element. .
[0015]
For this reason, the switch for turning on / off the drive of the first inverter or the second inverter can be excluded from the output line of the differential amplifier circuit, and the parasitic capacitance which has been a problem in the past can be excluded from the output line. As a result, even when the differential amplifier circuit requires high speed operation, the first inverter can operate stably and reliably.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0017]
The configuration of the embodiment of the differential amplifier of the present invention will be described with reference to the circuit diagram of FIG.
[0018]
As shown in FIG. 1, the differential amplifier according to this embodiment includes an operational amplifier 1 that performs differential amplification of input signals INP and INP, and a first clocked inverter that is a first inverter that inverts the output of the operational amplifier 1. 11, a second clocked inverter 12 that is a second inverter that can be connected to and separated from the output line 2 of the operational amplifier 1 in parallel, and a third inverter 5 that inverts the output of the first clocked inverter 11, Is provided at least.
[0019]
That is, the differential amplifier according to this embodiment replaces the first inverter 3 and the switch SW1 shown in FIG. 2 with a first clocked inverter 11 including a switch element as shown in FIG. The second inverter 4 and the switch SW2 are replaced with a second clocked inverter 12 including a switch element as shown in FIG. Note that the first clocked inverter 11 and the second clocked inverter 12 have the same size.
[0020]
More specifically, as shown in FIG. 1, the first clocked inverter 11 includes a CMOS inverter 13 including a PMOS transistor Q1 and an NMOS transistor Q2, and the input side of the CMOS inverter 13 is the output line 2 of the operational amplifier 1. The output side is connected to the input side of the inverter 5. Further, a PMOS transistor Q3 and an NMOS transistor Q4 are connected in series as switching elements to both ends of the CMOS inverter 13, respectively.
[0021]
In the PMOS transistor Q3, the power supply voltage VDD is supplied to the source, and the disable signal S1 is supplied to the gate. The NMOS transistor Q4 is configured such that the source is grounded and the enable signal S2 is supplied to the gate. The logic of the disable signal S1 and the enable signal S2 is reversed such that when one is at “H” level, the other is “L”.
[0022]
As shown in FIG. 1, the second clocked inverter 12 includes a CMOS inverter 14 composed of a PMOS transistor Q5 and an NMOS transistor Q6. The input side and the output side of the CMOS inverter 14 are connected to the output line 2 of the operational amplifier 1. It is connected. Further, a PMOS transistor Q7 and an NMOS transistor Q8 are connected in series as switching elements to both ends of the CMOS inverter 14, respectively.
[0023]
In the PMOS transistor Q7, the power supply voltage VDD is supplied to the source, and the disable signal S1 is supplied to the gate. The NMOS transistor Q8 has a source grounded and a gate to which an enable signal S2 is supplied.
[0024]
The third inverter 5 can supply the power supply voltage VDD via the PMOS transistor Q9 whose input side is a switch element. When the first clocked inverter 11 is in a high impedance state, the input side of the third inverter 5 is fixed to the power supply voltage VDD.
[0025]
Next, the operation of the differential amplifier according to the embodiment having such a configuration will be described.
[0026]
When the operational amplifier 1 starts to operate, the disable signal S1 becomes “L” level and the enable signal S2 becomes “H” level. As a result, in the first clocked inverter 11, the MOS transistors Q3 and Q4 are simultaneously turned on, and the CMOS inverter 13 is in an operating state. In the second clocked inverter 12, the MOS transistors Q7 and Q8 are simultaneously turned on, and the CMOS inverter 14 is in an operating state. At this time, the MOS transistor Q9 is off.
[0027]
Thereby, when the input signal INP and the input signal INN of the operational amplifier 1 are balanced, the potential of the node A becomes VDD / 2 which is the threshold value of the CMOS inverter 13 by the action of the CMOS inverter 14.
[0028]
When the balance between the input signal INP and the input signal INN of the operational amplifier 1 is lost and the potential of the node A is slightly lower than VDD / 2, the output of the CMOS inverter 13 immediately becomes “H” level. When the potential of A rises slightly higher than VDD / 2, the output of the CMOS inverter 13 immediately becomes “L” level. The output of the CMOS inverter 13 is inverted by the third inverter 5 and the “H” level or “L” level is output from the output terminal 6.
[0029]
On the other hand, when the operation of the operational amplifier 1 is stopped, the disable signal S1 becomes “H” level and the enable signal S2 becomes “L” level. As a result, in the first clocked inverter 11, the MOS transistors Q3 and Q4 are simultaneously turned off, and the MOS inverter 13 is disconnected from the power source. In the second clocked inverter 12, the MOS transistors Q7 and Q8 are simultaneously turned off, and the CMOS inverter 14 is disconnected from the power source.
[0030]
At this time, the MOS transistor Q9 is turned on, and the input side of the third inverter 5 is fixed to the power supply voltage VDD.
[0031]
As described above, in the differential amplifier according to this embodiment, as shown in FIG. 1, the inverter that inverts the output of the operational amplifier 1 includes the clocked inverter 11 including the switch element, and the output line of the operational amplifier 1. An inverter that can be connected to and separated in parallel with respect to 2 is constituted by a clocked inverter 12 including a switch element.
[0032]
For this reason, the switch for turning on and off the clocked inverters 11 and 12 can be eliminated from the output line 2 of the operational amplifier 1, and the parasitic capacitance due to the switches SW1 and SW2 can be eliminated from the output line 2 as in the prior art. Even when high speed operation is required, the clocked inverter 11 can operate stably and reliably.
[0033]
【The invention's effect】
As described above, according to the present invention, at least the second inverter is constituted by a clocked inverter including a switching element, and preferably, the first inverter and the second inverter are constituted by clocked inverters. The switch for turning on / off the drive of the first inverter or the second inverter can be eliminated from the output line of the differential amplifier circuit, and the parasitic capacitance which has been a problem in the past can be eliminated from the output line. For this reason, even when the differential amplifier circuit requires high-speed operation, the first inverter can operate stably and reliably.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of an embodiment of a differential amplifier of the present invention.
FIG. 2 is a circuit diagram of a conventional differential amplifier.
[Explanation of symbols]
SW1, SW2 switches Q1 to Q9 MOS transistor 1 operational amplifier (differential amplifier circuit)
2 output line 3 first inverter 4 second inverter 5 third inverter 11 first clocked inverter 12 second clocked inverter 13, 14 CMOS inverter

Claims (3)

A differential amplifier circuit for performing differential amplification of the input signal;
A first inverter for inverting the output of the differential amplifier circuit;
A second inverter having an input and an output connected to the output of the differential amplifier circuit,
At least the second inverter is constituted by a clocked inverter;
Configuring the second inverter so that the potential of the output of the differential amplifier circuit becomes the threshold value of the first inverter when the input signal is balanced during operation of the differential amplifier ;
The differential amplifier, wherein the clocked inverter of the first inverter and the second inverter are activated simultaneously .   The differential amplifier according to claim 1, wherein the first inverter is a clocked inverter.   The third inverter is connected to the output side of the first inverter, and when the output of the first inverter is high impedance, the input side of the third inverter is fixed to a predetermined voltage. Differential amplifier.

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