JP4211608B2 - Information transmission / reception system and information processing system - Google Patents

Description

  The present invention relates to an information transmission / reception system for transmitting / receiving information between at least two transmission / reception apparatuses and an information processing system for processing collected information.

  Regarding the understanding of the operating status of equipment (equipment) in the factory, it was common for equipment managers to inspect the equipment several times a day. Recently, however, due to labor shortages and labor cost reduction, instead of collecting information by humans, a sensor is attached to the equipment, and the operation information of the equipment collected by the sensor is sent from the terminal device installed near the equipment to the central monitoring equipment side. Has been taken. There are the following patent documents showing such an apparatus.

JP 2001-287645 A

  In the above prior art, when power cannot be supplied from the outside to the terminal device on the transmission side, the wireless system is driven by a battery. Since the supply voltage of a battery drops due to exhaustion, a general battery-driven power supply circuit uses a power supply (step-down power supply) circuit that steps down the battery voltage and supplies a constant voltage.

  The step-down power supply circuit wastes power by using the difference between the input voltage and the output voltage as heat during step-down. Since the heat generation (power consumption) increases as the voltage difference between the input and output increases, it is necessary to provide heat dissipation means, the number of batteries connected in series and parallel increases, and the apparatus becomes large.

  In addition, if a computing device is installed in a terminal device to perform various types of information processing such as organizing collected information, simplifying transmission information, and data compression, the power consumption becomes large and the battery life is increased. Becomes shorter.

  A wireless terminal with a large amount of power consumption consumes battery quickly and does not function as an information collection device. Therefore, battery replacement work frequently occurs, and manpower is required instead.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a small information transmission / reception system and an information processing system that have low power consumption and do not require manpower even with battery operation and have high information processing capability.

In order to achieve the above object, the present invention is characterized in that, in an information transmission / reception system that wirelessly transmits and receives information between at least two transmission / reception apparatuses including the terminal apparatus, the terminal apparatus drives the terminal apparatus. A battery, at least two power supply circuits for boosting the voltage of the battery to a desired voltage, a first oscillator having a low oscillation frequency, and a timer incorporating either ROM or RAM storage means; A second oscillator having a higher oscillation frequency than the oscillation frequency of the first oscillator and a CPU having a built-in RAM, and the timer is configured to process information in the CPU based on an operation clock of the first oscillator. In response, an interrupt signal can be supplied to the CPU, and the storage means built in the timer switches the operation clock generated by the second oscillator and supplies power. The CPU stores a state table describing the switching time of connection with the contents of switching, and the CPU stores the state table transmitted from the timer in a RAM of the CPU, and information on the state table stored in the RAM And the command from the timer, the CPU operates when the interrupt signal is supplied from the timer. After that, the CPU operates as a mode for supplying power to the sensor connected to the terminal device. The voltage applied to the CPU is set to a low voltage, the operation clock based on the first oscillator is received from the timer, and then the measurement clock is operated with the operation clock based on the second oscillator that the self has. Operation time based on the second transmitter that the self has as the operation mode when the time to complete the operation has elapsed Further reducing the applied voltage higher the processing time in voltage with increase is to make it subsequently proceeds the operation clock with a CPU voltage and low voltage to the low-speed mode received from the timer.

  It has been found that the arithmetic means does not execute high-speed information processing only by increasing the frequency of the supplied clock, but performs high-speed information processing by increasing the clock frequency and simultaneously increasing the applied voltage.

  Power consumption is high in high-speed processing, but information processing is quickly terminated due to high speed. Since there is information processing that does not require high-speed processing, the voltage and frequency supplied to the calculation means are switched by the timer according to the contents of the calculation.

  This switching can reduce the power consumption in the computing means and extend the battery life, so that not only the battery replacement is not manual, but also high information processing ability can be obtained.

  Since there is no power supply circuit that lowers the battery voltage, there is no wasteful power consumption, and even if you have a power supply circuit that boosts voltage, there is no need for heat dissipation means, and there is no need to have many batteries in series and parallel. Is much smaller.

  Hereinafter, an embodiment of the present invention shown in FIGS. 1 to 4 will be described.

  FIG. 1 shows a configuration of an information transmission / reception system for factory equipment according to an embodiment of the present invention.

  10 is a central monitoring device that performs wireless transmission / reception of information to / from the terminal device 20 via the wireless device 11 and monitors the operating status of facility in the factory (not shown) to which the terminal device 20 is attached based on information obtained from the terminal device 20. It is. The central monitoring device 10 and the terminal device 20 correspond to two transmission / reception devices that transmit and receive information wirelessly.

  In FIG. 1, only one terminal device 20 is shown, but a terminal device similar to the terminal device 20 is attached to each facility installed in the factory, and the central monitoring device 10 is connected to each terminal device as described later. Information can be sent and received and monitored.

  The terminal device 20 temporarily stores a central processing unit (CPU) 21 as a computing means for performing information processing, a ROM for storing an operation schedule (soft flow) of the terminal device 20 and information used for the operation schedule. Timer 22 with built-in RAM, oscillation means (oscillator), etc., battery 23 having a voltage as a power source of about 3.6V at the beginning drops to about 1.8V at the end, boosts the voltage of battery 23 If necessary, the power supply circuits 23a to 23c for stepping down and supplying a desired voltage, a transmission circuit (transmission unit) 24, a reception circuit (reception unit) 25, a switch box 26, an external memory 27, and a machine number setting unit 28 are provided. The A sensor 29a and the B sensor 29b are connected as various sensors that are attached to a facility (not shown) and detect the operation status.

  Examples of the power supply circuits 23a to 23c include a high voltage buck-boost regulator (model: LT3433) and a switching regulator (Technical Journal: Design Wave Magazine, 2002. October issued, pp 96-97) sold by Linear Technology Corporation. )and so on.

  In addition to the A sensor 29a and the B sensor 29b, a number of various sensors are attached to the equipment and the operating state of the equipment is measured (detected), but only two sensors are shown for simplicity. Hereinafter, the sensor 29 may be collectively referred to.

  As the external memory 27, a rewritable memory such as a flash memory is used so that recording is not lost even when there is no power supply.

  The machine number setting unit 28 shows only one machine in FIG. 1, but when a large number of terminal apparatuses 20 communicate with the central monitoring apparatus 10, which terminal apparatus 20 is transmitting information is added to the transmission information. The machine number is read on the central monitoring device 10 side, and the machine number (machine number) is set individually so that each terminal device 20 can be distinguished and specified. However, the machine number setting unit 28 may be stored in the memory of the CPU 21 or the external memory 27 as stored data.

  The battery 23 may be a primary battery or a secondary battery, but may be a solar battery or a fuel cell. Furthermore, in a facility with a large calorific value among facilities (not shown) to which the sensor 29 is attached, a storage device in which thermoelectric conversion means such as a thermocouple or a thermopile is installed in the facility and electric power obtained therefrom is stored may be used. A solar cell, a fuel cell, or thermoelectric conversion means may be used. In that case, a rectifier such as a diode and a capacitor may be provided to stabilize power.

  The battery 23 is connected to the timer 22 and the power supply circuits 23a to 23c via the switch box 26 and is indicated by a solid line, which indicates that the battery 23 is always connected.

  The power supply circuit 23a supplies a constant voltage of 3V, the power supply circuit 23b supplies a constant voltage of 5V, and the power supply circuit 23c supplies a constant voltage of 9V. Therefore, the power supply circuit 23a boosts or lowers the voltage according to the voltage of the battery 23, but the power supply circuit 23b and the power supply circuit 23c perform boosting.

  The power supply circuits 23a to 23c and the switch box 26 are connected by solid arrows. This indicates that an output command signal is output from the switch box 26, and the power supply circuits 23a to 23c are connected to the CPU 21 and the transmission circuit by this signal. 24, the receiving circuit 25, the external memory 27, and the sensor 29 are appropriately supplied with electric power via the switch box 26, which is indicated by a dotted line. That is, the switch box 26 connects the power supply circuits 23a to 23c to the CPU 21, the transmission circuit 24, the reception circuit 25, the external memory 27, and the sensor 29 when power is supplied. The connection with the circuits 23a to 23c is cut off.

  The switching of the switch box 26 for the appropriate power supply is performed based on a command issued from the timer 22 and the CPU 21 in accordance with a schedule set in a ROM or RAM built in the timer 22. That this command is issued is indicated by a solid line arrow from the CPU 21 and the timer 22 to the switch box 26.

  Since the voltage supplied to the power supplied to the CPU 21 is switched from time to time, the switching of the switch box 26 and its schedule, that is, the commands issued from the timer 22 and the CPU 21 will be described later.

The solid line arrows connecting the CPU 21 and the timer 22 indicate that they communicate with each other.
A one-dot chain line connecting the CPU 21 and the timer 22 indicates that an interrupt signal for starting the CPU 21 is output from the timer 22. An arrow indicating the CPU 21 and the timer 22 by a one-dot chain line indicates that the operation clock is supplied from the timer 22 to the CPU 21.

  The timer 22 has a function of transmitting the current time to the CPU 21 by communication and a function that can be changed by the CPU 21.

  The timer 22 has a built-in oscillator, and has a function of multiplying and dividing the oscillation frequency and supplying it to the CPU 21 as an operation clock.

  The timer 22 has a function of changing the supply frequency of the operation clock by changing the multiplication rate and the frequency division ratio of the oscillation frequency of the built-in oscillator through communication with the CPU 21.

  Further, the timer 22 has a function of generating an interrupt signal for starting the CPU 21 at a set time interval based on the oscillation frequency of the oscillator built in the timer 22 and outputting the interrupt signal to the CPU 21.

  The activation time interval of the CPU 21 due to this interruption can be changed by communication between the CPU 21 and the timer 22.

  The CPU 21 also has a built-in oscillator, and has a function of generating an operation clock by multiplying or dividing the oscillation frequency and switching the operation frequency. As will be described later, the CPU 21 has a function of switching to the operation clock supplied from the timer 22 and operating.

  FIG. 2 shows an operation schedule (soft flow) of the terminal device 20 stored in the ROM of the timer 22. The time distribution of each step in the operation schedule (soft flow) is as shown in FIG. 3, and how each part of the terminal device 20 operates and in what state in each time zone in the operation schedule (soft flow). This is shown in FIG. The following description of the operation schedule (soft flow) proceeds along the steps shown in FIG. 2, but in FIG. 4, each step of FIG. 2 is represented as a mode.

  The time and command for executing the situation of FIGS. 3 and 4 are stored in the RAM of the timer 22 and can be changed according to the situation.

  The central monitoring device 10 starts operating prior to the start of operation of each terminal device 20, inputs a machine number assigned to each terminal device 20, and receives transmission from each terminal device 20. From the device number listed in the transmission information, the terminal device 20 recognizes which terminal device 20 has transmitted, and returns information corresponding to each terminal device 20.

  An example of the reply information is time information, communication time change information, and the like. Although not shown in FIG. 1, a sensor 29 attached to the terminal device 20 is attached to the terminal device 20 provided with an alarm based on the monitoring result based on the information obtained from the wireless communication. Alarm information etc. notifying that the equipment is in a dangerous state or operating abnormally are also returned.

The startup step (mode) 100 shown in FIG. 2 is a communication immediately started by the timer 22 when the battery 23 is connected to the terminal device 20 and the timer 22 and the battery 23 are always connected via the switch box 26. Move to recording step (hereinafter abbreviated as S) 101.
The timer 22 supplies a voltage of 5 V to the transmission circuit 24 and the reception circuit 25 via the switch box 26 in S101 at the start of operation, and performs wireless communication with the power central monitoring device 10 to confirm and communicate the time. The time is confirmed and the information obtained thereby is stored in the built-in RAM, and the operation schedule (soft flow) in FIG. 2 and the state table information in FIG. 4 are transmitted to the built-in RAM of the CPU 21. Is activated when the information matches the command from the timer 22. When S101 ends, the process proceeds to S102 and pauses. The following description of the operation schedule (soft flow) proceeds along the steps shown in FIG. 2, but in FIG. 4, each step of FIG. 2 is represented as a mode.

As shown in FIG. 4, the timer 202 is operating even in this pause mode, and the time is confirmed by the operation clock, but the output of the operation clock is stopped, and all other parts are in the stopped state. In addition, although the battery voltage is directly applied to the CPU 21 from the battery 23 and the built-in oscillator is operated and only the time is confirmed, there is no communication with the outside, and it is not operated on the surface. An example of current consumption in this mode is about several μA.
When the desired pause time elapses, the timer 22 sends an interrupt signal to the CPU 21 to proceed to the measurement preparation S103 shown in FIG.

  In the measurement preparation (mode) S103, the CPU 21 operates the switch box 26 to supply electric power to the sensor 29, and performs idling so as to stably measure. In this case, 5V is applied to the A sensor 29a and 9V is applied to the B sensor 29b according to the rating of each sensor. In this mode, a voltage of 3V is applied from the power source 23a in order to suppress the power consumption in the CPU 21, and the system operates by receiving an operation clock of 32kHz from the timer 22.

  In FIG. 4, voltage application from the power sources 23 a to 23 c via the switch box 26 is displayed as ON and OFF.

After the sensor 29 rises, the process proceeds to measurement (mode) S104. Here, the CPU 21 operates with an operation clock of 10 MHz, and the respective voltages are continuously applied to the sensors 29 (see FIG. 4). The measurement result of each sensor 29 is stored in the built-in RAM of the CPU 21.
Measurement is performed 500 to 5000 times depending on the contents of the arithmetic processing.

When the time for completing the desired measurement has passed, the process proceeds to result calculation (mode) S105.
In this processing mode, the operation clock generated by the internal oscillator of the CPU 21 is raised to 40 MHz by multiplication, and the applied voltage is raised to 5 V by switching the switch box 26. With this measure, the CPU 21 executes processing of information obtained in the measurement mode S104 at high speed.

  Examples of high-speed calculation processing performed here include effective value calculation of measurement results by real number calculation and repetitive calculation, and frequency analysis by FFT calculation of measurement results.

  Therefore, as shown in FIG. 3, the power consumption increases, but the processing time is shortened, so the overall power consumption is reduced. The result of the information processing is stored in the internal RAM of the CPU 21.

  In addition, power is not supplied from the power supplies 23 a to 23 c to the transmission circuit 24, the reception circuit 25, the external memory 27, and the sensor 29.

  After completion of the result calculation (mode) S105, the process proceeds to battery voltage determination (mode) S106 to check the voltage of the battery 23. If there is a voltage of 3V or more, the process proceeds to a low speed (mode) S107, and the power supply circuit 23a operates the step-down circuit as it is, and waits for the next time to become the communication / recording (mode) S109. If the voltage of the battery 23 is 3V or less, the process proceeds to a low speed (mode) S108 to switch to a booster circuit so that 3V can be output, and waits for a time when the communication / recording (mode) S109 is entered.

Both low speeds (modes) S107 and S108 suppress power consumption until the time of the subsequent communication / recording (mode) S109. The drive voltage of the CPU 21 is as low as 3 V and the operation clock is also as low as 32 kHz.

  When either time of the low speed (mode) S107 or S108 has passed, the process proceeds to the communication / recording (mode) S109, supplying power of 5V to the transmission circuit 24 and the reception circuit 25, and operating both circuits 24 and 25. Thus, the information processing result in the result calculation (mode) S105 can be transmitted to the central monitoring apparatus 10 by wireless communication with the central monitoring apparatus 10. In this mode, the sensor 29 is not supplied with power.

  When the CPU 21 confirms the transmission timing with the reception circuit 25, the measurement result stored in the built-in RAM is transmitted from the transmission circuit 25 to the central monitoring device 10, and the transmission fact, time and contents are recorded in the external memory 27. As for the time, the time obtained by calling the time of the timer 22 by communication is used.

  After the measurement result is transmitted, it becomes a suspension (mode) S110, and the power consumption is suppressed until the next communication period (the (n + 1) th communication period) comes. In the pause (mode) S110, the terminal device 20 is in the same state as the pause (mode) S102.

  When the next communication period (the (n + 1) th communication period) comes, the timer 22 sends an interrupt signal to the CPU 21 and returns to the communication / recording (mode) S101 to confirm the time and whether there is a change in measurement conditions. Thereafter, the operation mode described above is repeated until the voltage drops completely and the battery 23 is removed for replacement.

  Note that the other terminal devices sequentially perform wireless communication similar to that of the central monitoring device 10 until the next communication period (the (n + 1) th communication period) comes after the suspension (mode) S110.

  FIG. 3 is a graph showing changes in power consumption in these operation modes, and the frequency displayed in FIG. 3 is an operation clock used by the CPU 21 for operation.

As described above, not only the operation clock and voltage of the CPU 21 but also the power control including the sensor, the transmission unit, the reception unit, and the external memory, as shown in FIG. Achieve improvements. In particular, the time of the result calculation (mode) S105 in the CPU 21 can be shortened, so that the pause (mode) S110 with extremely low power consumption can be lengthened.
This aspect also helps to prevent the battery 23 from being consumed

  The present invention is not limited to an information transmission / reception system that transmits and receives information between at least two transmission / reception devices, but is an information processing system that is battery-powered and includes arithmetic means. In any system, at least two power supply circuits that boost the voltage of the battery to a desired voltage, an oscillator that oscillates at least two different frequencies, and an oscillator according to the contents of information processing in the arithmetic means Means corresponding to the timer shown in FIG. 1 provided with a state table for switching the frequency supplied to the computing means and switching the application of voltage for power supply to the computing means by switching the connection with each power supply circuit and battery. By providing this, the amount of power consumption can be reduced and the life of the battery can be extended.

It is the schematic which shows the information transmission / reception system for the plant equipment which is one Embodiment of this invention. It is a soft flow figure of the operation schedule in the information transmission / reception system shown in FIG. 2 is a graph showing changes in power consumption in the information transmission / reception system shown in FIG. 1. 2 is a state table showing each operation mode of the information transmission / reception system shown in FIG. 1 and a state inside the terminal in each operation mode.

Explanation of symbols

10. Central monitoring device
20 ... Terminal device
21 ... CPU
22 ... Timer
23 ... Battery
23a to 23c ... power supply circuit
24 ... Transmission circuit
25. Receiving circuit
26 ... Switch box
27 ... External memory
28 ... Machine number setting device
29a ... A sensor
29b ... B sensor

Claims (1)

In an information transmission / reception system that wirelessly transmits and receives information between at least two transmission / reception devices including a terminal device,
The terminal device includes any one of a battery that drives the terminal device, at least two power supply circuits that boost the voltage of the battery to a desired voltage, a first oscillator having a low oscillation frequency, and a ROM and a RAM. A timer incorporating the storage means, a second oscillator having an oscillation frequency higher than the oscillation frequency of the first oscillator, and a CPU incorporating the RAM ,
The timer can supply an interrupt signal to the CPU according to the contents of information processing in the CPU based on the operation clock of the first oscillator , and the storage means built in the timer is generated by the second oscillator And a state table that describes the switching time of the operation clock and the connection time with the battery together with the switching content,
The CPU stores the state table transmitted from the timer in the RAM of the CPU, and operates when the information of the state table stored in the RAM matches the instruction from the timer,
Further, the CPU operates when an interrupt signal is supplied from the timer, and after the operation, a voltage applied to the CPU is set to a low voltage as a mode for supplying power to a sensor connected to the terminal device. Second operation that the self has as an operation mode when an operation clock based on the transmitter is received and then operates with the operation clock based on the second transmitter that the self has as a mode for measurement The operation clock based on the device is further increased and the applied voltage is increased to shorten the processing time, and then the CPU voltage is lowered and the operation clock is advanced to the low-speed mode that receives the operation clock from the timer. Information transmission / reception system.

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