JP4207591B2 - Manufacturing method of semiconductor device having shallow diffusion layer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and in particular, a semiconductor device suitable for an insulated gate (MIS) field effect semiconductor device capable of forming a shallow diffusion layer and obtaining an element with low resistance and small leakage. It relates to the manufacturing method.
[0002]
[Prior art]
When miniaturization of MIS-type FETs progresses and the gate length becomes 0.2 μm or less, the threshold voltage decreases due to the short channel effect, the OFF characteristics deteriorate, etc., and the electrical characteristics deteriorate, so it is necessary to suppress the short channel effect There is. FIGS. 2A to 2C are cross-sectional views showing states at main stages of a general MIS-type FET manufacturing method.
[0003]
In FIG. 2, 21 is a substrate made of Si or the like, 22 is SiO.₂, Etc., 23 is a gate electrode made of poly-Si, 24 is an impurity implantation layer, and 25 is a source / drain diffusion layer. Next, the manufacturing method will be described. First, as shown in FIG. 2A, for example, the substrate 21 is oxidized by thermal oxidation to form a silicon oxide film. For example, polysilicon is deposited on the silicon oxide film by CVD to form a polysilicon film. After the formation, the polysilicon film and the silicon insulating film are selectively etched by etching to form the gate electrode 23 and the gate insulating film 22.
[0004]
Next, as shown in FIG. 2B, impurities are ion-implanted using the gate electrode 23 as a mask to form an impurity-implanted layer 24. As impurities, As, P, Sb for nMOS, and B, In for pMOS are used.
[0005]
Next, as shown in FIG. 2C, annealing (heat treatment) (usually at 800 ° C. to 950 ° C. for 10 minutes to several hours or at 950 ° C. to 1050 ° C. for about 10 seconds) Impurities are activated (impurities are accommodated in crystal lattice positions so as to express predetermined electrical properties), and n-type source / drain diffusion layers 25 are formed for nMOS and p-type for pMOS. At this time, the source / drain diffusion layer 25 becomes deeper than the impurity implantation layer 24 due to impurity diffusion. Then, an interlayer insulating film made of BPSG or the like is formed so as to cover the gate electrode 23, a contact hole is formed in the interlayer insulating film, and then contact can be made with the gate electrode 23 and the source / drain diffusion layer 25 through the contact hole. Thus, a semiconductor device can be obtained by forming a wiring layer made of Al or the like.
[0006]
In the MIS type FET described above, characteristics are deteriorated due to the short channel effect (a phenomenon in which the FET is not sufficiently turned off by the miniaturization) with the miniaturization. In order to suppress this short channel effect, it is very effective to form a shallow pn junction of the source / drain diffusion layer 25.
[0007]
As a method for making the junction of the source / drain diffusion layer 25 shallow, a method has been conventionally used in which the ion implantation energy of impurities is lowered to reduce the depth of penetration of the impurities into the substrate. Further, in order to suppress the diffusion of impurities by annealing for activating the impurities, instead of annealing at a relatively low temperature for a long time (800 ° C. to 950 ° C., 10 minutes to several hours), a high temperature for a short time A method using annealing (1000 ° C., about 10 seconds) is performed. This is intended to suppress diffusion by shortening the annealing time and compensate for the decrease in annealing effect by increasing the temperature.
[0008]
If the implantation energy of ion implantation is lowered in order to reduce the penetration depth of impurities into the substrate, the efficiency of extracting ions as impurities from the ion source is lowered, and the beam current is lowered. This means that the time required for ion implantation becomes longer as the ion implantation energy is lowered, which becomes a problem in mass production. Further, even when high-temperature short-time annealing is used, impurity diffusion cannot be completely suppressed (for example, 1 × 10 6¹⁸cm^-3In addition to the depth of 0.06 μm, it becomes 0.1 μm by performing 1000 ° C. for 10 seconds), and if the time is too short, it is necessary to control the temperature of annealing with high accuracy. Therefore, there is a problem that the annealing apparatus is also expensive.
[0009]
B is most widely used as an impurity in the pMOS source / drain diffusion layer. This is because B has a higher activation rate than In and can reduce the resistance value of the source / drain diffusion layer. However, since B has a low mass, it easily penetrates deep into the substrate by ion implantation. Furthermore, B is easy to thermally diffuse (the diffusion coefficient at 1000 ° C. is 2 × 10^-14 cm² / S, As is 12 × 10^-15 cm² / S) property. For this reason, it is particularly difficult for the pMOS to make the pn junction of the source / drain diffusion layer shallow.
[0010]
On the other hand, as a method of reducing the depth of the junction formed on the Si substrate, an amorphous layer is formed on the semiconductor surface by implanting inert ions such as Si and Ge that do not affect the electrical characteristics of the semiconductor. After that, it is known that a shallow junction can be formed by ion implantation of impurity ions (so-called preamorphous method). It is known that ion implantation into such an amorphized region suppresses channeling and enables shallow junctions to be formed. For example, in JP-A-7-321313, a gate oxide film, polycrystalline silicon, and a silicon oxide film are stacked on a single crystal silicon substrate, and a polycrystalline silicon gate electrode and a silicon oxide film are patterned and patterned. Si ions, Ge ions, etc. are ion-implanted using the formed silicon oxide film as a mask to form a predetermined thickness on both sides of the region where the gate electrode is formed and below the gate oxide film in the single crystal silicon substrate. Then, the spacer is formed on the side surface of the gate electrode, and then impurity ions are implanted using the silicon oxide film and the spacer as a mask to form a diffusion layer deeper than the amorphous portion. In order to repair the damaged part due to ion implantation, heat at a low temperature of several hundred degrees Celsius and recover the single crystal by solid layer growth. Of RTA (Rapid Thermal Annealing) method of performing an activation treatment is disclosed by. In this publication, when the single crystal is recovered by solid layer growth, the ion-implanted impurities diffuse into the tail portion of the amorphous portion and the silicon single crystal substrate. Since the process proceeds faster than the diffusion into the silicon, the heat treatment is stopped when the diffusion into the tail portion is completed, and the impurity diffusion into the single crystal silicon can be prevented from deepening.
[0011]
[Problems to be solved by the invention]
When ion implantation is performed, atoms constituting the crystal of the semiconductor layer (here, silicon) are repelled. As a result, silicon atoms (interstitial atoms) deviated from the original crystal lattice position, or silicon atoms originally exist in the semiconductor layer. A place where no atom is present (a hole) is generated where it should be. These are collectively referred to as point defects. This excessive point defect interacts with impurity atoms in the subsequent annealing, thereby causing excessive diffusion (accelerated diffusion) of impurity atoms. In the conventional manufacturing method, after point defects are introduced by ion implantation, annealing is performed as it is. As a result, accelerated diffusion occurs, impurities are diffused, and the diffusion layer becomes deep.
[0012]
The above-mentioned Japanese Patent Application Laid-Open No. 7-321313 does not particularly mention the elimination of such point defects. In low-temperature annealing that causes diffusion of impurities even at a low temperature, the increase due to such point defects is not mentioned. As a result of the rapid diffusion, the junction depth is expected to increase.
[0013]
The object of the present invention has been made in view of the above points, and the object of the present invention is, in particular, a shallow junction capable of suppressing the short channel effect with a fine MISFET having a gate length of 0.2 μm or less. The present invention provides a novel method for manufacturing a semiconductor device that realizes (less than 600 mm) while suppressing an increase in resistance and leakage current.
[0014]
[SectionMeans for solving the problem]
  In order to achieve the above-described object, the present invention basically employs a technical configuration as described below.
[0015]
That is, the first aspect of the method for manufacturing a semiconductor device according to the present invention is:
By implanting ions into the semiconductor layer, the step of disturbing the crystal state of the surface of the semiconductor layer, the step of implanting impurity ions into the semiconductor layer, and the first annealing in a temperature range that does not cause diffusion of the impurities A step of recovering the disorder of the crystal state, and a step of recovering the crystal defects remaining in the first annealing by the second annealing at a higher temperature than the first annealing,
The second aspect is:
Implanting impurity ions into the semiconductor layer and simultaneously disturbing the crystal state of the surface of the semiconductor layer; recovering the disorder of the crystal state by first annealing in a temperature range that does not cause diffusion of the impurity; And a step of recovering crystal defects remaining in the first annealing by the second annealing at a temperature higher than that of the first annealing.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described.
[0017]
The diffusion of impurities implanted into the semiconductor layer by ion implantation is almost completely suppressed when the temperature is lower than a certain value. FIG. 3 shows the result of investigating the difference in diffusion due to the difference in annealing conditions of the B element ion-implanted into the silicon substrate by SIMS (secondary ion mass spectrometry) measurement. As can be seen from FIG. 3, in normal high temperature short time annealing (1000 ° C., 10 seconds), B element diffuses deeper than before annealing, and the depth of the diffusion layer expands to about 0.1 μm. However, in the annealing process at 650 ° C. or lower, the B element hardly diffuses, and the distribution before the annealing process is substantially maintained (junction depth 0.06 μm). Note that although not shown in the figure, after performing ion implantation which is one embodiment of the present invention to disturb the crystalline state, B⁺In the case of ion implantation, even after annealing at 650 ° C. or lower, the distribution of B hardly diffuses as in the case described above, and maintains the same distribution as before the annealing.
[0018]
When there is a silicon layer (or an amorphous layer) whose crystal state is disturbed on the crystallized base silicon layer, the crystal state is disturbed by annealing treatment even at a low temperature (450 ° C. or higher). The crystalline state of the silicon layer recovered. This is because a silicon layer whose crystal state is disturbed is easily recrystallized even at a low temperature by using the base silicon layer as a seed. As a result, the layer in which the crystal state is disturbed is gradually recovered from the lower side and finally disappears.
[0019]
If the effects of point defects can be removed well, the enhanced diffusion can be suppressed and a shallow diffusion layer can be realized.
[0020]
Point defects diffuse at a lower temperature than impurities introduced into the semiconductor layer. Further, in the situation where the region where the crystal state is disturbed is gradually recovering, the point defect is efficiently trapped and disappears when reaching the interface of the region where the crystal state is disturbed.
[0021]
At temperatures below 650 ° C., impurities are usually hardly activated. However, if impurities are introduced into the silicon layer in which the crystals are disturbed, the impurities are also taken into the crystal lattice positions in the process of recrystallization at a low temperature of 450 ° C. or higher and lower than 650 ° C., so that the impurities are efficiently activated. Is done. On the other hand, when annealing at 650 ° C. or higher and lower than 800 ° C. is performed, a phenomenon occurs in which impurities once activated at a low temperature are deactivated again. Above 800 ° C., the degree of activation increases with increasing temperature.
[0022]
The disordered crystal state can be recovered even at a low temperature of less than 650 ° C., in which ideally no diffusion of impurities occurs. However, unrecovered linear or planar crystal defects partially remain. This increases the leakage current of the semiconductor element. In order to surely prevent such a phenomenon, it is desirable to perform annealing at as high a temperature as possible.
[0023]
A method of manufacturing a semiconductor device according to the present invention is to obtain a diffusion layer that is shallow, has little leakage, and has a low resistance by applying the above physical phenomenon. A step of disturbing the crystalline state of the surface, a step of ion-implanting a desired impurity such as boron into the semiconductor layer, a step of annealing in a first temperature range in which recrystallization of silicon occurs but no impurity diffusion occurs, Annealing in a second temperature range for recovering crystal defects to be performed.
[0024]
In the present invention, it suffices to disturb the crystal state of the semiconductor layer by ion implantation into the semiconductor layer, but the crystal state may be disturbed to the amorphous state. Further, ion implantation for disturbing the crystal state and ion implantation for introducing impurities may be combined. The effect of disturbing the crystal state is suppression of impurity diffusion by improving the efficiency of disappearance of point defects and reduction of resistance by improving the impurity activation rate.
[0025]
In the present invention, first annealing is first performed at 450 ° C. to 650 ° C., which is sufficiently lower than usual, and only point defects are selectively eliminated without causing thermal diffusion of impurities. At this time, the point defect disappearance efficiency is increased by the layer in which the crystal formed in advance is disturbed. Subsequently, crystal defects that cannot be sufficiently eliminated at a low temperature are eliminated by the second annealing at a higher temperature. Thereby, a semiconductor element having a small leakage current can be obtained. At the time of the second annealing, point defects generated by the ion implantation are previously removed by the first annealing, so that the accelerated diffusion is suppressed and a shallow junction can be obtained. Further, since the impurities are already almost activated by performing the first annealing after disturbing the crystal state of the semiconductor layer, the second annealing may be the minimum necessary for eliminating the remaining crystal defects. As the second annealing, annealing at less than 800 ° C. deactivates impurities that have already been activated, which increases the resistance of the device and is not desirable. Further, in the case of annealing at 1000 ° C. or more as in the prior art, normal thermal equilibrium diffusion, which is not accelerated diffusion, is increased, resulting in deeper bonding and less profit compared to the conventional method. In order to obtain the effect of the present invention to the maximum, it is desirable that the second annealing is performed at 850 ° C. to 950 ° C. and the time is about 10 seconds.
[0026]
【Example】
In order to clarify the above and other objects, features and advantages of the present invention, specific examples of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a diagram for explaining an example of a semiconductor device manufacturing method according to the present invention. Hereinafter, the case of a pMOS with a gate length of 0.2 μm or less, which has the greatest effect of the present invention, is described as an example.
[0027]
In FIG. 1, 1 is an n-type substrate made of Si or the like, and 2 is SiO.₂3 is a gate electrode made of polysilicon or the like, 4 is a layer whose crystal state is disturbed, 5 is an impurity implantation layer, and 6 is a source / drain diffusion layer. Next, the manufacturing method will be described.
[0028]
First, as shown in FIG. 1A, a substrate 1 is oxidized by thermal oxidation to form a silicon oxide film having a thickness of 30 mm, and polysilicon is deposited on the silicon oxide film by a CVD method to obtain a film thickness. After the 1500 Å polysilicon film is formed, the polysilicon film and the silicon oxide film are selectively etched by dry etching to form the gate electrode 3 and the gate oxide film 2.
[0029]
Next, as shown in FIG. 1B, using the gate electrode 3 as a mask, for example, Ge⁺About 10 to 30 keV, 2 × 10¹⁴cm^-2Under the conditions, ions are implanted into the substrate 1 to disturb the crystal state of the surface. Under the above conditions, the layer 4 having a disordered crystal state of about 200 to 600% is formed on the surface. At this time, many point defects 11 are generated (the size is exaggerated).
[0030]
Next, as shown in FIG. 1C, B, which is an impurity, is used with the gate electrode 3 as a mask.⁺1-5 keV (BF₂ ⁺2 to 10 keV)¹⁴cm^-2The impurity implantation layer 5 having a thickness of about 200 to 1000 mm is formed by implanting the substrate 1 under the conditions described above. Thereby, the impurity implantation layer 5 covers the layer 4 in which the crystal is disturbed. At this time, point defects 11 further occur. Ge⁺This implantation step may be omitted when the crystal is sufficiently disturbed by ion implantation of a desired impurity. For example, an element constituting a semiconductor layer as implanted ions, here BF heavier than Si₂ ⁺This is the case when In, P, As, Sb, or the like is used. In this case, the situation of FIG. 1C is formed directly from the state of FIG. This is because the depth at which crystals are disturbed by impurity ion implantation is usually shallower than the depth at which impurities are distributed.
[0031]
Next, as shown in FIG. 1 (d), a low-temperature annealing treatment at 450 ° C. to 650 ° C. (for example, 550 ° C., 8 hours) is performed to recrystallize the layer 4 whose crystal state is disturbed. At this time, the Ge⁺, B⁺The point defects 11 generated by ion implantation such as are efficiently trapped at the interface of the layer 4 and disappear. The layer 4 also disappears after a certain annealing time. However, residual crystal defects 12 remain. Note that the annealing temperature described above is a temperature in a range where recrystallization of silicon occurs but impurity diffusion does not occur.
[0032]
Next, as shown in FIG. 1 (e), a high-temperature annealing treatment is performed at 800 ° C. or higher and lower than 1000 ° C. (for example, 900 ° C., 10 seconds) to eliminate the residual crystal defects 12. At this time, since point defects are removed in advance, impurity diffusion is suppressed, and a shallow junction is formed.
[0033]
Then, an interlayer insulating film made of BPSG or the like is formed so as to cover the gate electrode 3, a contact hole is formed in the interlayer insulating film, and then contact can be made with the gate electrode 3 and the source / drain diffusion layer 6 through the contact hole. Thus, a semiconductor device can be obtained by forming a wiring layer made of Al or the like.
[0034]
That is, in the above specific example, first, ions are implanted into the substrate 1 to disturb the crystal state of the substrate 1 to form the disordered layer 4, and then impurities are ion implanted to form the impurity implanted layer 5. Next, point defects generated by ion implantation in the process of recovering the crystallinity of the layer 4 whose crystal state is disturbed by the first annealing are eliminated. This suppresses accelerated diffusion in the subsequent second annealing. Next, the crystal defects remaining in the first annealing are eliminated by the second annealing, and a low-leakage diffusion layer is obtained. At this time, an optimum temperature is selected that achieves both the prevention of resistance increase due to impurity inactivation and the crystal recovery effect.
[0035]
FIG. 4 shows the effect of the above specific example. In the pMOSFET, the threshold value shifts in the positive direction as the gate length becomes shorter due to the short channel effect. In the figure, the conventional method (A) is a case where only annealing at 1000 ° C. for 10 seconds is performed, but the short channel effect is large, and the threshold value is greatly shifted at a gate length of about 0.1 μm. On the other hand, when the case where the first annealing (550 ° C., 8 hours) described in this specification is performed and the second annealing is not performed is viewed (B), impurities are not diffused in the first annealing. A shallow junction is formed, and the short channel effect is significantly suppressed as compared with the conventional method (A). However, since crystal defects remain, 10 per 1 μm of the transistor width.^-9A leakage current flows. In the case (C) according to the present invention, the second annealing (900 ° C., 10 seconds) is performed in addition to the first annealing. Since the second annealing causes slight impurity diffusion, the short channel effect is slightly deteriorated as compared with the case (B) in which the second annealing is not performed. However, since the diffusion is suppressed by the effect of the first annealing, the short channel effect is significantly suppressed as compared with the conventional method (A). Furthermore, since the crystal defects are reduced, the leakage current per 1 μm width of the transistor is 10^-11A was reduced by two orders of magnitude compared to the case where the second annealing was not performed (B), and was suppressed to the same level as the conventional method. Also, the parasitic resistance per unit width of the transistor was equivalent to that of the conventional method (350 Ωμm).
[0036]
The present invention has been described based on the case where the present invention is applied to a pMOS. However, the present invention is not limited to these specific examples.
[0037]
In the above example, B is used as the impurity of the source / drain diffusion layer, but other p-type impurities such as In may be used. Ge ions are used as ions for ion implantation to disturb the crystalline state of the substrate surface.⁺Was used, but Si⁺Alternatively, neutral ions that do not affect the electrical characteristics of other semiconductors may be used. Further, when the target conductivity type is the p-type, the reverse conductivity type As⁺And Sb⁺In this case, the p-type source / drain may be formed such that the p-type impurity concentration implanted in the impurity ion implantation step exceeds the n-type impurity concentration. Further, the present invention can also be applied to an nMOS by using a p-type substrate as the n-type substrate and n-type impurity ions such as P, As, and Sb as impurity ions to be implanted. As an ion for ion implantation for disturbing the crystal state in the case of nMOS, the neutral impurity Ge is used.⁺, Si⁺In addition to In⁺An equal p-type impurity may be used. In this case, the n-type source / drain may be formed in the impurity ion implantation step so that the n-type impurity concentration exceeds the p-type impurity concentration.
[0038]
Furthermore, the impurity ions are As⁺As in the case of the above, when the crystalline state of the substrate surface is disturbed by ion implantation of impurity ions with ions that are heavier than Si that is a constituent element of the semiconductor substrate (for example, As⁺, 20 keV, 2 × 10¹⁴cm^-2), The ion implantation for disturbing the crystal state can be combined with the impurity ion implantation, thereby reducing the number of manufacturing steps.
[0039]
Furthermore, although the order of the ion implantation process for disturbing the crystal state and the ion implantation process for impurities can be switched, the effect of preventing channeling (a phenomenon in which ions deeply penetrate into a specific crystal direction) can be obtained. After ion implantation for disturbing the state, impurity ions are desirably implanted.
[0040]
Further, although the impurity implanted layer 5 completely covers the layer 4 in which the crystal is disturbed in FIG. 1C, the impurity implanted layer 5 may be included in the layer 4 in which the crystal is disturbed. However, from the viewpoint of reducing leakage, it is desirable that the impurity-implanted layer 5 is deeper than the layer 4 in which crystals are disturbed. This is because the residual crystal defects 12 are often formed at the boundary of the layer 4, and even if the defects 12 are not partially recovered by the second annealing, they are included in the diffusion layer 6. This is because the increase of is relatively small.
[0041]
In the above example, the gate insulating film is patterned together with the gate electrode, and ion implantation is performed on the exposed semiconductor substrate surface using the gate electrode as a mask. However, the gate insulating film is formed without patterning the gate insulating film. It is also possible to ion-implant via.
[0042]
The atmosphere at the time of annealing is not particularly limited, and the annealing may be performed in an oxidizing atmosphere such as the air or an inert gas atmosphere such as nitrogen gas. As described above, when the first annealing is performed in an oxidizing atmosphere with the substrate surface exposed, an oxide film is formed on the substrate surface. In this case, the formed oxide film causes a second annealing. This also has the effect of suppressing the outward diffusion of impurity ions.
[0043]
Ions are also implanted into the gate electrode during ion implantation. When the gate electrode is polysilicon, crystal regrowth occurs by the first annealing, resulting in polysilicon with large grain boundaries and low resistance. Turn into. In the case of metal, silicidation is performed by Si ion implantation, and low resistance can be expected. If ion implantation into the gate electrode is not desired, an oxide film may be separately formed on the gate electrode and used as a mask.
[0044]
In FIG. 1, the source / drain diffusion layer 6 has been described in the simplest form for the sake of simplicity. However, the method according to the present invention can produce a structure having a more complicated source / drain diffusion layer. It can also be applied to processes. For example, the present invention can also be applied to manufacturing a so-called source / drain extension structure in which the source / drain diffusion layer 6 is shallow in the vicinity of the gate electrode 3 and has a deep structure in other portions.
[0045]
The source / drain / extension structure is a shallow source / drain junction in the vicinity of the gate electrode to suppress the short channel effect, while deepening the source / drain junction in other areas to further reduce resistance. In addition, the structure is intended to facilitate the formation of the wiring by making the metal wiring contact in a deep region of the source / drain junction. In this case, it is important to make the junction shallow especially in the shallow source / drain region, and this can be realized by applying the present invention.
[0046]
As a second embodiment, a method of applying the present invention to a source / drain extension structure will be described with reference to FIG. First, the gate electrode 3 is formed in the same manner as in FIG. 1A (FIG. 5A). Next, in the same manner as in FIG. 1C, the layer 4 in which the crystal is disturbed and the impurity introduction layer 5A are formed using the gate electrode 3 as a mask (FIG. 5B). At this time, the layer 4 and the layer 5A may be formed by separate ion implantation, or may be formed by the same ion implantation. Next, after depositing an insulating film on the entire surface of the substrate, anisotropic etching is performed to form a gate sidewall insulating film 7 on the side surface of the gate electrode 3 (FIG. 5C). Next, using the gate electrode 3 and the gate sidewall insulating film 7 as a mask, an impurity having the same conductivity type as that of the impurity introduction layer 5A is deeply ion-implanted to form the impurity introduction layer 5 composed of a shallow region and a deep region ( FIG. 5 (d)). In the ion implantation for forming this deep region, it is usual to implant a larger amount of impurities at a higher energy and intentionally introduce the impurities deeper than when forming the impurity introduction layer 5A. For example, if the same pMOSFET as in the first embodiment, B⁺2 to 10 keV and 2 to 5 × 10¹⁵cm^-2Inject about. At this time, the layer 4 in which the crystals are disturbed may be enlarged (not shown), but this is not related to the essence of the invention. Finally, the source / drain diffusion layer 6 is formed by performing the first and second annealing described above.
[0047]
The first annealing is optimally performed once in the state of FIG. 5D in which all the ion implantations are completed. However, for example, the effect can be obtained even if it is performed in the state of FIG. 5B. Further, it may be carried out in both the states of FIGS. 5B and 5D.
[0048]
The difference between the second embodiment and the first embodiment is that the impurity introduction layer 5 is formed by two ion implantations in FIGS. 5B and 5D. The effect is the same as in the first embodiment. That is, the point defects formed by the two ion implantations of the shallow source / drain and the deep source / drain are eliminated without causing impurity diffusion by the effect of the first low-temperature annealing and the layer 4 in which the crystal is disturbed. The residual defects are removed by the second high temperature annealing. As a result, impurity diffusion can be suppressed, and particularly shallow source / drain regions can be formed shallow, and all source / drain regions can be formed with low resistance and low leakage.
[0049]
As a third embodiment, another method for applying the present invention to a source / drain extension structure will be described with reference to FIG. First, the gate electrode 3 is formed in the same manner as in FIG. 1A (FIG. 6A). Next, after depositing an insulating film on the entire surface of the substrate, anisotropic etching is performed to form a gate sidewall insulating film 7 on the side surface of the gate electrode 3 (FIG. 6B). The gate sidewall insulating film 7 in this embodiment is preferably made of a material that can be easily removed later by selective etching, such as a silicon nitride film. Next, a deep impurity introduction layer 5B is formed by ion implantation using the gate electrode 3 and the gate sidewall insulating film 7 as a mask (FIG. 6C). Similar to the second embodiment, if pMOSFET, B⁺2 to 10 keV and 2 to 5 × 10¹⁵cm^-2Inject about. At this time, a layer in which crystals are disturbed may be formed inside the impurity introduction layer 5B. Next, a third annealing is performed to activate the impurity introduction layer 5B and convert it into a deep source / drain region 6B. At this time, if there is a layer in which the crystal is disturbed, it is recovered once. The third annealing condition at this time can be determined independently of the optimum condition for a shallow source / drain region to be formed later. For example, the RTA treatment is performed at 1000 ° C. for 10 seconds. Before or after this step, the gate sidewall insulating film 7 is removed by a selective etching method (FIG. 6D). For example, if the gate sidewall insulating film 7 is a silicon nitride film, etching with a hot phosphoric acid solution may be used. Next, in the same manner as in FIG. 1C, a layer 4 in which crystals are disturbed and an impurity introduction layer 5A are formed using the gate electrode 3 as a mask. At this time, the layer 4 and the layer 5A may be formed by separate ion implantation, or may be formed by the same ion implantation. Finally, the source / drain diffusion layer 6 is formed by performing the first and second annealing described above.
[0050]
The difference between the third embodiment and the second embodiment is that the order of forming the deep source / drain regions and the shallow source / drain regions is reversed and the third annealing is added. As an advantage of using such a technique, when the gate electrode 3 is a semiconductor such as polysilicon and it is necessary to introduce impurities into the inside by ion implantation, this ion implantation step is performed for deep source / drain region formation. Therefore, it can be easily used as an ion implantation step. That is, relatively high-temperature annealing (1000 ° C., about 10 seconds or more) is necessary for introducing impurities into the gate electrode 3, but for the shallow source / drain regions, as described above, such a high temperature is required. This annealing is inconvenient. However, according to the third embodiment, before forming the shallow source / drain impurity region 5A, the impurity is introduced into the gate electrode 3 simultaneously with the introduction of the impurity for forming the deep source / drain. By performing the high-temperature third annealing, the impurities introduced into the gate electrode 3 are also activated, and the resistance reduction of the gate electrode 3 is promoted. As described above, since the third annealing is performed before the shallow source / drain regions are formed, it is possible to achieve a high temperature suitable for introducing impurities into the gate electrode, and the introduction of impurities into the gate electrode is facilitated. Further, as another advantage, it is expected that the resistance of the deep source / drain region can be further reduced by setting the third annealing to a sufficiently high temperature as compared with the second embodiment.
[0051]
Also in this embodiment, the effect of the present invention is the same as that of the first embodiment. The point defect formed by shallow source / drain ion implantation is a layer in which the crystal is disturbed by the first low-temperature annealing. The effect of 4 is eliminated without causing impurity diffusion, and residual defects are removed by the second high-temperature annealing. As a result, impurity diffusion can be suppressed to form shallow source / drain regions, and resistance and leakage can be suppressed particularly in shallow source / drain regions.
【The invention's effect】
As described above, according to the present invention, it is possible to form a shallow source / drain diffusion layer without increasing resistance and leakage current, and to suppress the short channel effect.
[0052]
It should be noted that the present invention is not limited to the above-described embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a specific example of a method for manufacturing a semiconductor device according to the present invention.
FIG. 2 is a diagram for explaining a conventional manufacturing method.
FIG. 3 is a diagram illustrating the effect of the present invention.
FIG. 4 is a diagram illustrating the effect of the present invention.
FIG. 5 is a process cross-sectional view illustrating a manufacturing process according to a second embodiment of the present invention.
FIG. 6 is a process cross-sectional view illustrating a manufacturing process according to a third embodiment of the present invention.
[Explanation of symbols]
1 Substrate
2 Gate insulation film
3 Gate electrode
4 Layers with disturbed crystal state
5 Impurity implanted layer
6 Source / drain diffusion layer
7 Gate sidewall insulation film
11 point defect
12 Residual crystal defects

Claims (10)

Forming a gate insulating film and a gate electrode on the semiconductor substrate;
Disturbing the crystal state of the surface of the semiconductor substrate by ion implantation into the semiconductor substrate using the gate electrode as a mask;
Using the gate electrode as a mask, implanting impurity ions into the semiconductor substrate;
Recovering disorder of the crystalline state by first annealing in a temperature range that does not cause diffusion of the impurities;
Forming a gate sidewall insulating film on the gate electrode;
Using the gate electrode and the gate sidewall insulating film as a mask, implanting an impurity having the same conductivity type as the ion-implanted impurity with a higher energy than the ion implantation;
Recovering crystal defects remaining in the first annealing by a second annealing at a higher temperature than the first annealing;
A method for manufacturing a semiconductor device, characterized by sequentially performing steps. Forming a gate insulating film and a gate electrode on the semiconductor substrate;
Disturbing the crystal state of the surface of the semiconductor substrate by ion implantation into the semiconductor substrate using the gate electrode as a mask;
Using the gate electrode as a mask, implanting impurity ions into the semiconductor substrate;
Recovering disorder of the crystalline state by first annealing in a temperature range that does not cause diffusion of the impurities;
Forming a gate sidewall insulating film on the gate electrode;
Using the gate electrode and the gate sidewall insulating film as a mask, implanting an impurity having the same conductivity type as the ion-implanted impurity with a higher dose and higher energy than the ion implantation;
Recovering crystal defects remaining in the first annealing by a second annealing at a higher temperature than the first annealing;
A method for manufacturing a semiconductor device, characterized by sequentially performing steps. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the ions implanted to disturb the crystal state of the surface of the semiconductor substrate are ions that do not affect the electrical characteristics of the semiconductor. The ions implanted to disturb the crystalline state of the surface of the semiconductor substrate are ions that give a conductivity type opposite to the target conductivity type,
3. The method of manufacturing a semiconductor device according to claim 1, wherein ions that give a target conductivity type are implanted at a higher concentration in the impurity ion implantation step than ions that give the opposite conductivity type. Forming a gate insulating film and a gate electrode on the semiconductor substrate;
Ion implantation into the semiconductor substrate using the gate electrode as a mask, and simultaneously disturbing the crystal state of the surface of the semiconductor substrate;
Recovering disorder of the crystalline state by first annealing in a temperature range that does not cause diffusion of the impurities;
Forming a gate sidewall insulating film on the gate electrode;
Using the gate electrode and the gate sidewall insulating film as a mask, implanting an impurity having the same conductivity type as the ion-implanted impurity with a higher energy than the ion implantation;
Recovering crystal defects remaining in the first annealing by a second annealing at a higher temperature than the first annealing;
A method for manufacturing a semiconductor device, characterized by sequentially performing steps. Forming a gate insulating film and a gate electrode on the semiconductor substrate;
Ion implantation into the semiconductor substrate using the gate electrode as a mask, and simultaneously disturbing the crystal state of the surface of the semiconductor substrate;
Recovering disorder of the crystalline state by first annealing in a temperature range that does not cause diffusion of the impurities;
Forming a gate sidewall insulating film on the gate electrode;
Using the gate electrode and the gate sidewall insulating film as a mask, implanting an impurity having the same conductivity type as the ion-implanted impurity with a higher dose and higher energy than the ion implantation;
Recovering crystal defects remaining in the first annealing by a second annealing at a higher temperature than the first annealing;
A method for manufacturing a semiconductor device, characterized by sequentially performing steps. 7. The method of manufacturing a semiconductor device according to claim 5 , wherein the impurity ions to be implanted are ions heavier than an element constituting the semiconductor substrate. The method of manufacturing a semiconductor device according to any one of claims 1 to 7 wherein the first annealing temperature is equal to or less than 450 ° C. or higher 650 ° C.. The method of manufacturing a semiconductor device according to any one of claims 1 to 8 wherein the second annealing temperature is equal to or less than 800 ° C. or higher 1000 ° C.. The method of manufacturing a semiconductor device according to any one of claims 1 to 9 regions impurity is implanted is equal to or deeper than the region where the crystalline state is disturbed.

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