JP2003243652A - Method for manufacturing semiconductor device having shallow diffusion layer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a shallow junction for inhibiting the short channel effect in a MISFET by inhibiting the increase of current leak and resistance. <P>SOLUTION: The semiconductor device is manufactured by a method wherein a layer 4 with its crystal state disturbed by ion implantation is formed on the surface of a semiconductor layer, an impurity implanted layer 5 is formed by implanting impurity ions into the same semiconductor layer, the disturbed crystal state is remedied in a first annealing process of a temperature not to incur dispersion of the impurity for the elimination of crystal defects 11 present in the substrate, and then crystal defects 12 residual after the first annealing process are remedied by a second annealing process of a higher temperature. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an insulated gate (MIS) electric field effect capable of forming a shallow diffusion layer and obtaining an element having low resistance and small leakage. The present invention relates to a semiconductor device manufacturing method suitable for a semiconductor device.

[0002]

2. Description of the Related Art As the miniaturization of MIS-type FET progresses and the gate length becomes 0.2 μm or less, a short channel effect causes a decrease in threshold voltage, deterioration of off characteristics, and the like, and electrical characteristics are deteriorated. It is necessary to suppress the effect. 2A to 2C are cross-sectional views showing a state in a main stage of a method of manufacturing a general MIS type FET.

In FIG. 2, 21 is a substrate made of Si or the like, 22 is a gate insulating film made of SiO ₂ or the like, 23 is a gate electrode made of poly-Si or the like, 24 is an impurity injection layer, 2
Reference numeral 5 is a source / drain diffusion layer. Next, the manufacturing method will be described. First, as shown in FIG. 2A, for example, the substrate 21 is oxidized by thermal oxidation to form a silicon oxide film, and, for example, polysilicon is deposited on the silicon oxide film by a CVD method to form a polysilicon film. After the formation, the polysilicon film and the silicon insulating film are selectively etched by etching to form the gate electrode 23 and the gate insulating film 22.

Next, as shown in FIG. 2B, impurities are ion-implanted using the gate electrode 23 as a mask to form an impurity-implanted layer 24. As an impurity, nMOS has A
B, In are used for s, P, Sb, and pMOS.

Next, as shown in FIG. 2 (c), impurity implantation is performed by annealing (heat treatment) (normally 800 ° C. to 950 ° C. for 10 minutes to several hours, or 950 ° C. to 1050 ° C. for about 10 seconds). The impurities in the layer 24 are activated (so that the impurities are contained in the crystal lattice position and express a predetermined electric property), and the nMOS is n-type and the pMOS is p-type.
A source / drain diffusion layer 25 of the mold is formed. At this time, due to the impurity diffusion, the source / drain diffusion layer 25 becomes deeper than the impurity injection layer 24. Then, an interlayer insulating film made of BPSG or the like is formed so as to cover the gate electrode 23, a contact hole is formed in the interlayer insulating film, and then the gate electrode 23 and the source / drain diffusion layer 25 can be contacted through the contact hole. By forming the wiring layer made of Al or the like as described above, a semiconductor device can be obtained.

In the MIS type FET shown above,
Along with miniaturization, deterioration of characteristics occurs due to a short channel effect (a phenomenon in which the FET is not sufficiently turned off due to miniaturization). To suppress the short channel effect, it is very effective to form the pn junction of the source / drain diffusion layer 25 shallow.

As a method for making the junction of the source / drain diffusion layers 25 shallow, a method has been conventionally used in which the ion implantation energy of impurities is lowered to make the depth of penetration of impurities into the substrate shallow. Further, in order to suppress the diffusion of impurities due to the annealing for activating the impurities, annealing at a relatively low temperature (800 ° C. to 950 ° C.) is performed.
A method using high-temperature short-time annealing (1000 ° C., about 10 seconds) is used instead of (° C., 10 minutes to several hours). This suppresses diffusion by shortening the annealing time,
This is intended to compensate for the decrease in the annealing effect due to the increase in temperature.

When the implantation energy of the ion implantation is lowered in order to make the depth of penetration of impurities into the substrate shallow, the efficiency of extracting the ions serving as impurities from the ion source is lowered and the beam current is lowered. This means that the lower the ion implantation energy, the longer the time required for ion implantation, which is a problem in mass production. Furthermore, even when high-temperature short-time annealing is used, the diffusion of impurities cannot be completely suppressed (for example, the depth at which the concentration becomes 1 × 10 ¹⁸ cm ⁻³ changes from 0.06 μm to 1000 ° C. for 10 seconds). In addition to the above, the annealing temperature is required to be controlled with high accuracy in order to shorten the time too much.

B is most widely used as an impurity in the source / drain diffusion layers of pMOS. This is B is I
This is because the activation rate is higher than that of n and the resistance value of the source / drain diffusion layer can be lowered. However, since B has a light mass, it easily penetrates deep into the substrate by ion implantation. Further, B easily diffuses thermally (diffusion coefficient at 1000 ° C. is 2 × 10 ⁻¹⁴ cm ² / s, As is 12 × 10 4).
^-15 cm ² / s). Therefore, it is particularly difficult in the pMOS to make the pn junction of the source / drain diffusion layer shallow.

On the other hand, as a method for reducing the depth of the junction formed on the Si substrate, inactive ions such as Si and Ge which do not affect the electric characteristics of the semiconductor are implanted so that the semiconductor surface is amorphous. It is known that a shallow junction can be formed by implanting impurity ions after forming the layer (so-called preamorphous method). It is known that the ion implantation into the amorphized region suppresses the channeling and enables the formation of a shallow junction. For example, in Japanese Patent Laid-Open No. 7-321313, a gate oxide film, polycrystalline silicon,
Further, a silicon oxide film is laminated, a gate electrode and a silicon oxide film of polycrystalline silicon are formed by patterning, and Si ions, Ge ions, etc. are ion-implanted using the patterned silicon oxide film as a mask to form a gate electrode. On both sides of the formed region, and the lower part of the gate oxide film in the single crystal silicon substrate is made amorphous to a predetermined thickness, subsequently spacers are formed on the side surfaces of the gate electrode, and then the silicon oxide film and Impurity ions are implanted using the spacer as a mask to form a diffusion layer in a region deeper than the amorphous part, and then heated at a low temperature of several hundreds of degrees Celsius in order to repair the damaged part due to ion implantation, and solid phase growth is performed. After recovering the single crystal, RTA (Rapid Thermal
Annealing) discloses a method of performing activation treatment. In this publication, when the single crystal is recovered by solid phase growth, the ion-implanted impurities diffuse into the tail portion of the amorphous portion and the silicon single crystal substrate. Since it progresses faster than the diffusion into silicon, the heat treatment is stopped at the time when the diffusion into the tail portion is completed, and it is possible to prevent the impurity diffusion into the single crystal silicon from becoming deep.

[0011]

When the ion implantation is carried out, the atoms (here, silicon) that compose the crystal of the semiconductor layer are repelled, and as a result, silicon atoms (lattice) deviated from the original crystal lattice position in the semiconductor layer. Interatoms), or places where no silicon atoms should exist (vacancy) are generated. These are collectively referred to as point defects.
This excessive point defect interacts with the impurity atom in the subsequent annealing, which causes excessive diffusion (enhanced diffusion) of the impurity atom. In the conventional manufacturing method, after point defects are introduced by ion implantation, annealing is performed as it is. As a result, accelerated diffusion occurs, impurities diffuse, and the diffusion layer becomes deep.

The above-mentioned Japanese Patent Application Laid-Open No. 7-321313 does not particularly mention the elimination of such point defects, and such a point is encountered in low temperature annealing at which diffusion of impurities occurs even at low temperatures. It is expected that the junction depth will increase as a result of enhanced diffusion due to defects.

The object of the present invention is made in view of the above-mentioned points. The object of the present invention is to suppress the short channel effect particularly in a fine MISFET having a gate length of 0.2 μm or less. The present invention provides a novel method for manufacturing a semiconductor device, which realizes a shallow junction (600 Å or less) that can be achieved while suppressing an increase in resistance and leakage current.

[0014]

In order to achieve the above-mentioned object, the present invention basically adopts the technical constitution as described below.

That is, the first aspect of the method for manufacturing a semiconductor device according to the present invention is a step of disturbing the crystalline state of the surface of the semiconductor layer by implanting ions into the semiconductor layer, and impurity ions in the semiconductor layer. Ion implantation, restoration of the disorder of the crystalline state by first annealing in a temperature range that does not cause diffusion of impurities, and second annealing at a temperature higher than that of the first annealing. And a step of injecting impurity ions into the semiconductor layer, and at the same time disturbing the crystalline state of the surface of the semiconductor layer. A step of recovering the disorder of the crystalline state by a first annealing in a temperature range that does not cause diffusion of the impurities; and a second annealing at a temperature higher than that of the first annealing. A step of recovering a crystal defect remaining in the first annealing by Neil, is characterized in that it has a.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described.

By the ion implantation, the diffusion of the impurities implanted in the semiconductor layer is almost completely suppressed if the temperature is lower than a certain value. FIG. 3 shows the difference in the diffusion of the B element ion-implanted in the silicon substrate due to the difference in the annealing conditions.
It is the result of examination by IMS (secondary ion mass spectrometry) measurement. As can be seen from FIG. 3, in the normal high temperature short time annealing (1000 ° C., 10 seconds), the B element diffuses deeper than before the annealing treatment, and the depth of the diffusion layer expands to about 0.1 μm. However, the B element hardly diffuses in the annealing process at 650 ° C. or lower, and the distribution before the annealing process is almost maintained (junction depth 0.06 μm).
m). Although not shown in the drawing, after Ge ion implantation, which is one embodiment of the present invention, is performed to disturb the crystalline state, B
^{Even when +} is ion-implanted, the B distribution hardly diffuses even after the annealing treatment at 650 ° C. or lower, and maintains the almost same distribution as before the annealing.

When a silicon layer (or an amorphous layer) in which the crystalline state is disturbed is present on the crystallized base silicon layer, the crystalline state can be obtained by performing an annealing treatment even at a low temperature (450 ° C. or higher). The crystalline state of the disturbed silicon layer is recovered. This is because the silicon layer whose crystal state is disturbed is easily recrystallized even at a low temperature by using the underlying silicon layer as a seed. As a result, the layer in which the crystalline state is disturbed gradually recovers from the lower side and finally disappears.

If the effect of point defects can be removed well, enhanced diffusion can be suppressed and a shallow diffusion layer can be realized.

The point defects diffuse at a lower temperature than the impurities introduced into the semiconductor layer. Further, the point defect is efficiently captured and disappears there when reaching the interface of the region in which the crystalline state is disturbed in a state where the region in which the crystalline state is disturbed is gradually recovering.

At temperatures below 650 ° C., impurities are usually rarely activated. However, if impurities are introduced into the silicon layer in which the crystals are disturbed, the impurities are also taken into the crystal lattice position during the recrystallization process at a low temperature of 450 ° C. or higher and lower than 650 ° C., so that the impurities are efficiently activated. To be done. On the other hand, when annealing at 650 ° C or higher and lower than 800 ° C is applied,
A phenomenon occurs in which impurities once activated at low temperature are again inactivated. At 800 ° C. or higher, the degree of activation increases as the temperature increases.

The disordered crystal state can ideally be recovered even at a low temperature of less than 650 ° C. at which almost no impurity diffusion occurs, but linear or planar crystal defects which are not recovered are partially recovered. Remain, which increases the leakage current of the semiconductor device. In order to surely prevent such a phenomenon, it is desirable to perform annealing at a temperature as high as possible.

The method of manufacturing a semiconductor device according to the present invention is to obtain a diffusion layer having a shallow depth, a small leakage, and a low resistance by applying the above-mentioned physical phenomenon. A step of disturbing the crystalline state of the surface of the semiconductor layer, a step of implanting a desired impurity such as boron into the semiconductor layer, and a step of annealing in a first temperature range in which recrystallization of silicon occurs but diffusion of impurities does not occur. And a step of annealing in a second temperature range for recovering the remaining crystal defects.

In the present invention, it suffices to disturb the crystalline state of the semiconductor layer by implanting ions into the semiconductor layer, but the crystalline state may be disturbed to the amorphous state. Further, the ion implantation for disturbing the crystalline state and the ion implantation for introducing the impurities may be combined. The effect of disturbing the crystalline state is to suppress the diffusion of impurities by improving the vanishing efficiency of point defects and to reduce the resistance by improving the activation rate of impurities.

In the present invention, first, 450 which is sufficiently lower than usual is used.
The first anneal is performed at a temperature of 650 ° C. to 650 ° C. to selectively eliminate only point defects without causing thermal diffusion of impurities. At this time, the extinction efficiency of the point defects is enhanced by the layer in which the crystals formed in advance are disturbed. Subsequently, crystal defects that cannot be sufficiently eliminated at a low temperature are detected at the second temperature of a higher temperature.
Disappear by annealing. This makes it possible to obtain a semiconductor element having a small leak current. At the time of the second annealing, the point defects generated by the ion implantation are removed by the first annealing in advance, so that the accelerated diffusion is suppressed and a shallow junction can be obtained. In addition, since the impurities have already been almost activated by performing the first annealing after disturbing the crystal state of the semiconductor layer, the second annealing may be the minimum necessary to eliminate the remaining crystal defects. As the second annealing, annealing at less than 800 ° C. deactivates the impurities that have already been activated, which increases the resistance of the device, which is not desirable. In addition, in the same annealing at 1000 ° C. or higher as in the conventional case, the normal thermal equilibrium diffusion, which is not the enhanced diffusion, becomes large, so the junction becomes deep,
There are few profits compared with the conventional method. In order to obtain the maximum effect of the present invention, it is desirable that the second annealing is 850 ° C.
It is preferable that the temperature is 950 ° C. to 950 ° C. and the time is about 10 seconds.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS To clarify the above and other objects, features and advantages of the present invention, specific examples of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention. Less than,
P with a gate length of 0.2 μm or less is the most effective
The case of MOS will be described as an example.

In FIG. 1, 1 is an n-type substrate made of Si or the like, 2 is a gate insulating film made of SiO ₂ or the like, 3 is a gate electrode made of polysilicon or the like, 4 is a layer in which the crystalline state is disturbed, and 5 is An impurity injection layer and 6 are source / drain diffusion layers. Next, the manufacturing method will be described.

First, as shown in FIG. 1 (a), the substrate 1 is oxidized by thermal oxidation to form a silicon oxide film having a film thickness of 30 Å, and polysilicon is deposited on the silicon oxide film by the CVD method. After forming a polysilicon film having a film thickness of 1500Å, the polysilicon film and the silicon oxide film are selectively etched by dry etching to form the gate electrode 3 and the gate oxide film 2.

Next, as shown in FIG. 1 (b), the gate
Using the electrode 3 as a mask, for example, Ge ⁺10 to 30 ke
About V, 2 × 10¹⁴cm^-2Under the conditions of
Enter to disturb the crystalline state of the surface. Under the above conditions, 20 on the surface
A layer 4 with a crystal state of 0-600Å disturbed is formed
It At this time, many point defects 11 occur (the size is exaggerated)
Has been).

Next, as shown in FIG. 1 (c), the impurity B ⁺ is ¹ to 5 keV with the gate electrode 3 as a mask.
Degree (about 3 to 30 keV when BF ₂ ⁺ is used), 2
It is injected into the substrate 1 under the condition of × 10 ¹⁴ cm ^-2 and the thickness is 20
An impurity injection layer 5 of about 0 to 1000 Å is formed. As a result, the impurity injection layer 5 covers the layer 4 in which the crystal is disturbed. At this time, a point defect 11 is further generated. The Ge ⁺ implantation step may be omitted if the crystals are sufficiently disturbed by ion implantation of desired impurities. For example, BF that is heavier than Si, which is an element forming a semiconductor layer as implanted ions.
This is the case when ₂ ⁺ , In, P, As, Sb, etc. are used. In this case, the state of FIG.
The situation is formed. This is because the depth at which the crystals are disturbed by the impurity ion implantation is usually shallower than the depth at which the impurities are distributed.

Next, as shown in FIG.
A low temperature annealing treatment at a temperature of 650 ° C. to 650 ° C. (for example, 550 ° C. for 8 hours) is performed to recrystallize the layer 4 whose crystal state is disturbed.
At this time, the point defects 11 generated by the ion implantation of Ge ⁺ , B ^{+ and the} like are efficiently captured at the interface of the layer 4 and disappear. The layer 4 also disappears after a certain annealing time. However, residual crystal defects 12 remain. The temperature of the above-mentioned annealing is a temperature within a range in which recrystallization of silicon occurs but diffusion of impurities does not occur.

Next, as shown in FIG.
The residual crystal defects 12 are eliminated by performing a high temperature annealing process at a temperature of not less than 1000 ° C. and less than 1000 ° C. (for example, 900 ° C., 10 seconds). At this time, since the point defects are removed in advance, the diffusion of impurities is suppressed and a shallow junction is formed.

Then, BPS is applied so as to cover the gate electrode 3.
After forming an interlayer insulating film made of G or the like and forming a contact hole in the interlayer insulating film, a wiring layer made of Al or the like is formed so as to make contact with the gate electrode 3 and the source / drain diffusion layer 6 through the contact hole. By forming it, a semiconductor device can be obtained.

That is, in the above specific example, first, the substrate 1 is ion-implanted to disturb the crystal state of the substrate 1 to form the layer 4 in which the crystal state is disturbed, and then the impurities are ion-implanted to implant the impurity-implanted layer 5. And then the point defects caused by the ion implantation are eliminated in the process of recovering the crystallinity of the layer 4 whose crystal state is disturbed by the first annealing. This suppresses enhanced diffusion in the subsequent second annealing. Then, by the second annealing, the crystal defects remaining in the first annealing are eliminated to obtain a low leak diffusion layer.
At this time, the optimum temperature is selected so as to prevent the resistance increase due to the impurity inactivation and the crystal recovery effect.

FIG. 4 shows the effect of the above specific example. In the pMOSFET, the threshold shifts in the positive direction as the gate length becomes shorter due to the short channel effect. In the figure, the conventional method (A) is a case where only annealing at 1000 ° C. for 10 seconds is performed, but the short channel effect is large, and the threshold value is largely deviated at a gate length of about 0.1 μm. On the other hand, in the case where the first annealing (550 ° C., 8 hours) described in this specification is performed and the second annealing is not performed (B), impurities are not diffused in the first annealing. A shallow junction is formed, and the short channel effect is significantly suppressed as compared with the conventional method (A). However, because the crystal defects remain, the transistor width is 1 μm.
A leak current of 10 ⁻⁹ A flows around. In the case (C) according to the present invention, the second annealing (900 ° C., 10 seconds) is performed in addition to the first annealing. Since slight impurity diffusion occurs in the second annealing, the short channel effect is slightly deteriorated as compared with the case (B) in which the second annealing is not performed. However, since the diffusion is suppressed by the effect of the first annealing, the short channel effect is significantly suppressed as compared with the conventional method (A). By further reducing crystal defects, the leak current per 1 μm width of the transistor is 10
^-11 A, which is two orders of magnitude smaller than that in the case where the second annealing is not performed (B), and is suppressed to the same level as the conventional method. Also, the parasitic resistance per unit width of the transistor was the same as that of the conventional method (350 Ωμm).

Although the present invention has been described based on the case where it is applied to a pMOS, the present invention is not limited to these specific examples.

In the above example, B was used as the impurity of the source / drain diffusion layer, but other p-type impurities such as In may be used. Further, Ge ⁺ is used as the ion for ion implantation for disturbing the crystal state of the substrate surface, but neutral ions such as Si ⁺ that do not affect the electrical characteristics of other semiconductors may be used. Further, when the target conductivity type is the above-mentioned p-type, an n-type impurity such as As ⁺ or Sb ⁺ , which is the opposite conductivity type, may be used.
The p-type source / drain may be formed so that the type impurity concentration exceeds the n-type impurity concentration. Further, the n-type substrate is used as a p-type substrate, and the impurity ions to be implanted are P, As, Sb
It can also be applied to an nMOS by using n-type impurity ions such as. In the case of nMOS, neutral impurities such as Ge ⁺ and S are used as ions for ion implantation to disturb the crystalline state.
In addition to i ^+, a p-type impurity such as In ⁺ may be used. In this case, the n-type source / drain may be formed such that the n-type impurity concentration exceeds the p-type impurity concentration in the impurity ion implantation step.

Further, as in the case where the impurity ions are As ⁺ , when the crystal state of the substrate surface is disturbed by ion implantation of the impurity ions, which is heavier than Si which is a constituent element of the semiconductor substrate (for example, As ⁺ , 20keV, 2
In the case of × 10 ¹⁴ cm ^-2 ), the ion implantation for disturbing the crystal state can be combined with the ion implantation of impurities to reduce the number of manufacturing steps.

Furthermore, the order of the ion implantation process for disturbing the crystal state and the ion implantation process for impurities can be exchanged, but the effect of preventing channeling (a phenomenon in which ions deeply penetrate in a specific crystal direction) can be obtained. Therefore, it is desirable to implant the impurity ions after performing the ion implantation for disturbing the crystal state.

Further, in FIG. 1C, the impurity injection layer 5
Completely covers the crystal-disturbed layer 4, but the impurity-implanted layer 5 may be included in the crystal-disturbed layer 4. However, from the viewpoint of leakage reduction, it is desirable that the impurity injection layer 5 is deeper than the layer 4 in which the crystal is disturbed. This is because the residual crystal defect 12 is often formed at the boundary of the layer 4, and even if the defect 12 is not partially recovered by the second annealing,
This is because they are included in the diffusion layer 6 and the increase in leakage is relatively small.

Further, in the above example, the gate insulating film is patterned together with the gate electrode, and ion implantation is performed on the exposed surface of the semiconductor substrate using the gate electrode as a mask. However, the gate insulating film is not patterned and the gate is not patterned. It is also possible to implant ions through the insulating film.

The atmosphere at the time of annealing is not particularly limited, and it may be carried out in an oxidizing atmosphere such as the air or in an inert gas atmosphere such as nitrogen gas. As described above, when the first annealing is performed in an oxidizing atmosphere with the substrate surface exposed, an oxide film is formed on the substrate surface. In that case, the oxide film formed causes the second annealing to be performed. It also has the effect of suppressing the outward diffusion of the impurity ions.

Ions are also implanted into the gate electrode at the time of ion implantation. When the gate electrode is polysilicon, crystal regrowth occurs due to the first annealing, resulting in polysilicon having large grain boundaries. To lower the resistance. Further, in the case of a metal, it can be expected to be reduced in resistance by being silicidized by Si ion implantation. If ion implantation into the gate electrode is not desired, an oxide film is formed separately on the gate electrode,
This may be used as a mask.

In FIG. 1, the source / drain diffusion layer 6 is illustrated in the simplest form for simplification of description, but the method according to the present invention has a more complicated source / drain diffusion layer. It is also applicable to the manufacturing process of the structure. For example, the source / drain diffusion layer 6 is shallow in the vicinity of the gate electrode 3 and deep in the other portions, so-called source / drain / extension structure.

The source / drain / extension structure has a further resistance by making the source / drain junction shallow near the gate electrode to suppress the short channel effect, while deepening the source / drain junction in other portions. The structure is intended to facilitate the formation of the wiring by making a reduction and making contact with the metal wiring in the deep region of the source / drain junction. In this case, it is important to make the junction shallow especially in the shallow source / drain regions, and this can be realized by applying the present invention.

As a second embodiment, a method of applying the present invention to a source / drain extension structure will be described with reference to FIG. First, the gate electrode 3 is formed similarly to FIG. 1A (FIG. 5A). Next, similarly to FIG. 1C, the layer 4 in which the crystal is disturbed and the impurity introduction layer 5A are formed using the gate electrode 3 as a mask (FIG. 5B). At this time, the layer 4 and the layer 5A may be formed by separate ion implantation or may be formed by the same ion implantation. Next, after depositing an insulating film on the entire surface of the substrate, anisotropic etching is performed to form a gate sidewall insulating film 7 on the side surface of the gate electrode 3 (FIG. 5C). Next, using the gate electrode 3 and the gate sidewall insulating film 7 as a mask, deeply ion-implanting impurities of the same conductivity type as the impurity introduction layer 5A to form the impurity introduction layer 5 composed of a shallow region and a deep region ( Figure 5
(D)). Ion implantation for forming this deep region is generally performed by implanting a larger amount of impurities with higher energy and intentionally introducing the impurities deeper than when forming the impurity introduction layer 5A. For example, in the case of the same pMOSFET as in the first embodiment, B ⁺ should be ² to 10 ke.
^{Implant at} about ^{2 to} 5 × 10 ¹⁵ cm ^{−2 with} V. At this time, the crystal-disturbed layer 4 may be expanded (not shown), but this is not related to the essence of the invention. Finally, the source / drain diffusion layer 6 is formed by performing the first and second anneals described above.

The first annealing is optimally carried out once in the state of FIG. 5 (d) where all the ion implantations have been completed, but the effect is obtained even if it is performed in the state of FIG. 5 (b), for example. To be Further, it may be carried out in both of the states shown in FIGS. 5 (b) and 5 (d).

The difference between the above-mentioned second embodiment and the first embodiment is that the impurity introduction layer 5 is 2 in FIG. 5 (b) and FIG. 5 (d).
The effect of the present invention is similar to that of the first embodiment, although it is formed by ion implantation once. That is, shallow source / drain and deep source / drain
The point defects formed by the single ion implantation are eliminated without impurity diffusion due to the effect of the first low temperature annealing and the layer 4 in which the crystal is disturbed, and the residual defects are removed by the second high temperature annealing. As a result, it is possible to suppress the diffusion of impurities and form a particularly shallow source / drain region shallow, and to form the entire source / drain region with low resistance and low leak.

As a third embodiment, another method of applying the present invention to a source / drain extension structure will be described with reference to FIG. First, the gate electrode 3 is formed similarly to FIG. 1A (FIG. 6A). Next, after depositing an insulating film on the entire surface of the substrate, anisotropic etching is performed to form a gate sidewall insulating film 7 on the side surface of the gate electrode 3 (FIG. 6).
(B)). The gate sidewall insulating film 7 in this embodiment is
It is preferable to use a material that is easily removed later by selective etching, for example, a silicon nitride film. Next, a deep impurity introduction layer 5B is formed by ion implantation using the gate electrode 3 and the gate sidewall insulating film 7 as a mask (FIG. 6).
(C)). Similar to the second embodiment, in the case of pMOSFET, B ⁺ is implanted at 2 to 10 keV and about ^{2 to} 5 × 10 ¹⁵ cm ^-2 . At this time, a layer in which crystals are disturbed may be formed inside the impurity introduction layer 5B. Next, a third anneal is performed to activate the impurity introduction layer 5B and convert it into deep source / drain regions 6B. At this time, if there is a layer in which the crystal is disturbed, it is once recovered. The third annealing condition at this time can be determined independently of the optimum conditions for the shallow source / drain regions to be formed later, and is, for example, RTA treatment at 1000 ° C. for 10 seconds. Before or after this step, the gate sidewall insulating film 7 is removed by the selective etching method (FIG. 6D). For example, if the gate sidewall insulating film 7 is a silicon nitride film, etching with a hot phosphoric acid solution may be used. Next, similarly to FIG. 1C, the layer 4 in which the crystal is disturbed and the impurity introduction layer 5A are formed using the gate electrode 3 as a mask. At this time, the layer 4 and the layer 5A may be formed by separate ion implantation or may be formed by the same ion implantation. Finally, the source / drain diffusion layer 6 is formed by performing the first and second anneals described above.

The difference between the third embodiment and the second embodiment described above is that the order of forming the deep source / drain regions and the shallow source / drain regions is reversed, and that the third annealing is added. is there. As an advantage of using such a method, when the gate electrode 3 is a semiconductor such as polysilicon and it is necessary to introduce impurities into the inside by ion implantation, this ion implantation step is performed to form deep source / drain regions. Therefore, it becomes easy to use it as the ion implantation step. That is, a relatively high temperature annealing (1000 ° C., about 10 seconds or more) is required for introducing impurities into the gate electrode 3, but for a shallow source / drain region, as described above, such a high temperature is required. Annealing is inconvenient. However, according to the third embodiment, before the shallow source / drain impurity regions 5A are formed, the impurities are also introduced into the gate electrode 3 simultaneously with the introduction of the impurities for forming the deep source / drain. By performing the high-temperature third annealing, the impurities introduced into the gate electrode 3 are also activated, and the resistance reduction of the gate electrode 3 is promoted. As described above, since the third annealing is performed before forming the shallow source / drain regions, it is possible to raise the temperature to a temperature suitable for introducing impurities into the gate electrode and facilitate introduction of impurities into the gate electrode. Another advantage is that the third annealing is performed at a sufficiently high temperature, and the effect of further lowering the resistance of the deep source / drain regions as compared with the second embodiment can be expected.

The effect of the present invention in this embodiment is similar to that of the first embodiment, and the point defects formed by the shallow source / drain ion implantation are disturbed by the first low temperature annealing and the crystal. Due to the effect of the deposited layer 4, it is eliminated without causing impurity diffusion, and the residual defects are removed by the second high temperature annealing. As a result, it is possible to suppress the diffusion of impurities to form the shallow source / drain regions shallow, and to suppress the resistance and the leak in the particularly shallow source / drain regions.

As described above, according to the present invention,
Shallow source / without increasing resistance and leakage current
There is an effect that the diffusion layer of the drain diffusion layer can be formed and the short channel effect can be suppressed.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and it is apparent that each embodiment can be appropriately modified within the scope of the technical idea of the present invention.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a specific example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a diagram illustrating a manufacturing method of a conventional example.

FIG. 3 is a diagram illustrating an effect of the present invention.

FIG. 4 is a diagram illustrating an effect of the present invention.

FIG. 5 is a process sectional view illustrating the manufacturing process of the second embodiment of the present invention.

FIG. 6 is a process cross-sectional view illustrating the manufacturing process of the third embodiment of the present invention.

[Explanation of symbols]

1 substrate 2 Gate insulating film 3 Gate electrode 4 Layer with disturbed crystal state 5 Impurity injection layer 6 Source / drain diffusion layer 7 Gate sidewall insulation film 11 point defects 12 Residual crystal defects

Continued front page    F-term (reference) 5F140 AA00 AA13 AA21 AA24 AA39                       AC01 BA01 BE07 BF04 BG08                       BG28 BG38 BG54 BH14 BH21                       BH22 BJ05 BK02 BK03 BK10                       BK13 BK20 CC07 CF07

Claims (14)

[Claims] 1. A step of forming a gate insulating film and a gate electrode on a semiconductor substrate; a step of disturbing a crystalline state of a surface of the semiconductor layer by ion-implanting the semiconductor layer using the gate electrode as a mask; A step of implanting impurity ions into the semiconductor layer using the gate electrode as a mask; a step of recovering the disorder of the crystalline state by first annealing in a temperature range that does not cause diffusion of the impurities; A step of forming a sidewall insulating film, and using the gate electrode and the gate sidewall insulating film as a mask,
Crystals remaining in the first annealing due to a step of ion-implanting impurities of the same conductivity type as the ion-implanted impurities at a higher energy than the ion-implantation, and a second annealing at a higher temperature than the first annealing. A method of manufacturing a semiconductor device, which comprises sequentially performing a step of recovering a defect. 2. A step of forming a gate insulating film and a gate electrode on a semiconductor substrate, a step of disturbing a crystal state of a surface of the semiconductor layer by ion-implanting the semiconductor layer using the gate electrode as a mask, A step of implanting impurity ions into the semiconductor layer using the gate electrode as a mask; a step of recovering the disorder of the crystalline state by first annealing in a temperature range that does not cause diffusion of the impurities; A step of forming a sidewall insulating film, and using the gate electrode and the gate sidewall insulating film as a mask,
The first anneal is performed by ion-implanting an impurity of the same conductivity type as the ion-implanted impurity with a higher dose and energy than the ion-implantation, and a second anneal at a higher temperature than the first anneal. The method for manufacturing a semiconductor device, which comprises sequentially performing the step of recovering the remaining crystal defects. 3. A step of forming a gate insulating film, a gate electrode and a gate sidewall insulating film on a semiconductor substrate; a step of implanting impurity ions into the semiconductor layer using the gate electrode and the gate sidewall insulating film as a mask; and annealing. And activating the impurities by selectively removing the gate sidewall insulating film, and disturbing the crystalline state of the surface of the semiconductor layer by implanting ions into the semiconductor layer using the gate electrode as a mask. Ion-implanting an impurity having the same conductivity type as the ion-implanted impurities and forming a source / drain extension with energy lower than that of the ion-implantation, using the gate electrode as a mask; First temperature range not causing diffusion of impurities forming drain extension And a step of recovering the disorder of the crystalline state by Neel, and a step of recovering the crystal defects remaining in the first annealing by a second annealing at a temperature higher than that of the first annealing. Of manufacturing a semiconductor device. 4. A step of forming a gate insulating film, a gate electrode and a gate sidewall insulating film on a semiconductor substrate; a step of implanting impurity ions into the semiconductor layer using the gate electrode and the gate sidewall insulating film as a mask; and annealing. And activating the impurities by selectively removing the gate sidewall insulating film, and disturbing the crystalline state of the surface of the semiconductor layer by implanting ions into the semiconductor layer using the gate electrode as a mask. And a step of ion-implanting an impurity having the same conductivity type as the ion-implanted impurities and forming a source / drain extension with a lower dose amount and lower energy than the ion-implantation, using the gate electrode as a mask. And does not cause diffusion of impurities forming the source / drain extension A step of recovering the disorder of the crystalline state by a first annealing in a temperature range, and a step of recovering the crystal defects remaining in the first annealing by a second annealing having a higher temperature than the first annealing. A method of manufacturing a semiconductor device, which is performed sequentially. 5. The ion implanted to disturb the crystal state of the surface of the semiconductor layer is an ion that does not affect the electrical characteristics of the semiconductor. A method of manufacturing a semiconductor device according to item 1. 6. The ions implanted to disturb the crystal state of the surface of the semiconductor layer are ions giving a conductivity type opposite to the target conductivity type, and the target conductivity type is changed in the impurity ion implantation step. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the given ions are implanted at a higher concentration than the ions giving the opposite conductivity type. 7. A step of forming a gate insulating film and a gate electrode on a semiconductor substrate, a step of ion-implanting a semiconductor layer using the gate electrode as a mask, and at the same time disturbing a crystal state of a surface of the semiconductor layer, Recovering the disorder of the crystalline state by first annealing in a temperature range that does not cause impurity diffusion; forming a gate sidewall insulating film on the gate electrode; using the gate electrode and the gate sidewall insulating film as a mask ,
Crystals remaining in the first annealing due to a step of ion-implanting impurities of the same conductivity type as the ion-implanted impurities at a higher energy than the ion-implantation, and a second annealing at a higher temperature than the first annealing. A method of manufacturing a semiconductor device, which comprises sequentially performing a step of recovering defects. 8. A step of forming a gate insulating film and a gate electrode on a semiconductor substrate, a step of implanting ions into the semiconductor layer using the gate electrode as a mask, and at the same time disturbing a crystalline state of the surface of the semiconductor layer, Recovering the disorder of the crystalline state by first annealing in a temperature range that does not cause impurity diffusion; forming a gate sidewall insulating film on the gate electrode; using the gate electrode and the gate sidewall insulating film as a mask ,
The first anneal is performed by ion-implanting an impurity of the same conductivity type as the ion-implanted impurity with a higher dose and energy than the ion-implantation, and a second anneal at a higher temperature than the first anneal. The method for manufacturing a semiconductor device, which comprises sequentially performing the step of recovering the remaining crystal defects. 9. A step of forming a gate insulating film, a gate electrode and a gate sidewall insulating film on a semiconductor substrate; a step of implanting ions into the semiconductor layer using the gate electrode and the gate sidewall insulating film as a mask; A step of activating impurities, a step of selectively removing the gate sidewall insulating film, and a source / drain extension having the same conductivity type as the ion-implanted impurities using the gate electrode as a mask A step of ion-implanting impurities with energy lower than that of the ion-implantation and simultaneously disturbing the crystalline state of the surface of the semiconductor layer; and a first temperature range not causing diffusion of impurities forming the source / drain extensions. A step of recovering the disorder of the crystalline state by annealing, and A method of manufacturing a semiconductor device, which comprises sequentially performing a step of recovering the crystal defects remaining in the first annealing by a second warm annealing. 10. A step of forming a gate insulating film, a gate electrode and a gate sidewall insulating film on a semiconductor substrate; a step of implanting ions into the semiconductor layer using the gate electrode and the gate sidewall insulating film as a mask; A step of activating impurities, a step of selectively removing the gate sidewall insulating film, and a source / drain extension having the same conductivity type as the ion-implanted impurities using the gate electrode as a mask Ion-implanting impurities with a dose and energy lower than that of the ion-implantation, and at the same time disturbing the crystalline state of the surface of the semiconductor layer, and a temperature range that does not cause diffusion of impurities forming the source / drain extensions Recovering the disorder of the crystalline state by the first annealing of A method of manufacturing a semiconductor device, which comprises sequentially performing a step of recovering crystal defects remaining in the first annealing by a second annealing having a temperature higher than that of the first annealing. 11. The method of manufacturing a semiconductor device according to claim 7, wherein the implanted impurity ions are ions that are heavier than elements forming the semiconductor layer. 12. The first annealing temperature is 450 ° C.
11. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is 650 ° C. or higher. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the second annealing temperature is 800 ° C. or higher and lower than 1000 ° C. 14. A region in which impurities are implanted is deeper than a region in which a crystalline state is disturbed.
The method for manufacturing a semiconductor device according to any one of 1.