JP4196843B2 - Manufacturing method of semiconductor devices - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device such as a MOS type IC (an integrated circuit including a MOS type transistor [insulated gate field effect transistor]), and more particularly to an improvement in a method for recovering process damage of a MOS type transistor by hydrogen annealing. Is.

  Conventionally, it is known to perform heat treatment (hydrogen annealing treatment) in a hydrogen-containing atmosphere to recover process damage to a MOS transistor (see, for example, Patent Document 1). It is also known that when a hydrogen annealing process is performed, if a wiring material layer including a Ti (titanium) layer is present above the MOS transistor, the Ti layer occludes hydrogen, so that the process damage cannot be recovered sufficiently. (For example, refer to Patent Document 2).

FIG. 8 shows an example of a conventional MOS IC. A field insulating film 2 made of a silicon oxide film is formed on the surface of the silicon substrate 1, and the first and second MOSs are respectively formed in the silicon portions in the first and second element holes of the insulating film 2. Type transistors T ₁ and T ₂ are formed.

The transistor T ₁ includes a gate insulating film F, a gate electrode layer G, side spacers K ₁ and K ₂ on both sides of the electrode layer G, a source region S ₁ and a drain region D ₁ having a relatively low impurity concentration, an impurity It has a source region S ₂ and a drain region D ₂ having a relatively high concentration, and has a so-called LDD (Lightly Doped Drain) structure. Transistor _{T 2} are, have the same structure as the transistor _{T 1.}

On the upper surface of the substrate, an interlayer insulating film 3 made of a silicon oxide film is formed by a CVD (Chemical Vapor Deposition) method so as to cover the insulating film 2 and the transistors T ₁ and T ₂ . In the insulating film 3, source and drain connection holes (not shown) corresponding to the source region S ₂ , the drain region D _{2, and the} like are formed by photolithography and dry etching. After sequentially depositing a Ti layer and an Al alloy layer on the insulating film 3 by a sputtering method, the deposited layer is patterned by photolithography and dry etching treatment to form a source for a source comprising a stack of a Ti layer and an Al alloy layer. A drain wiring layer (not shown) is formed. At this time, on the insulating film 3, the wiring material layer 4 to cover the transistors T ₁ consists of a stack of Ti layer 4a and the Al alloy layer 4b is formed.

Next, the transistors T ₁ and T ₂ are subjected to hydrogen annealing treatment for recovering process damage. The hydrogen annealing treatment is usually performed at the final stage after completing the main processing steps. That is, since the interface state may increase due to damage during processing such as dry etching, it is meaningful to perform hydrogen annealing as a process for reducing the interface state after these processing steps.

After the hydrogen annealing treatment, the silicon oxide film 5 is formed on the insulating film 3 by the CVD method so as to cover the wiring material layer 4 and the wiring layer. A silicon nitride film 6 is formed on the oxide film 5 by a CVD method. The oxide film 5 and the nitride film 6 are used as a passivation (surface protection) film.
JP-A-7-74167 JP-A-9-252131

According to the above-described prior art, in the transistor T ₂ that is not covered with the wiring material layer 4, dangling bonds at the interface between the substrate and the gate oxide film are terminated with hydrogen, thereby recovering the process damage. The voltage can be set to an appropriate value. However, in the transistor T ₁ covered with the wiring material layer 4, the process damage is not sufficiently recovered, and the threshold voltage cannot be set to an appropriate value. The threshold voltage of the transistor T ₁ is vary widely between multiple samples. This is probably because the Ti layer 4a occludes hydrogen, so that the hydrogen does not sufficiently reach the interface between the substrate and the gate oxide film F.

  An object of the present invention is to provide a novel method of manufacturing a semiconductor device capable of recovering process damage by hydrogen annealing when a wiring layer with a Ti layer is provided above a MOS transistor.

The semiconductor device according to the present invention is
Forming a MOS transistor on one main surface of the semiconductor substrate;
Forming an insulating film covering one main surface of the semiconductor substrate and the MOS transistor;
A silicon nitride layer is deposited on the insulating film by plasma CVD, and a part of the silicon nitride layer covers the channel portion of the MOS transistor and remains smaller than the element hole of the MOS transistor in plan view. Forming a silicon nitride film consisting of the remaining portion of the silicon nitride layer by removing so as to
A laminated layer of a titanium layer and a wiring material layer is formed on the insulating film and the silicon nitride film via another insulating film, and a part of the laminated layer covers the channel portion of the MOS transistor and is viewed in plan view. Forming a wiring layer consisting of the remaining portion of the stack by removing the MOS transistor so as to remain over the element hole;
After forming the wiring layer, performing a heat treatment for recovering process damage to the MOS transistor in a hydrogen-containing atmosphere;
Forming a passivation film comprising a stack of a silicon oxide film and a silicon nitride film covering the wiring layer;
Is included.

According to the method for manufacturing a semiconductor device of the present invention, hydrogen annealing treatment (heat treatment for recovering process damage in a hydrogen-containing atmosphere) with a silicon nitride film disposed between the wiring layer with the Ti layer and the MOS transistor is performed. Is done. The silicon nitride film is formed by a plasma CVD method. In the plasma CVD process, since silane, ammonia, or the like is used as a source gas, the silicon nitride film does not have a complete Si ₃ N ₄ composition, and unreacted hydrogen is removed from the film such as N—H and Si—H. Includes in combined state. For this reason, the silicon nitride film formed by the plasma CVD method functions as a hydrogen supply source during the hydrogen annealing process. In the hydrogen annealing treatment, hydrogen supplied from the silicon nitride film in addition to hydrogen supplied from the hydrogen-containing atmosphere contributes to the inactivation of the interface states. Therefore, even in the MOS type transistor covered with the wiring layer with the Ti layer, the process damage can be sufficiently recovered.

  Since the silicon nitride film has a large relative dielectric constant of about 7, if it is formed over the entire surface, the inter-wiring capacitance is increased. Therefore, in the present invention, the silicon nitride film is formed in a pattern that covers the channel portion of the MOS transistor, thereby avoiding an increase in inter-wiring capacitance.

  In the method of manufacturing a semiconductor device of the present invention, in the step of forming the wiring layer, the wiring layer has a width of 5 μm or more as the wiring layer by removing the stacked layer so that a part thereof remains with a width of 5 μm or more. May be formed. In this case, since there is a wiring layer with a large Ti layer having a width of 5 μm or more above the MOS transistor, the amount of hydrogen occluded by the Ti layer increases during the heat treatment. In the present invention, since the silicon nitride film formed by the plasma CVD method exists between the wiring layer and the MOS transistor as a hydrogen supply source, the process damage can be sufficiently recovered.

  In the method of manufacturing a semiconductor device according to the present invention, after forming the wiring layer, a step of forming a passivation silicon nitride film by plasma CVD is performed to cover the wiring layer, thereby forming the passivation silicon nitride film. Then, the heat treatment may be performed on the MOS transistor.

  In this case, the silicon nitride film for passivation is formed to a thickness that allows hydrogen to pass therethrough. As described above, since the silicon nitride film formed by the plasma CVD method acts as a hydrogen supply source during the hydrogen annealing process, hydrogen supplied from the silicon nitride film for passivation also deactivates the interface state. Contribute. Therefore, the process damage can be recovered more sufficiently.

  According to the present invention, since the process damage can be sufficiently recovered in the MOS transistor covered with the wiring layer with the Ti layer, the threshold voltage can be optimized and the variation in the threshold voltage can be reduced. An effect is obtained.

  In addition, since the silicon nitride film for supplying hydrogen is formed in a pattern that covers the channel portion of the MOS transistor, an increase in inter-wiring capacitance is avoided, so that the operation speed can be increased and the operation margin can be secured. can get.

  1 to 5 show a method of manufacturing a MOS IC according to an embodiment of the present invention, and steps (1) to (5) corresponding to the respective drawings will be described in order.

  (1) A P-type well region 12 is formed on one main surface of a semiconductor substrate 10 made of silicon, for example, by selective impurity ion implantation. Then, a field insulating film 14 made of a silicon oxide film having an element hole 14a and connection holes 14b and 14c is formed on the surface of the well region 12 by a selective oxidation process. The field insulating film 14 can also be formed by providing a groove on the surface of the well region 12 by selective etching and depositing an insulating film such as a silicon oxide film by a CVD method so as to fill the groove.

On the surface of the well region 12, a MOS transistor T is formed in a semiconductor portion corresponding to the connection hole 14a by a well-known method. The transistor T includes a gate insulating film F, a gate electrode layer G, side spacers K ₁ and K ₂ on both sides of the electrode layer G, an N ⁻ -type source region S ₁ and a drain region D ₁ having a relatively low impurity concentration. And an N ⁺ type source region S ₂ and drain region D ₂ having a relatively high impurity concentration, and has an LDD structure. The transistor T is not limited to the LDD structure, and various structures can be formed.

P ⁺ -type well contact regions CN ₁ and CN ₂ are formed in the semiconductor portions respectively corresponding to the connection holes 14b and 14c on the surface of the well region 12 by selective impurity ion implantation processing or the like. The contact regions CN ₁ and CN ₂ are both used for applying a substrate potential to the transistor T.

(2) On the upper surface of the substrate 10, an interlayer insulating film 16 made of a silicon oxide film or the like is formed so as to cover the insulating film 14, the transistor T, and the contact regions CN ₁ and CN ₂ . The insulating film 16 is preferably formed in a flat shape by combining a coating insulating film such as SOG (spin-on-glass) and a deposited insulating film by a CVD method or the like to form a laminated structure.

Next, connection holes 16a, 16b, 16c, and 16d corresponding to the source region S ₂ , drain region D ₂ , and contact regions CN ₁ and CN ₂ are formed in the insulating film 16 by photolithography and dry etching. Then, a Ti layer as a barrier metal layer is deposited on the insulating film 16 by sputtering or the like so as to cover the connection holes 16a to 16d, and then overlapped with the Ti layer by Al or an Al alloy (for example, Al-Si-). An Al-based metal layer such as a Cu alloy is deposited by sputtering or the like. Thereafter, the laminated layers of the Ti layer and the Al-based metal layer are patterned by a dry etching process using the resist layer as a mask to form the wiring layers 18, 20, 22, and 24. The wiring layers 18 to 24 may be formed by a lift-off process in which a resist layer having wiring holes is formed in accordance with a wiring pattern, and then a Ti layer and an Al-based metal layer are deposited and then the resist layer is removed. it can.

The wiring layer 18 is made of a laminate of extensive Al-based metal layer 18b on the Ti layer 18a, is connected to the source region _{S 2} through the connection hole 16a. Wiring layer 20 is made of a laminate of extensive Al-based metal layer 20b on the Ti layer 20a, is connected to the drain region _{D 2} via a contact hole 16b. Wiring layer 22 is made of a laminate of extensive Al-based metal layer 22b on the Ti layer 22a, is connected to the contact region CN ₁ via the connecting hole 16c. Wiring layer 24 is made of a laminate of extensive Al-based metal layer 24b on the Ti layer 24a, is connected to the contact region CN ₂ via a contact hole 16d. Each of the wiring layers 18 to 24 is a first-layer metal wiring. The first-layer metal wiring is mainly used for short-distance connections such as a source, drain, gate, and well contact, and does not require a large wiring width.

  (3) A silicon oxide film 26 is formed on the insulating film 16 by a CVD method so as to cover the wiring layers 18 to 24. The silicon oxide film 26 constitutes an interlayer insulating film 31 together with the silicon oxide film 30 shown in FIG.

  Next, a silicon nitride layer is deposited on the silicon oxide film 26 by plasma CVD. Then, by patterning the silicon nitride layer by a dry etching process using the resist layer as a mask so that a part of the silicon nitride layer remains covering the channel portion below the gate electrode layer G of the transistor T, the silicon nitride layer is patterned from the remaining portion of the silicon nitride layer. A silicon nitride film 28 is formed. The silicon nitride film 28 is used as a hydrogen supply source in the later-described hydrogen annealing process, and is formed to a thickness of, for example, 50 to 300 nm by a plasma CVD method. The silicon nitride film 28 can also be formed by a lift-off process in which a resist layer having a hole corresponding to the pattern of the film 28 is formed and then the silicon nitride layer is deposited and then the resist layer is removed.

  FIG. 6 shows an example of a planar pattern of the silicon nitride film 28. In the example of FIG. 6, the silicon nitride film 28 is formed so as to cover the channel portion below the gate electrode layer G with a rectangular planar pattern slightly smaller than the element hole 14 a of the insulating film 14. FIG. 3 corresponds to a cross section taken along line X-X ′ in FIG. 6. In FIG. 6, GC indicates a contact portion between the gate electrode layer G and the first-layer metal wiring.

  (4) A silicon oxide film 30 is formed on the silicon oxide film 26 by a CVD method so as to cover the silicon nitride film 28. The silicon oxide film 30 constitutes an interlayer insulating film 31 together with the silicon oxide film 26.

  Next, connection holes 30a and 30b corresponding to the wiring layers 22 and 24, respectively, are formed in the insulating film 31 by photolithography and dry etching. Then, a Ti layer as a barrier metal layer is deposited on the insulating film 31 by a sputtering method or the like so as to cover the connection holes 30a and 30b, and then overlapped with the Ti layer by Al or an Al alloy (for example, Al-Si-). An Al-based metal layer such as a Cu alloy is deposited by sputtering or the like. Thereafter, the laminated layers of the Ti layer and the Al-based metal layer are patterned by a dry etching process using the resist layer as a mask to form wiring layers 32, 34, and 36. The wiring layers 32 to 36 can also be formed by lift-off processing in the same manner as described above for the first-layer metal wiring.

  The wiring layer 32 is formed by stacking an Al-based metal layer 32b on a Ti layer 32a. As shown in FIGS. 4 and 6, the element hole 14a, the transistor T, the wiring layers 18 and 20, the silicon nitride film 28, etc. It is formed to cover. The wiring layer 34 is made of a laminate in which an Al-based metal layer 34b is stacked on a Ti layer 34a, and is connected to the wiring layer 22 through a connection hole 30a. The wiring layer 36 is formed of a laminate in which an Al-based metal layer 36b is stacked on a Ti layer 36a, and is connected to the wiring layer 24 through a connection hole 30b.

  Each of the wiring layers 32 to 36 is a second-layer metal wiring. The second-layer metal wiring is used as a relatively long-distance wiring such as supply of a power supply potential and a ground potential in addition to connection at a short distance. A long-distance wiring that supplies a power supply potential or a ground potential needs to have a large wiring width in order to reduce a voltage drop due to wiring resistance. The wiring layer 32 is an example of this type of long-distance wiring, and is formed to have a width W of 5 μm or more so as to cover the element hole 14a, the gate electrode layer G, and the like as shown in FIG. The cross section in FIG. 4 corresponds to the cross section along the line X-X ′ in FIG. 6. The wiring width W shown in FIG. 6 is a wiring width in the direction parallel to the direction of the channel current (source-drain current), but the wiring width in the direction orthogonal to the direction of the channel current may be 5 μm or more. .

  In the above example, the silicon nitride film 28 is disposed in the interlayer insulating film 31 (between the silicon oxide films 26 and 30). However, the silicon nitride film 28 is disposed on the insulating film 16 (silicon oxide film) in the interlayer insulating film 16. It may be disposed on the silicon oxide film 30 (under the wiring layer 32) or the like.

  After forming the wiring layers 32 to 36 as shown in FIG. 4, the structure shown in FIG. 4 is subjected to hydrogen annealing treatment. The treatment conditions at this time can be a hydrogen concentration of 20 [%], a temperature of 400 [° C.], and a time of 30 [min]. In such a hydrogen annealing process, hydrogen from the silicon nitride film 28 is supplied to the channel portion of the transistor T in addition to hydrogen from the processing atmosphere, contributing to reduction of the interface state. For this reason, even if the wiring layer 32 has a large area with a width of 5 μm or more, process damage due to dry etching or the like can be sufficiently recovered. As a result, the threshold voltage of the transistor T becomes an appropriate value, and variations in threshold voltage are reduced.

  (5) After the hydrogen annealing process, a silicon oxide film 38 is formed on the silicon oxide film 30 so as to cover the wiring layers 32 to 36 by the CVD method. Then, a silicon nitride film 40 is formed on the silicon oxide film 38 by a plasma CVD method. The stack of the silicon oxide film 38 and the silicon nitride film 40 is used as a passivation (surface protection) film.

  In the above-described example, the hydrogen annealing process is performed before forming the passivation film. However, the hydrogen annealing process may be performed after forming the passivation film. In this case, the silicon nitride film 40 for passivation is formed thin (for example, 5 to 20 nm) so that hydrogen in the processing atmosphere can pass through during the hydrogen annealing process. The passivation silicon nitride film 40 is formed by a plasma CVD method and acts as a hydrogen supply source during the hydrogen annealing process. For this reason, the hydrogen from the silicon nitride film 40 also contributes to the reduction of the interface state in the channel portion of the transistor T, and the process damage can be recovered more sufficiently.

  FIG. 7 shows a modification of the IC of FIG. In FIG. 7, the same parts as those in FIG.

  The example of FIG. 7 is characterized in that a laminated film 27 is formed flat on the interlayer insulating film 16 instead of the silicon oxide film 26 in FIG. That is, the silicon oxide film 30 is formed without the silicon nitride film 28 of FIG. The laminated film 27 is formed by stacking a silicon nitride film 27a, a silicon oxide film 27b, and an SOG film 27c in order from the bottom.

  The silicon nitride film 27a is formed so as to cover the channel portion of the transistor T by plasma CVD processing, patterning processing, or the like in the same manner as the silicon nitride film 28 described above. The wiring layer is formed at a distance of about 1.0 μm from the end of each wiring layer such as 18. The silicon oxide film 27b is formed to cover the insulating film 16, the silicon nitride film 27a, and the wiring layers 18 to 24 by the CVD method. The SOG film 27c is formed into a flat shape by a spin coating method or the like, and then made into a glass shape or a ceramic shape by heat treatment.

  After the stacked film 27 is formed, connection holes 30a and 30b are formed in the interlayer insulating film formed by stacking the stacked film 27 and the silicon oxide film 30 in the same manner as described above with reference to FIG. Then, wiring layers 32 to 36 are formed on the silicon oxide film 30 in the same manner as described above with reference to FIG. Thereafter, a hydrogen annealing process is performed in the same manner as described above with reference to FIG.

  Next, a silicon oxide film 38 and a silicon nitride film 40 are formed on the silicon oxide film 30 so as to cover the wiring layers 32 to 36 in the same manner as described above with reference to FIG. The hydrogen annealing treatment may be performed after the passivation film is formed as described above, instead of being performed before the formation of the passivation film composed of the silicon oxide film 38 and the silicon nitride film 40.

  According to the manufacturing method described above with reference to FIG. 7, since the silicon nitride film 27a serves as a hydrogen supply source in the hydrogen annealing process, it is possible to sufficiently recover the process damage. Further, since the silicon nitride film 27a is formed slightly apart from each wiring layer, the flatness of the SOG film 27c is improved, and the flatness of the interlayer insulating film formed by stacking the stacked film 27 and the silicon oxide film 30 is improved. To do.

It is sectional drawing which shows the process until well contact region formation in the manufacturing method of MOS type IC which concerns on one Embodiment of this invention. FIG. 2 is a cross-sectional view showing an interlayer insulating film forming step and a wiring forming step following the step of FIG. 1. FIG. 3 is a cross-sectional view showing a silicon oxide film forming step and a silicon nitride film forming step following the step of FIG. 2. FIG. 4 is a cross-sectional view showing a silicon oxide film formation step and a wiring formation step following the step of FIG. 3. FIG. 5 is a cross-sectional view showing a silicon oxide film formation step and a silicon nitride film formation step following the step of FIG. 4. FIG. 5 is a plan view showing an electrode arrangement and a silicon nitride film arrangement in the structure of FIG. 4. FIG. 6 is a cross-sectional view showing a MOS type IC according to a modification of the IC of FIG. 5. It is sectional drawing which shows the conventional MOS type | mold IC.

Explanation of symbols

  10: Semiconductor substrate, 12: P-type well region, 14: Field insulating film, 16, 31: Interlayer insulating film, 18-22, 32-36: Wiring layer, 26, 26b, 30, 38: Silicon oxide film, 27 : Laminated film, 27a, 28, 40: silicon nitride film, 27c: SOG film, T: MOS transistor.

Claims (4)

Forming a MOS transistor on one main surface of the semiconductor substrate;
Forming an insulating film covering one main surface of the semiconductor substrate and the MOS transistor;
A silicon nitride layer is deposited on the insulating film by plasma CVD, and a part of the silicon nitride layer covers the channel portion of the MOS transistor and remains smaller than the element hole of the MOS transistor in plan view. Forming a silicon nitride film consisting of the remaining portion of the silicon nitride layer by removing so as to
A laminated layer of a titanium layer and a wiring material layer is formed on the insulating film and the silicon nitride film via another insulating film, and a part of the laminated layer covers the channel portion of the MOS transistor and is viewed in plan view. Forming a wiring layer consisting of the remaining portion of the stack by removing the MOS transistor so as to remain over the element hole ;
After forming the wiring layer, performing a heat treatment for recovering process damage to the MOS transistor in a hydrogen-containing atmosphere ;
Forming a passivation film comprising a stack of a silicon oxide film and a silicon nitride film covering the wiring layer;
Of a semiconductor device including 2. The semiconductor according to claim 1, wherein in the step of forming the wiring layer, the wiring layer having a width of 5 μm or more is formed as the wiring layer by removing the stacked layer so that a part thereof remains with a width of 5 μm or more. How to make the device. 3. The method of manufacturing a semiconductor device according to claim 1 , wherein the step of forming the passivation film is performed before the step of performing a heat treatment for recovering the process damage on the MOS transistor in the hydrogen-containing atmosphere . The silicon nitride film is formed in a region without a wiring layer corresponding to a connection hole of the MOS transistor, and the other insulating film is formed flat by a spin coating method. Item 4. A method for manufacturing a semiconductor device according to Item 1.

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