JP4193060B2 - Electronic circuit - Google Patents

Electronic circuit Download PDF

Info

Publication number
JP4193060B2
JP4193060B2 JP2004167694A JP2004167694A JP4193060B2 JP 4193060 B2 JP4193060 B2 JP 4193060B2 JP 2004167694 A JP2004167694 A JP 2004167694A JP 2004167694 A JP2004167694 A JP 2004167694A JP 4193060 B2 JP4193060 B2 JP 4193060B2
Authority
JP
Japan
Prior art keywords
coil
transmission
signal
circuit
transmission coil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2004167694A
Other languages
Japanese (ja)
Other versions
JP2005348264A (en
Inventor
忠広 黒田
大介 溝口
典之 三浦
貴康 櫻井
博 川口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Keio University
Original Assignee
Keio University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Keio University filed Critical Keio University
Priority to JP2004167694A priority Critical patent/JP4193060B2/en
Priority to PCT/JP2005/010029 priority patent/WO2005119932A1/en
Priority to TW094118381A priority patent/TW200603557A/en
Publication of JP2005348264A publication Critical patent/JP2005348264A/en
Application granted granted Critical
Publication of JP4193060B2 publication Critical patent/JP4193060B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H04B5/75

Description

本発明は、IC(Integrated Circuit)ベアチップやPCB(プリント基板)などの基板間の通信を好適に行うことができる電子回路に関する。   The present invention relates to an electronic circuit that can suitably perform communication between substrates such as an IC (Integrated Circuit) bare chip and a PCB (printed circuit board).

本発明者らは、チップを3次元実装し、チップ間を誘導性結合により電気的に接続する方法によって、LSI(Large Scale Integration)の1パッケージに複数のベアチップを封入するシステムインパッケージ(SiP)を実現することを提案している(特許文献1参照)。   The present inventors have system-in-package (SiP) in which a plurality of bare chips are encapsulated in one LSI (Large Scale Integration) package by a method in which chips are three-dimensionally mounted and the chips are electrically connected by inductive coupling. Has been proposed (see Patent Document 1).

図3は、先願発明の電子回路の構成を示す図である。この電子回路は、第1〜第3LSIチップ31a〜31cから成る。LSIチップが3層にスタックされ、3チップにまたがるバスを形成する例である。すなわち、3者間(3つのLSIチップ間)で互いに通信可能な1つの通信チャネルを構成している。第1〜第3LSIチップ31a〜31cが縦に積まれ、各チップは接着剤で互いに固定されている。第1〜第3LSIチップ31a〜31c上には、それぞれ、送信に用いる第1〜第3送信コイル33a〜33cが配線により形成され、また、それぞれ、受信に用いる第1〜第3受信コイル35a〜35cが配線により形成される。これら3ペアの送受信コイル33、35の開口の中心が一致するように、第1〜第3LSIチップ31a〜31c上で配置されている。これにより、3ペアの送受信コイル33、35は誘導性結合を形成し、通信が可能となる。第1〜第3送信コイル33a〜33cにはそれぞれ第1〜第3送信回路32a〜32cが接続され、第1〜第3受信コイル35a〜35cにはそれぞれ第1〜第3受信回路34a〜34cが接続される。送受信コイル33、35は、プロセス技術の多層配線を利用し、通信に許される面積内で、3次元的に1回巻き以上のコイルとして実装される。送受信コイル33、35には、通信に最適な形状が存在し、最適なまき数、開口、線幅をとる必要がある。一般的に、送信コイル33が受信コイル35より小さい。   FIG. 3 is a diagram showing the configuration of the electronic circuit of the invention of the prior application. The electronic circuit includes first to third LSI chips 31a to 31c. In this example, LSI chips are stacked in three layers to form a bus extending over three chips. That is, one communication channel that can communicate with each other between three parties (three LSI chips) is configured. First to third LSI chips 31a to 31c are stacked vertically, and the respective chips are fixed to each other with an adhesive. On the first to third LSI chips 31a to 31c, first to third transmission coils 33a to 33c used for transmission are formed by wiring, respectively, and first to third reception coils 35a to 35c used for reception are respectively formed. 35c is formed by wiring. These three pairs of transmitting and receiving coils 33 and 35 are arranged on the first to third LSI chips 31a to 31c so that the centers of the openings coincide with each other. As a result, the three pairs of transmitting and receiving coils 33 and 35 form inductive coupling, and communication is possible. The first to third transmission circuits 33a to 33c are connected to the first to third transmission circuits 32a to 32c, respectively, and the first to third reception coils 35a to 35c are respectively connected to the first to third reception circuits 34a to 34c. Is connected. The transmission / reception coils 33 and 35 are mounted as three-dimensional or more coils in a three-dimensional manner within the area allowed for communication, utilizing multilayer wiring of process technology. The transmission / reception coils 33 and 35 have an optimum shape for communication, and it is necessary to take an optimum number of turns, openings, and line widths. Generally, the transmission coil 33 is smaller than the reception coil 35.

図4は、先願発明の電子回路に用いる送信回路の構成例を示す図である。この送信回路は、遅延バッファ41、及びトランジスタT7〜T10から成る。トランジスタT7とトランジスタT8、及び、トランジスタT9とトランジスタT10がそれぞれインバータを形成して、バッファとして機能し、送信コイル42を駆動する。入力される送信データTxdataがローからハイになると、トランジスタT7、T8で反転して送信コイル42に電流ITを流し、遅延バッファ41で遅延されて、トランジスタT9、T10で反転して送信コイル42の電流ITを止める。これにより送信コイル42に三角波形状のパルス電流を流す。送信データTxdataがハイからローになると、送信コイル42に逆極性の三角波形状のパルス電流を流す。
特願2004−037242
FIG. 4 is a diagram showing a configuration example of a transmission circuit used in the electronic circuit of the prior invention. This transmission circuit includes a delay buffer 41 and transistors T7 to T10. The transistors T7 and T8, and the transistors T9 and T10 form inverters, function as buffers, and drive the transmission coil 42. When the input transmission data Txdata goes from low to high, it is inverted by the transistors T7 and T8, the current IT is passed through the transmission coil 42, delayed by the delay buffer 41, inverted by the transistors T9 and T10, and inverted by the transmission coil 42. Stop the current IT. As a result, a triangular wave-shaped pulse current is caused to flow through the transmission coil 42. When the transmission data Txdata changes from high to low, a pulse current having a reverse triangular wave shape is caused to flow through the transmission coil 42.
Japanese Patent Application No. 2004-037242

しかし、上記の送信回路の場合には、送信コイル42が送信していない間、すなわち、送信コイル42に電流が流れていない間は、送信コイル42の両端は短絡状態にあるため、同じ通信チャネルを構成している他の送信コイルが信号を送信している間は、送信コイル42内の誘導電流が磁界の変化に干渉して、受信信号を減衰させてしまう。   However, in the case of the transmission circuit described above, both ends of the transmission coil 42 are in a short circuit state while the transmission coil 42 is not transmitting, that is, while no current is flowing through the transmission coil 42. While the other transmission coils constituting the signal are transmitting signals, the induced current in the transmission coil 42 interferes with the change in the magnetic field and attenuates the received signal.

本発明は、上記問題点に鑑み、基板間通信を誘導性結合によって実現する場合に、信号を送信していない送信コイルによる通信への干渉を抑えることができる電子回路を提供することを目的とする。   The present invention has been made in view of the above problems, and an object thereof is to provide an electronic circuit capable of suppressing interference to communication by a transmission coil not transmitting a signal when inter-board communication is realized by inductive coupling. To do.

本発明の電子回路は、基板上の配線により形成され信号を受信する第1受信コイルと、該第1受信コイルから信号を入力する第1受信回路と、基板上の配線により前記第1受信コイルと誘導結合する位置に形成され信号を送信する第1送信コイルと、該第1送信コイルに信号を出力し前記第1受信回路が信号を受信している間は第1送信コイルを開放する第1送信回路とを有する第1基板と、基板上の配線により前記第1送信コイルと対応する位置に形成されて通信チャネルを構成し信号を受信する第2受信コイルと、該第2受信コイルから信号を入力する第2受信回路と、基板上の配線により前記第2受信コイルと誘導結合し前記第1受信コイルと対応する位置に形成されて第1受信コイルとで通信チャネルを構成し信号を送信する第2送信コイルと、該第2送信コイルに信号を出力し前記第2受信回路が信号を受信している間は第2送信コイルを開放する第2送信回路とを有する第2基板とを備える。 An electronic circuit of the present invention includes a first receiving coil that is formed by wiring on a substrate and receives a signal, a first receiving circuit that inputs a signal from the first receiving coil, and the first receiving coil by wiring on the substrate. A first transmission coil that is formed at a position where it is inductively coupled to the first transmission coil, and outputs a signal to the first transmission coil and opens the first transmission coil while the first reception circuit is receiving the signal . A first substrate having one transmitter circuit, a second receiver coil that is formed at a position corresponding to the first transmitter coil by wiring on the substrate to form a communication channel and receive a signal; and from the second receiver coil A second receiving circuit for inputting a signal and an inductive coupling with the second receiving coil by a wiring on the substrate are formed at a position corresponding to the first receiving coil to form a communication channel between the first receiving coil and the signal. Second transmission to send During a coil, wherein the output signals to the second transmission coil second receiver circuit is receiving a signal and a second substrate having a second transmission circuit for opening the second transmission coil.

本発明によれば、基板間通信を誘導性結合によって実現する場合に、送信コイルを開放する時を簡易に判断して、信号を送信していない送信コイルによる通信への干渉を抑えることができる。
According to the present invention, when inter-board communication is realized by inductive coupling, it is possible to easily determine when to open the transmission coil and to suppress interference to communication by the transmission coil not transmitting a signal. .

以下、添付図面を参照しながら本発明を実施するための最良の形態について詳細に説明する。   The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings.

図1は、本発明の実施例1による電子回路における送信回路の構成を示す図ある。この送信回路は、遅延バッファ11、NOT12、NAND13、NOR14、及びトランジスタT1〜T4から成り、送信コイル15を駆動する。遅延バッファ11、及びトランジスタT1〜T4は、従来技術として説明した遅延バッファ41、及びトランジスタT7〜T10と同一のものであり詳しい説明は省略する。信号Tx/バー(Rx)は、この通信チャネルに関してこのチップが送信していない時には受信しているものであることを想定して、送信している時にはハイ、受信している時にはローである信号である。これによりこのチップが送信していない時(この実施例1では、すなわち、受信している時)には、信号Tx/バー(Rx)はローであるので、NOT12の出力はハイ、NAND13の出力はハイ、NOR14の出力はローとなって、トランジスタT3、T4をオフにして、送信コイル15を開放状態にする。このため、この送信コイル15が磁界の変化に干渉して、受信信号を減衰させることはない。   1 is a diagram illustrating a configuration of a transmission circuit in an electronic circuit according to a first embodiment of the present invention. This transmission circuit includes a delay buffer 11, NOT12, NAND13, NOR14, and transistors T1 to T4, and drives the transmission coil 15. The delay buffer 11 and the transistors T1 to T4 are the same as the delay buffer 41 and the transistors T7 to T10 described as the prior art, and detailed description thereof is omitted. The signal Tx / bar (Rx) is a signal that is high when transmitting and low when receiving, assuming that this chip is receiving when this chip is not transmitting for this communication channel. It is. As a result, when the chip is not transmitting (in this embodiment 1, that is, when receiving), since the signal Tx / bar (Rx) is low, the output of the NOT 12 is high and the output of the NAND 13 Is high and the output of the NOR 14 is low, turning off the transistors T3 and T4 and opening the transmission coil 15. For this reason, the transmission coil 15 does not interfere with the change of the magnetic field and does not attenuate the reception signal.

図2は、本発明の実施例2による電子回路における送信回路の構成を示す図ある。この送信回路は、NOT21、NAND22、NOR23、トランジスタT5、T6、及びコンデンサ25から成り、送信コイル24を駆動する。NOT21、NAND22、及びNOR23は、実施例1のNOT12、NAND13、及びNOR14と同一のものであり詳しい説明は省略する。コンデンサ25はMOSトランジスタの容量性を用いることで、簡易に製造することができる。送信の時、すなわち、Tx/バー(Rx)がハイである時に、入力される送信データTxdataがローからハイになると、トランジスタT5はオフからオンになると共に、トランジスタT6はオンからオフになり、送信コイル24には電流ITが流れコンデンサ25を充電する。コンデンサ25が十分に充電されると電流ITは止まり、結局、送信コイル24には三角波形状のパルス電流が流れることになる。つぎに、送信データTxdataがハイからローになると、トランジスタT5はオンからオフになると共に、トランジスタT6はオフからオンになり、送信コイル24には電流ITが逆に流れコンデンサ25を放電する。コンデンサ25が十分に放電されると電流ITは止まり、送信コイル24には逆極性の三角波形状のパルス電流が流れることになる。この実施例2の場合、逆極性のパルス電流を流すのにコンデンサ25の放電を用いていて、電源電流を用いていないので、節電ができる。また、遅延バッファ11を割愛でき、送信コイル24を駆動する2つのバッファ(T1〜T4)を1つ(T5、T6)にできるので、さらに節電ができる。また、コイルを介してコンデンサを充放電する場合の充放電電流は線形性がよいので、小さな電流で送信コイル24から大きな信号を送信することができ、この点でも節電ができる。   FIG. 2 is a diagram illustrating a configuration of a transmission circuit in an electronic circuit according to the second embodiment of the present invention. This transmission circuit includes NOT 21, NAND 22, NOR 23, transistors T 5 and T 6, and a capacitor 25, and drives the transmission coil 24. NOT21, NAND22, and NOR23 are the same as NOT12, NAND13, and NOR14 of the first embodiment, and detailed description thereof is omitted. The capacitor 25 can be easily manufactured by using the capacitance of the MOS transistor. At the time of transmission, that is, when Tx / bar (Rx) is high, when the input transmission data Txdata goes from low to high, the transistor T5 turns from off to on, and the transistor T6 turns from on to off, A current IT flows through the transmission coil 24 and charges the capacitor 25. When the capacitor 25 is fully charged, the current IT stops, and eventually, a triangular wave-shaped pulse current flows through the transmission coil 24. Next, when the transmission data Txdata goes from high to low, the transistor T5 turns from on to off and the transistor T6 turns from off to on, and the current IT flows in the transmission coil 24 in the reverse direction, discharging the capacitor 25. When the capacitor 25 is sufficiently discharged, the current IT stops and a pulse current having a triangular wave shape with a reverse polarity flows through the transmission coil 24. In the case of the second embodiment, since the discharge of the capacitor 25 is used to flow the pulse current having the reverse polarity and the power supply current is not used, power can be saved. Further, since the delay buffer 11 can be omitted and the two buffers (T1 to T4) for driving the transmission coil 24 can be made one (T5, T6), power can be further saved. In addition, since the charge / discharge current when charging / discharging the capacitor via the coil has good linearity, a large signal can be transmitted from the transmission coil 24 with a small current, and power can be saved also in this respect.

なお、本発明は上記実施例に限定されるものではない。   In addition, this invention is not limited to the said Example.

1つの通信チャネルに複数の送信コイルがある場合に、各送信コイルは他の送信コイルが送信している間は開放して、送信していない送信コイルが他の通信に干渉することを抑止することが、本発明の本質である。   When there are a plurality of transmission coils in one communication channel, each transmission coil is opened while the other transmission coil is transmitting, and a transmission coil not transmitting interferes with other communications. That is the essence of the present invention.

送信していない送信コイルを開放することにしてもよい。   You may decide to open | release the transmission coil which is not transmitting.

2チップ間通信のような2者間通信である場合には、受信中は送信コイルを開放することにしてもよい。   In the case of two-party communication such as communication between two chips, the transmission coil may be opened during reception.

3者以上の間の通信チャネルについて、その通信チャネルに関してある基板には受信コイルがなく送信コイルだけを搭載しているものがあってもよい。その場合でもその送信コイルは他の送信コイルが送信している間は開放する。   As for a communication channel between three or more parties, there may be a board on which only a transmission coil is mounted without a reception coil on a certain board related to the communication channel. Even in that case, the transmitting coil is opened while the other transmitting coil is transmitting.

本発明の実施例1による電子回路における送信回路の構成を示す図ある。It is a figure which shows the structure of the transmission circuit in the electronic circuit by Example 1 of this invention. 本発明の実施例2による電子回路における送信回路の構成を示す図ある。It is a figure which shows the structure of the transmission circuit in the electronic circuit by Example 2 of this invention. 先願発明の電子回路の構成を示す図である。It is a figure which shows the structure of the electronic circuit of prior invention. 先願発明の電子回路に用いる送信回路の構成例を示す図である。It is a figure which shows the structural example of the transmission circuit used for the electronic circuit of prior application invention.

符号の説明Explanation of symbols

11 遅延バッファ
12 NOT
13 NAND
14 NOR
15 送信コイル
21 NOT
22 NAND
23 NOR
24 送信コイル
25 コンデンサ
31 LSIチップ
32 送信回路
33 送信コイル
34 受信回路
35 受信コイル
41 遅延バッファ
42 送信コイル
T1〜T10 トランジスタ
Txdata 送信データ
11 Delay buffer 12 NOT
13 NAND
14 NOR
15 Transmitting coil 21 NOT
22 NAND
23 NOR
24 transmission coil 25 capacitor 31 LSI chip 32 transmission circuit 33 transmission coil 34 reception circuit 35 reception coil 41 delay buffer 42 transmission coils T1 to T10 transistor Txdata transmission data

Claims (1)

基板上の配線により形成され信号を受信する第1受信コイルと、該第1受信コイルから信号を入力する第1受信回路と、基板上の配線により前記第1受信コイルと誘導結合する位置に形成され信号を送信する第1送信コイルと、該第1送信コイルに信号を出力し前記第1受信回路が信号を受信している間は第1送信コイルを開放する第1送信回路とを有する第1基板と、
基板上の配線により前記第1送信コイルと対応する位置に形成されて通信チャネルを構成し信号を受信する第2受信コイルと、該第2受信コイルから信号を入力する第2受信回路と、基板上の配線により前記第2受信コイルと誘導結合し前記第1受信コイルと対応する位置に形成されて第1受信コイルとで通信チャネルを構成し信号を送信する第2送信コイルと、該第2送信コイルに信号を出力し前記第2受信回路が信号を受信している間は第2送信コイルを開放する第2送信回路とを有する第2基板と
を備えることを特徴とする電子回路。
A first receiving coil that is formed by wiring on the substrate and receives a signal, a first receiving circuit that inputs a signal from the first receiving coil, and a position that is inductively coupled to the first receiving coil by wiring on the substrate A first transmission coil that transmits a signal and a first transmission circuit that outputs a signal to the first transmission coil and opens the first transmission coil while the first reception circuit receives the signal . 1 substrate,
A second receiving coil which is formed at a position corresponding to the first transmitting coil by wiring on the substrate to form a communication channel and receives a signal; a second receiving circuit which inputs a signal from the second receiving coil; and a substrate A second transmitter coil that is inductively coupled to the second receiver coil by the upper wiring, is formed at a position corresponding to the first receiver coil, forms a communication channel with the first receiver coil, and transmits a signal; An electronic circuit comprising: a second substrate having a second transmission circuit that outputs a signal to a transmission coil and opens the second transmission coil while the second reception circuit receives the signal .
JP2004167694A 2004-06-04 2004-06-04 Electronic circuit Active JP4193060B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004167694A JP4193060B2 (en) 2004-06-04 2004-06-04 Electronic circuit
PCT/JP2005/010029 WO2005119932A1 (en) 2004-06-04 2005-06-01 Electronic circuit
TW094118381A TW200603557A (en) 2004-06-04 2005-06-03 Electronic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004167694A JP4193060B2 (en) 2004-06-04 2004-06-04 Electronic circuit

Publications (2)

Publication Number Publication Date
JP2005348264A JP2005348264A (en) 2005-12-15
JP4193060B2 true JP4193060B2 (en) 2008-12-10

Family

ID=35463171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004167694A Active JP4193060B2 (en) 2004-06-04 2004-06-04 Electronic circuit

Country Status (3)

Country Link
JP (1) JP4193060B2 (en)
TW (1) TW200603557A (en)
WO (1) WO2005119932A1 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173986A (en) 2004-12-15 2006-06-29 Keio Gijuku Electronic circuit
JP4784773B2 (en) * 2005-09-02 2011-10-05 日本電気株式会社 Transmission method, interface circuit, semiconductor device, semiconductor package, semiconductor module, and memory module
CN101377808B (en) * 2007-08-31 2012-02-29 天时电子股份有限公司 Radio frequency identification positioning apparatus and method
US9053950B2 (en) 2007-11-26 2015-06-09 Keio University Electronic circuit
JP5600237B2 (en) 2008-02-02 2014-10-01 学校法人慶應義塾 Integrated circuit
JP5475962B2 (en) 2008-04-28 2014-04-16 学校法人慶應義塾 Electronic circuit
JP5252486B2 (en) 2008-05-14 2013-07-31 学校法人慶應義塾 Inductor element, integrated circuit device, and three-dimensional mounting circuit device
JP5671200B2 (en) 2008-06-03 2015-02-18 学校法人慶應義塾 Electronic circuit
JP4982778B2 (en) 2008-07-04 2012-07-25 学校法人慶應義塾 Electronic circuit equipment
JP5325495B2 (en) 2008-08-12 2013-10-23 学校法人慶應義塾 Semiconductor device and manufacturing method thereof
JP5433199B2 (en) 2008-10-21 2014-03-05 学校法人慶應義塾 Electronic circuit
JP5326088B2 (en) 2008-10-21 2013-10-30 学校法人慶應義塾 Electronic circuit and communication function inspection method
JP5283075B2 (en) * 2008-12-26 2013-09-04 学校法人慶應義塾 Electronic circuit
JP5395458B2 (en) 2009-02-25 2014-01-22 学校法人慶應義塾 Inductor element and integrated circuit device
JP5374246B2 (en) 2009-06-12 2013-12-25 学校法人慶應義塾 Sealed semiconductor recording medium and sealed semiconductor recording device
JP5635759B2 (en) 2009-10-15 2014-12-03 学校法人慶應義塾 Multilayer semiconductor integrated circuit device
JP5750031B2 (en) 2010-11-19 2015-07-15 株式会社半導体エネルギー研究所 Electronic circuit and semiconductor device
JP2016139985A (en) 2015-01-28 2016-08-04 株式会社東芝 Transmission circuit, reception circuit, and communication system
JP6495671B2 (en) 2015-01-28 2019-04-03 東芝メモリ株式会社 Transmission circuit and communication system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08149054A (en) * 1994-11-25 1996-06-07 Japan Aviation Electron Ind Ltd Non-contact connector, signal transmitting and receiving method using the connector, and device performing the method
JPH09171541A (en) * 1995-12-19 1997-06-30 Tokimec Inc Communication equipment

Also Published As

Publication number Publication date
TWI365531B (en) 2012-06-01
WO2005119932A1 (en) 2005-12-15
TW200603557A (en) 2006-01-16
JP2005348264A (en) 2005-12-15

Similar Documents

Publication Publication Date Title
JP4193060B2 (en) Electronic circuit
WO2006013835A1 (en) Electronic circuit
JP4131544B2 (en) Electronic circuit
US7546106B2 (en) Electronic circuit
JP5671200B2 (en) Electronic circuit
US8648614B2 (en) Electronic circuit testing apparatus
JP4124365B2 (en) Electronic circuit
US20090233546A1 (en) Transmission method, interface circuit, semiconductor device, semiconductor package, semiconductor module and memory module
JP2006173415A (en) Electronic circuit
JP5475962B2 (en) Electronic circuit
JP2006324525A (en) Signal transfer method
US6014037A (en) Method and component arrangement for enhancing signal integrity
JP5436997B2 (en) Integrated circuit
JP2006325031A (en) Signal transport unit and method of transporting signal
JP5616813B2 (en) Electronic circuit
CN108376549B (en) Semiconductor device with a plurality of transistors
JP2020039041A (en) Communication circuit and control method of the same
KR20110012405A (en) Through silicon via type semiconductor integrated circuit
JPH1056135A (en) Semiconductor integrated circuit device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070402

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20080125

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20080313

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080326

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080523

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080827

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080909

R150 Certificate of patent or registration of utility model

Ref document number: 4193060

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111003

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111003

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121003

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131003

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250