JP2006324525A - Signal transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simply structured signal transfer method which can be used for a signal tranfer between chips and which securely transfers a pulse signal. <P>SOLUTION: A first signal is transmitted by applying a pulse voltage to a transmitting side inductor 3. A receiving side inductor 7 receives the first signal to output the received signal with an electromagnetic induction, and creates a level shift signal by adding the predetermined voltage to the received signal. An NMOSFET 28 is driven by the level shift signal, and a charged electric charge is emitted from a drain electrode of the NMOSFET 28 to output a transition signal showing the transition of the potential of the drain electrode to 0V as a second signal. This transfers a radio signal without a clock. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal transmission method, and more particularly to a signal transmission method for transmitting a signal using two inductor elements.

  In general, as a semiconductor integrated circuit becomes finer and more highly integrated, peripheral circuits are taken into the IC chip one after another and the IC chip itself tends to have higher performance. Furthermore, in order to reduce the size and increase the speed, it is required to integrate a comprehensive system into one package. One way to meet this requirement is to build a complete system on a single IC chip.

However, when a comprehensive system is constructed with a large-scale IC and the system is built in one semiconductor chip, the yield is greatly reduced in the previous process in the semiconductor device manufacturing process. Therefore, it is difficult to realize such a semiconductor chip from an economical viewpoint. Therefore, as another method for accommodating a comprehensive system in a small package, a multi-chip module (MCM) technology, a three-dimensional IC technology, and the like have been considered (for example, Patent Documents 1 and 2). .
JP-A-6-291250 JP-A-11-330350

  However, in the method of manufacturing a three-dimensional IC by stacking chips as described in Patent Document 1, a plurality of IC chips on which pads for inter-chip connection electrodes are formed are overlapped to connect the IC chips to each other. In order to connect by electrodes, it is necessary to have high-precision alignment between chips and an electrode formation technique that penetrates both sides of a chip having a large aspect ratio during mounting. Furthermore, since the inter-chip connection electrodes are formed, the chip interval cannot be increased, and it is difficult to dissipate the internal chip. In the technique described in Patent Document 2, the side surfaces of a plurality of chips are bonded together with an adhesive, and electrical connection between the chips is performed by wire bonding. An MCM is created using this technique. In some cases, there are significant restrictions on the arrangement of elements and connection terminals on the chip, and various MCMs cannot be created freely.

  The present invention has been made in view of such points, and an object of the present invention is to provide a signal transmission method that can be used for signal transmission between chips with a simple structure and can reliably transmit a pulse signal. It is in.

  The signal transmission method of the present invention is a signal transmission method in which the second inductor element receives the first signal transmitted from the first inductor element and outputs it as the second signal, and applies a pulse voltage to the first inductor element. A step in which the first inductor element transmits a first signal; a step in which the second inductor element receives the first signal and outputs a reception signal by electromagnetic induction; and a predetermined voltage applied to the reception signal. To a level shift signal, driving the first switching element having the predetermined voltage as a threshold voltage by the level shift signal, and driving the first switching element to the first switching element. And outputting a transition signal in which the charged charge is released and the potential transitions to 0 V as the second signal. By performing signal transmission in this way, the first signal is output as the second signal after a certain delay time by wireless transmission.

  Preferably, the first inductor element and the second inductor element have substantially the same inductance and self-resonant frequency.

  The pulse width T of the pulse voltage is preferably expressed by 1 / (4f) ≦ T ≦ 3 / (4f), where f is the self-resonance frequency of the first inductor element and the second inductor element.

  In a preferred embodiment, the output step includes a sub-step of delaying the transition signal for a predetermined time, and further, driving a second switching element with the transition signal delayed for the predetermined time; and the second switching Charging the first switching element by driving the element.

  Preferably, the method further includes a step of driving the third switching element by the transition signal to short-circuit the second inductor element.

  A leakage current compensation circuit is connected to the first switching element, and the leakage current compensation circuit prevents a voltage from decreasing in the first switching element due to leakage when the first switching element is not driven. It is preferable.

  In a preferred embodiment, the input first NRZ signal is converted into a pulse signal and transmitted by the first inductor element, and the second signal received and output by the second inductor element is converted into a second NRZ signal. When the rising signal of the first NRZ signal is received before the pulse voltage applying step, the first pulse voltage is generated, and when the falling signal is received, the second pulse voltage is generated. And when the second signal corresponding to the first pulse voltage is output, it is converted to an output of a predetermined voltage other than 0, and the second signal corresponding to the second pulse voltage is output And further converting the output to 0 and outputting the second NRZ signal.

  The first pulse voltage is preferably two continuous pulse voltages, and the second pulse voltage is preferably a single pulse.

  According to the present invention, a very simple wireless connection that does not require a clock can be realized.

  Before describing embodiments of the present invention, the background to the present invention will be described.

  From the viewpoint of cost, as a means for integrating a comprehensive system having a plurality of functions as described above into a single package, a method in which a plurality of chips are housed in a single package and the chips are connected in some way. Although considered to be advantageous, the methods of Patent Documents 1 and 2 that are currently considered have significant problems. As one of the solutions, the present invention is applied to a wireless signal transmission method for wiring connection between chips by forming a planar inductor on an IC chip to be laminated instead of an inter-chip connection electrode and electromagnetic coupling between the planar inductors. They came up with it. However, when performing wireless connection by electromagnetic coupling between inductors, a clock circuit is used to synchronize the transmitting side and the receiving side for reliable signal transmission. In this case, a new clock circuit is required. End up. Thus, a circuit that does not use a clock was conceived and the present invention was reached.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a schematic diagram showing a signal transmission device according to Embodiment 1 of the present invention. Spiral inductors 1 and 2 for interlayer wireless connection are formed on the upper and lower IC chips 101 and 102, respectively. Further, circuits for signal transmission, which will be described later, are also formed on the IC chips 101 and 102, respectively. Here, an example of a spiral inductor is shown as a planar inductor, but an inductor having another structure may be used.

  The signal transmission device of this embodiment is manufactured by forming spiral inductors 1 and 2 made of the same metal as the metal wiring in the process of forming the metal wiring among the processes of forming the electronic circuit on the semiconductor chip. The circuit of the signal transmission device including the reception circuit / transmission circuit is formed simultaneously with the electronic circuit formed on the semiconductor chip. In this way, an element (terminal) for signal transmission between chips can be formed at the same time as the electronic circuit formation, and therefore, it is not necessary to perform an extra step such as through-hole formation or protruding electrode formation, and the manufacturing cost is kept low. be able to.

  Next, FIG. 2 shows a circuit in which the spiral inductor pairs 1 and 2 are represented by equivalent circuits, and a transmission-side inductor (first inductor element) 3 represented by the equivalent circuit is switched by an NMOSFET (switching element) 4. Since the spiral inductors 1 and 2 are designed and formed in the same shape with the same material, they have the same inductor characteristics in design, and considering the processing unevenness and deviation in manufacturing, the transmitting inductor 3 It can be said that the receiving-side inductor (second inductor element) 7 has substantially the same inductance and self-resonant frequency. Here, the coupling coefficient between the transmission-side inductor 3 and the reception-side inductor 7 is denoted by k.

  When the gate electrode of the NMOSFET 4 is driven by the pulse 11 of the voltage Vin shown in FIG. 3, the current (iL) 5 flowing through the transmission-side inductor 3 and the output voltage (Vout) 6 of the reception-side inductor 7 are the waveform 12 shown in FIG. 13

  The signal of the output voltage excited in the receiving inductor 7 by the rising and falling of the drive voltage pulse 11 applied from the NMOSFET 4 to the transmitting inductor 3 is the waveform 13 described above. The output voltage waveform 13 is composed of two damped vibration waveforms 14 and 15. The vibration waveform 15 that excites the falling edge of the drive voltage pulse 11 has a larger amplitude than the vibration waveform 14 that excites the rising edge. This is because the characteristics of the transmission-side inductor 3 and the reception-side inductor 7 are different due to the ON conductance of the NMOSFET 4 at the time of rising. That is, at the time of start-up, the total inductance on the transmission side is a combination of the ON conductance of the NMOSFET 4 and the inductance of the transmission-side inductor 3. On the other hand, at the time of falling, the NMOSFET 4 is cut off, so that the characteristics of the transmission-side inductor 3 and the reception-side inductor 7 become equal, and the amplitude of the vibration waveform 15 increases due to the resonance phenomenon between the inductors 3 and 7.

  Thus, for exciting the transmission-side inductor 3, it is important to turn off the NMOSFET 4 after excitation. Although the excitation method using the NMOSFET 4 has been described this time, it is important to open the transmission inductor 3 after excitation in other excitation methods. That is, when a drive pulse is applied to the transmission inductor 3, the switching element such as the NMOSFET 4 rises by causing the current supply line to the transmission inductor 3 to conduct (pulse generation), and the switching element cuts off the current supply line. To make it fall off (end of pulse). By doing so, the characteristics of the transmission-side inductor 3 and the reception-side inductor 7 become equal, the amplitude of the vibration waveform 15 increases due to the resonance phenomenon between the inductors 3 and 7, and the voltage value applied to the transmission-side inductor 3 is Even if it is small, a signal with a large amplitude appears in the receiving-side inductor 7.

  The relationship between the rise time and the fall time of the output voltage waveform 13 of the reception-side inductor 7 described above is generally applicable regardless of the pulse waveform of the drive voltage, but the transmission-side inductor 3 and the reception-side inductor. In order to ensure signal transmission to and from 7, it is preferable to increase the amplitude of the output voltage of the receiving inductor 7. In order to increase the amplitude of the vibration waveform on the output side, the inventors of the present application from the lower left pulse waveform in FIG. 3, the vibration waveform 14 excited at the rising edge of the driving pulse and the vibration waveform excited at the falling edge of the driving pulse. I came up with the idea of superimposing 15. That is, when the transmission-side inductor 3 is excited by the drive pulse 16 having a narrow pulse width shown in FIG. 3, the transmission-side inductor 7 transmits the first pulse-like signal shown in the middle right of FIG. When the receiving inductor 7 receives this first signal, the vibration waveform 14 excited at the rising edge of the drive pulse by electromagnetic induction overlaps with the vibration waveform 15 excited at the falling edge of the drive pulse, so that a larger vibration waveform 17 can be realized. It is.

  Here, the pulse width T of the drive pulse 16 having a narrow pulse width is set according to the self-resonant frequency f of the transmission-side and reception-side inductors 3 and 7, as T = 1 / (2f). If the pulse width T is T = 1 / (2f), the amplitude of the output voltage waveform is extremely high, which is very preferable. However, the pulse width T does not have to be exactly 1 / (2f), and ± 50 of 1 / (2f). %, That is, 1 / (4f) ≦ T ≦ 3 / (4f), the amplitude of the vibration waveform on the output side increases. Within ± 25%, that is, 3 / (8f) ≦ T ≦ 5 / (8f), it is preferable because the amplitude becomes sufficiently large for practical use.

  From the viewpoint of power consumption, the pulse width T is preferably set to 1 / (4f) to 3 / (4f). This will be described below.

  The power consumption in the coupling circuit by the spiral inductor pairs 3 and 7 shown in FIG. 2 is mainly determined by the current iL flowing through the transmission-side inductor 3.

  In the signal transmission device according to this embodiment in which the amplitude of the vibration waveform on the output side is increased by controlling the pulse width of the drive pulse, the maximum value of the current flowing through the inductor 3 on the transmission side can be set relatively small. In addition, since the time during which current flows through the transmission-side inductor 3 can be shortened by the driving pulse 16 having a narrow pulse width shown in FIG. 3, the power consumption in the coupling circuit using the spiral inductor pair shown in FIG. That is, when a predetermined amount of output voltage (= voltage amplitude) is to be output from the receiving inductor 7 on the output side, the power consumption is the most when the circuit configuration of this embodiment is used and the drive pulse width of this embodiment is used. Can be reduced.

  Next, FIG. 4 shows an asynchronous transmission / reception circuit according to the present embodiment which does not require a clock and is based on the above-described coupling circuit using a pulse-driven inductor pair. In general, a clock is required to synchronize a transmission signal and a reception signal, and a clock recovery circuit such as a nonlinear extraction circuit or a PLL circuit is formed on the reception side for this purpose. Thus, the pulse signal group on the transmission side can be faithfully reproduced and output on the reception side with the time interval between the pulse signals without a clock and clock recovery circuit.

  In the asynchronous transmission / reception circuit of this embodiment shown in FIG. 4, the transmission and reception spiral inductors 3 and 7 described above are used. The waveform of each node voltage during operation is shown in FIG. 5, and the signal transmission method according to this embodiment will be described below.

  First, the gate electrode of the NMOSFET 21 is driven by the pulse 22 generated from the pulse generation circuit 36. By this driving, a pulse voltage is applied to the transmission-side spiral inductor 3. The pulse width T of this pulse voltage is T = 1 / (2f), and is set in accordance with the self-resonant frequency f of the transmission side and reception side inductors 3 and 7.

  When the pulse voltage is applied, the transmission-side spiral inductor 3 transmits a first signal equivalent to the waveform in the middle right of FIG. Waveform 23 is excited.

  This is level-shifted by applying a predetermined voltage Vbn (here, 0.4 V) by the capacitor 24, the resistor 25 and the bias circuit 26 to obtain a vibration waveform signal (level shift signal) 27 having a center potential of Vbn. The level shift signal 27 is applied to the gate electrode of an NMOSFET (first switching element) 28 to drive the NMOSFET 28.

  The drain electrode of the NMOSFET 28 is a terminal that is dynamically charged and discharged, and is charged to Vdd when driven. The threshold voltage for driving the NMOSFET 28 is Vbn. Accordingly, when the level shift signal 27 is applied to the gate electrode of the NMOSFET 28 and a signal larger than Vbn is applied, the NMOSFET 28 becomes conductive, so that the drain electrode of the NMOSFET 28 is discharged and transitions to the 0V potential.

  The transition pulse (transition signal) 34 to 0V is delayed by a predetermined time by a delay circuit 29 constituted by two inverters. Then, this delayed transition signal (delayed transition signal) 31 drives the gate electrode of the PMOSFET 30. Since the PMOSFET 30 is thus conducted, the drain electrode of the NMOSFET 28 is again charged to Vdd. This step can be called a self-precharge step. By this self-precharge, the NMOSFET 28 can again issue the transition signal 34 when the next transmission pulse 22 is sent. On the other hand, the delayed transition signal 31 is inverted by an inverter to become a reception signal 32 (second signal).

  As described above, the transmission pulse 22 is reproduced as the second signal 32. The second signal 32 is input to the reproduction circuit 37. As can be seen from FIG. 5, a pulse group having the same shape as the transmission pulse 22 is output as the second signal 32. The transmission pulse 22 and the second signal 32 have the same pulse shape and the same interval between pulses. Note that the delay time between the transmission pulse 22 and the second signal 32 is 0.4 ns.

  Furthermore, in the present embodiment, the NMOSFET (third switching element) 33 shown in FIG. 4 reproduces the received signal so that the attenuation rate of the received vibration waveform is increased in order to suppress intersymbol interference, and then receives the received inductor. 7 is short-circuited to release the retained electromagnetic energy. In other words, since the reception signal 32 drives the NMOSFET 33 to short-circuit the reception inductor 7, the portion of the vibration waveform 23 excited by the reception inductor 7 that oscillates while pulling down is quickly attenuated. Disappear. This prevents malfunction.

  Further, the leakage current of the NMOSFET (first switching element) 28 in FIG. 4 gradually discharges the dynamic node charge on the drain electrode of the NMOSFET 28 and finally outputs an error pulse. Therefore, a leakage current compensation circuit shown in FIG. 6 is provided and connected to the NMOSFET (first switching element) 28.

  In the leakage current compensation circuit shown in FIG. 6, the leakage current and the signal pulse are distinguished by low-pass filters formed by PMOSFETs 41 and 42 that function as resistors and capacitors, respectively. The operation of this leakage current compensation circuit will be described below.

  The voltage at the terminal 43 level-shifted by the source follower constituted by the NMOSFETs 44 and 45 is applied to the gate electrode of the PMOSFET 46. When the potential of the terminal 43 connected to the drain electrode of the NMOSFET (first switching element) 28 drops due to the discharge due to the leakage current of the NMOSFET (first switching element) 28, the potential of the gate electrode of the PMOSFET 46 drops accordingly. Therefore, the gate-source voltage of the PMOSFET 46 increases, the compensation current that is the drain current of the PMOSFET 46 increases, and the voltage drop at the terminal 43 due to the leakage current is suppressed. On the other hand, the change in the potential of the terminal 43 due to the signal pulse is as high as several hundred ps, so that it is blocked by the low-pass filter composed of the PMOSFETs 41 and 42, and does not cause the potential change of the gate electrode of the PMOSFET 46. The signal pulse detection operation is not affected by the current.

  Furthermore, transmission of the NRZ signal is enabled by the pulse generation circuit 63 and the logic level reproduction circuit 37 shown in FIG. FIG. 7A shows a block diagram of the pulse generation circuit, and FIG. 7B shows a block diagram of the logic level reproduction circuit.

  In the pulse generation circuit shown in FIG. 7A, the outputs of the first, second, and third NAND circuits 51, 52, and 53 are inputs to the fourth NAND circuit 54, and the output of the fourth NAND circuit 54 is the output of the pulse generation circuit. It has become. The first NAND circuit 51 receives an NRZ signal on the transmission side and a signal obtained by delaying the NRZ signal by three NOT circuits. Since the signals delayed by the three NOT circuits are ON / OFF reversed from the original NRZ signal, the first NAND circuit 51 outputs an inversion pulse only when the NRZ signal rises, and its pulse width is 3 This is the delay time of one NOT circuit. On the other hand, in the second NAND circuit 52, a signal S1 obtained by delaying a signal obtained by delaying the original NRZ signal by three NOT circuits by a first delay circuit 55 including an even number of NOT circuits, and the signal S1 by three NOTs. The signal S2 delayed by the circuit is input. Since the signal S1 is ON / OFF opposite to that of the original NRZ signal, and the signal S2 is ON / OFF the same as the original NRZ signal, the second NAND circuit 52 is only at the falling edge of the NRZ signal. Output inversion pulse. The third NAND circuit 53 receives a signal S3 obtained by delaying the signal S1 by one NOT circuit and a signal S4 obtained by delaying the signal S3 by three NOT circuits. Therefore, like the first NAND circuit 51, the third NAND circuit 53 outputs an inversion pulse only when the NRZ signal rises, and this output is the amount of delay from the output of the first NAND circuit 51 by the first delay circuit 55 and one NOT circuit. Delayed by time.

  From the fourth NAND circuit to which the outputs of the above three NAND circuits 51, 52, 53 are input, two continuous pulses are output when the NRZ signal rises, and one pulse is output when the NRZ signal falls. . The separation time between two continuous pulses is a time corresponding to a delay by the first delay circuit 55 and one NOT circuit.

  Next, in the logic level reproduction circuit shown in FIG. 7B, the first and second RS flip-flop circuits 61 and 62 and the second delay circuit 63 reproduce the NRZ signal from the pulse output from the pulse generation circuit. The second RS flip-flop circuit 62 on the lower side of FIG. 7B is connected so as to be reset after a certain time delay generated by the second delay circuit 63 by its own holding signal Q1, so that it is in a steady state. Then, it is in a reset state. In this state, when the pulse of the reception signal 32 is input as VRX, the first RS flip-flop circuit 61 is reset by this pulse, and the second RS flip-flop circuit 62 is set at the same time. Then, after a delay of a certain time, the second RS flip-flop circuit 62 is reset by the holding signal Q1, but if another pulse is input before this reset, the first RS flip-flop circuit 61 is set. That is, when a continuous pulse within a certain time is input, the first RS flip-flop circuit 61 is set, but when it is a single pulse, the first RS flip-flop circuit 61 remains reset. Therefore, the NRZ signal is reproduced and output by this operation.

  As described above with reference to FIG. 8, the pulse generation circuit generates two continuous pulses when the input NRZ signal rises. At this time, the interval time between successive pulses needs to be shorter than the fixed time delay generated by the second delay circuit 63. However, if this interval is smaller than 1 / f, two pulses overlap each other, so that the pulses must be separated by 1 / f or more. On the other hand, only one pulse is generated at the fall. In addition, the logic level reproduction circuit sets the output logic level to High and sends only one pulse when two pulses continue from the pulse sent through the coupling circuit formed by the previous pulse-driven inductor pair. If possible, set the output logic level to Low. An NRZ signal having the same shape as that inputted according to the logic level of the output can be outputted.

  In the present embodiment, high-accuracy chip-to-chip alignment such as through vias is not required, and the cost for chip formation can be reduced. In addition, since the distance between chips can be set larger than the connection between chips using through vias, heat generated from the electronic circuit can be easily released. And since signal transmission is performed using the resonance characteristic between inductor elements, transmission power can be suppressed low. Furthermore, since the asynchronous receiving circuit does not use a clock, it can be considered functionally as a buffer with direction control, and can be easily used as a logic block at the time of logic design of an electronic circuit on a semiconductor chip.

(Embodiment 2)
The second embodiment is a signal transmission device represented by the circuit shown in FIG. In the present embodiment, the transmitter and receiver circuits of FIG. 4 are merged, one inductor is connected, and a PMOSFET 50 serving as a switch is added as shown in FIG. 9 to transmit one circuit. Alternatively, a transceiver that can be used by switching to reception is easily configured. More specifically, by applying a Low signal to the gate electrode of the PMOSFET 50 to turn on the PMOSFET 50, turning on the pulse generator circuit (Pulse Generator), and applying a Low signal to the bias circuit, the MMOSFET of the NMOSFET is turned off. This circuit becomes a transmission circuit. Conversely, the PMOSFET 50 is turned off, a high signal is applied to the pulse generator (Pulse Generator) to turn on the M1 of the NMOSFET, and a high signal is applied to the bias circuit to drive the M3 of the NMOSFET. It becomes a receiving circuit.

  In this case, as shown in FIG. 10, the coupling circuit by the pulse-driven inductor pair including the pulse generation circuit and the logic level reproduction circuit can be considered as a buffer with direction control functionally. Can be used easily.

  By adopting such a transceiver structure, the number of inductors can be reduced to half and the number of circuit elements for transmission and reception can be reduced, so that the entire apparatus can be reduced in size and the manufacturing cost can be reduced.

(Embodiment 3)
In the third embodiment, the transmitting and receiving inductors are 0.18 μm thick, the wiring width is 20 μm, the wiring spacing is 1.5 μm, the number of turns is 2, the number of layers is 4, and the square is 200 μm on each side. Separated by The rest is the same as in the second embodiment.

  When a signal transmission test was performed at a data rate of 1.0 Gbps with a multichip module equipped with the signal transmission device of this embodiment, it was found that the device had a performance of 0.95 mW / 1.0 Gbps / ch.

(Other embodiments)
The above-described embodiments are examples of the present invention, and the present invention is not limited to these examples.

  The transmission circuit, the reception circuit, the transceiver circuit, the leakage current compensation circuit, the pulse generation circuit, the logic level reproduction circuit, and the like may have a circuit configuration different from the above-described circuit configuration.

  The transmission of the NRZ signal is not limited to a configuration in which two continuous pulses are generated when the input NRZ signal rises and a single pulse is generated when the input NRZ signal falls. A single pulse may be generated at the rising edge, and two continuous pulses may be generated at the falling edge, or three or more pulses may be generated.

  Three or more semiconductor chips may be stacked. In this case, for example, if there are three semiconductor chips of X, Y, and Z, they are used for signal transmission between the inductors β and XZ used for signal transmission between the inductor α and YZ used for signal transmission between XY. If the inductance with the inductor γ is set to be different from each other, signal transmission can be reliably performed without causing interference between the respective signal transmissions. In this case, inductors α, β and γ having three different inductances are formed on one semiconductor chip.

  The signal transmission device of the above embodiment is preferably used for a multi-chip module in which a plurality of semiconductor chips are stacked and collected as one package. It is preferable that the signal transmission method of the above embodiment is used for signal transmission between different semiconductor chips in one package.

  As described above, since the signal transmission method according to the present invention is an asynchronous transmission / reception method that does not require a clock, it can be used for signal transmission between chips in the MCM and the like.

1 is a schematic perspective view of a signal transmission device according to Embodiment 1. FIG. It is a circuit diagram which shows the equivalent circuit of the inductor pair of transmission and reception. 3 shows a drive pulse waveform, inductor current waveform, and output voltage waveform in the circuit of FIG. FIG. 3 is a circuit diagram illustrating a part of the signal transmission device according to the first embodiment. FIG. 5 is a waveform of each node potential explaining a drive pulse waveform, a received voltage waveform, and a self-precharge function of the circuit of FIG. 4. It is a circuit diagram which shows a leakage current compensation circuit. (A) is a block diagram showing a pulse generation circuit, and (b) is a block diagram showing a logic level reproduction circuit. It is an operation waveform of a pulse generation circuit and a logic level reproduction circuit. FIG. 6 is a circuit diagram illustrating a part of a signal transmission device according to a second embodiment. It is a conceptual diagram of the buffer with direction control which is functionally equivalent to the mutual coupling circuit between IC chips using the inductor pair of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Spiral inductor formed on the upper IC chip 2 Spiral inductor 3 formed on the lower IC chip Transmitting side inductor (first inductor element)
4 Transistors for pulse drive (switching elements)
5 Current flowing in the transmission-side inductor 6 Output voltage of the reception-side inductor 7 Reception-side inductor (second inductor element)
11 Waveform of drive pulse 12 Waveform of current flowing through transmission side inductor 13 Waveform of output voltage of reception side inductor 14 Damping vibration 15 rising of driving pulse 11 is excited Damping vibration 16 falling of driving pulse 11 is excited 16 Pulse width Narrow drive pulse (pulse voltage)
17 Overlaid vibration waveform 21 Transistor for pulse drive (switching element)
22 Drive Pulse Waveform 23 Vibration Waveform Excited by Receiving Inductor 24 Level Shift Capacitor 25 Level Shift Resistor 26 Bias Circuit 27 Level Shifted Vibration Waveform 28 Received Vibration Waveform Detection Transistor 29 Delay Two inverters 30 constituting the circuit Transistor 31 for performing precharge Pulse 32 for starting precharge Regenerated pulse waveform 33 Transistor 36 for suppressing intersymbol interference Pulse generation circuit 37 Logic level reproduction circuit 41 Operates as a resistor The transistor 42 that operates as a capacitor 43 The input / output terminal 44 of the compensation circuit The source follower driver 45 The load transistor 46 of the source follower 50 The transistor 50 that generates the compensation current 50 Switch

Claims (8)

A signal transmission method in which the second inductor element receives the first signal transmitted from the first inductor element and outputs the first signal as a second signal,
Applying a pulse voltage to the first inductor element;
The first inductor element transmitting a first signal;
The second inductor element receives the first signal and outputs a received signal by electromagnetic induction;
Adding a predetermined voltage to the received signal to obtain a level shift signal;
Driving the first switching element having the predetermined voltage as a threshold voltage by the level shift signal;
Outputting a transition signal in which the electric charge charged in the first switching element is released by driving the first switching element and the potential transitions to 0 V is output as the second signal.   The signal transmission method according to claim 1, wherein the first inductor element and the second inductor element have substantially the same inductance and self-resonant frequency.   The pulse width T of the pulse voltage is represented by 1 / (4f) ≦ T ≦ 3 / (4f), where f is a self-resonance frequency of the first inductor element and the second inductor element. The signal transmission method described in 1. The output step includes a sub-step of delaying the transition signal for a predetermined time,
further,
Driving the second switching element with the transition signal delayed for the predetermined time;
The signal transmission method according to claim 1, further comprising: charging the first switching element by driving the second switching element.   5. The signal transmission method according to claim 1, further comprising a step of driving a third switching element by the transition signal to short-circuit the second inductor element. 6. A leakage current compensation circuit is connected to the first switching element,
6. The signal transmission method according to claim 1, wherein the leakage current compensation circuit prevents a voltage from being lowered in the first switching element due to leakage when the first switching element is not driven. 6. . The input first NRZ signal is converted into a pulse signal and transmitted by the first inductor element, and the second signal received and output by the second inductor element is converted into a second NRZ signal and output. 6. The signal transmission method according to any one of 6,
Generating a first pulse voltage when receiving the rising signal of the first NRZ signal and generating a second pulse voltage when receiving the falling signal before the pulse voltage applying step;
When the second signal corresponding to the first pulse voltage is output, it is converted to an output of a predetermined voltage other than 0, and when the second signal corresponding to the second pulse voltage is output, it is output. Converting the signal to 0 and outputting the second NRZ signal.   The signal transmission method according to claim 7, wherein the first pulse voltage is two continuous pulse voltages, and the second pulse voltage is a single pulse.

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