CN103368535B - Receiver and the semiconductor integrated circuit with the receiver - Google Patents

Receiver and the semiconductor integrated circuit with the receiver Download PDF

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Publication number
CN103368535B
CN103368535B CN201310118543.9A CN201310118543A CN103368535B CN 103368535 B CN103368535 B CN 103368535B CN 201310118543 A CN201310118543 A CN 201310118543A CN 103368535 B CN103368535 B CN 103368535B
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China
Prior art keywords
pulse
circuit
testing result
result
determines
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CN201310118543.9A
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CN103368535A (en
Inventor
武田晃
武田晃一
归山隼
归山隼一
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority claimed from JP2013074132A external-priority patent/JP6043225B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Manipulation Of Pulses (AREA)

Abstract

The present invention relates to receiver and the semiconductor integrated circuit with the receiver, the receiver determines that circuit and negative pulse determine circuit including positive pulse.Positive pulse determines that exporting the first L level during period of the circuit at the time of pulse signal with positive amplitude is detected and between being not detected by the time of the pulse signal with positive amplitude is also not detected by the pulse signal with negative amplitude determines result, and exports the first H level if the pulse signal with positive amplitude is detected during other periods and determine result.Negative pulse determines that period of the circuit at the time of pulse signal with positive amplitude is detected and between being not detected by the time of the pulse signal with positive amplitude is also not detected by the pulse signal with negative amplitude exports the second L level and determine result, and exports the second H level if the pulse signal with negative amplitude is detected during other periods and determine result.

Description

Receiver and the semiconductor integrated circuit with the receiver
The cross reference of related application
By on March 30th, 2012 is submitting including specification, drawing and description are made a summary by way of integrally quoting The disclosure of 2012-082323 Japanese patent applications inside is hereby incorporated by.
Technical field
The present invention relates to a kind of receiver and the semiconductor integrated circuit with the receiver.More specifically, it is of the invention It is related to a kind of for example by the receiver of AC coupling elements reception signal and the semiconductor integrated circuit with such receiver.
Background technology
When wiring is used for directly transmitting signal between the different multiple semiconductor chips of supply voltage, semiconductor chip Damage or signal bust this may occur due to the voltage difference in the DC voltage component of signal waiting for transmission.Therefore, when Will between the different semiconductor chip of supply voltage transmit signal when, between semiconductor chip couple AC coupling elements so as to Only transmit AC signals.Capacitor or transformer may be used as AC coupling elements.
Certain passes through the method for transmitting signals of AC coupling elements according to the amplitude direction indicated number of pulse signal waiting for transmission According to the direction of transformation.For example transmission with positive amplitude pulse signal when, find data level change from L to H (on Rise).When transmission has the pulse signal of negative amplitude, it is found that the level of data changes (decline) from H to L.This signal is transmitted Although method is compared with other method for transmitting signals can reduce current drain and circuit area, have the following problems.
The situation that wherein transformer is used as AC coupling elements is illustrated below.When transmission has the pulse signal of positive amplitude, This method for transmitting signals makes electric current temporarily flow to the other end from one end of primary coil.Then the electric current in primary coil Change and positive voltage potential (pulse signal with positive amplitude) is generated in secondary coil.On the other hand, there is negative amplitude in transmission Pulse signal when, this method for transmitting signals makes electric current temporarily flow to the one end from the other end of primary coil.Then basis Electric current in primary coil changes generates negative zeta potential (pulse signal with negative amplitude) in secondary coil.
If when transmission has the pulse signal of positive amplitude, the electric current for flowing to the other end from one end of primary coil is hindered Only, then electric current in primary coil changes generates negative zeta potential (back pulse with negative amplitude) in secondary coil.Class As, if when transmission has the pulse signal of negative amplitude, the electric current for flowing to the one end from the other end of primary coil is hindered Only, then electric current in primary coil changes generates positive voltage potential (back pulse with positive amplitude) in secondary coil.Cause This, receiver can obtain such back pulse as the normal burst signal in the direction for indicating data transformation.In other words, connect The logical value of data may be erroneously determined that by receiving device.
In " A2.5kV isolation35kV/us CMR250Mbps0.13mA/Mbps digital isolator in Standard CMOS with an on-chip small transformer " (S.Kaeriyama, S.Uchida, M.Furumiya, M.Okada, M.Mizuno, 2010Symposium on VLSI Circuits, Technical Digest Of Technical Papers, 2010, the 197-198 pages) disclosed in a kind of solution to above mentioned problem.
In " A2.5kV isolation35kV/us CMR250Mbps0.13mA/Mbps digital isolator in Standard CMOS with an on-chip small transformer " (S.Kaeriyama, S.Uchida, M.Furumiya, M.Okada, M.Mizuno, 2010Symposium on VLSI Circuits, Technical Digest Of Technical Papers, 2010, the 197-198 pages) disclosed in configuration by the amplitude of the pulse signal with positive amplitude It is to represent the direction that data change with which pulse signal is the amplitude of the pulse signal with negative amplitude be compared to determine Normal burst signal.Disclosed correlation technique is configured to prevent from erroneously determining that patrolling for data using such in the above documents Collect value.
Other are relevant disclosed in -236696 Japanese laid-open patent with 2011-142175 of Publication No. Hei8 (1996) Technology.
A kind of integrated circuit disclosed in Publication No. Hei8 (1996) -236696 Japanese laid-open patent, which has, to be passed through Vertical stacking IC chip is come the three-dimensional structure formulated.This integrated circuit is configured so that coupling inductance M is used for providing A part and another portion of the vertical integrated circuit in another chip layer Lnx for vertical integrated circuit in one chip layer Ln / based on inductance signal transmission.
A kind of configuration disclosed in Publication No. 2011-142175 Japanese laid-open patent includes AC coupling elements and connect Receive device.AC coupling elements generate the reception signal V2 that its voltage changes and changed according to input transmission signal V1 electric current.Receive Device passes through to being believed based on integral operation is performed to the numerical value for the differential order for receiving signal V2 from transmission signal V1 according to reception Number V2 reproduces transmission signal V1.
The content of the invention
However, in " A2.5kV isolation35kV/us CMR250Mbps0.13mA/Mbps digital Isolator in standard CMOS with an on-chip small transformer " (S.Kaeriyama, S.Uchida, M.Furumiya, M.Okada, M.Mizuno, 2010Symposium on VLSI Circuits, Technical Digest of Technical Papers, 2010, the 197-198 pages) disclosed in configuration need to compare for analog voltage Special circuit (be specially passive element).Therefore it is unable to the increase of suppression circuit size.The other problemses and sheet of correlation technique The novel feature of invention will be neutralized from accompanying drawing and will be made apparent from from being detailed description below.
Including positive pulse determine that circuit and negative pulse determine the reception of circuit there is provided a kind of according to an aspect of the present invention Device.Positive pulse determines that circuit exports the first of the first logical value during the first period and determines result, and the first period was in detection Have at the time of to pulse signal with negative amplitude with being not detected by the pulse signal with positive amplitude and being also not detected by Time interval between at the time of the pulse signal of negative amplitude, and if detected during different from the period of the first period Pulse signal with positive amplitude, then export the second logical value first determines result.Negative pulse determines circuit in the second period Period exports second of a logical value in the first and second logical values and determines result, and the second period is being detected with just With being not detected by the pulse signal with positive amplitude and being also not detected by with negative amplitude at the time of the pulse signal of amplitude Time interval between at the time of pulse signal, and if detected during different from the period of the second period with negative width The pulse signal of degree, then export another logical value in the first and second logical values second determines result.
Including positive pulse determine that circuit and negative pulse determine the reception of circuit there is provided a kind of according to another aspect of the present invention Device.Positive pulse determines that circuit exports the first logical value during the scheduled time slot after detecting the pulse signal with negative amplitude First determine result, and if detecting the pulse signal with positive amplitude during the period different from scheduled time slot, Then export the second logical value first determines result.Negative pulse determines circuit after the pulse signal with positive amplitude is detected Scheduled time slot during export second of a logical value in the first and second logical values and determine result, and if in difference The pulse signal with negative amplitude is detected during the period of scheduled time slot, then exports another in the first and second logical values The second of logical value determines result.
Aforementioned aspect of the present invention makes it possible to provide one kind with small scale in circuitry configuration and can use high precision Property receive data receiver.
Brief description of the drawings
Fig. 1 is block diagram of the diagram according to the semiconductor integrated circuit of the first embodiment of the present invention；
Fig. 2 is the schematic diagram for being shown to illustrate how to implement the semiconductor integrated circuit according to first embodiment；
Fig. 3 is that diagram determines that circuit and negative pulse determine the state transition diagram of circuit according to the positive pulse of first embodiment；
Fig. 4 A are timing diagram of the diagram according to the operation of the receiver of first embodiment；
Fig. 4 B are timing diagram of the diagram according to the operation of the receiver of first embodiment；
Fig. 5 is that diagram determines that circuit and negative pulse determine that the exemplary of circuit is matched somebody with somebody in detail according to the positive pulse of first embodiment The figure put；
Fig. 6 is timing diagram of the diagram according to the operation of the receiver of first embodiment；
Fig. 7 is the block diagram for illustrating semiconductor integrated circuit according to the second embodiment of the present invention；
Fig. 8 is block diagram of the diagram according to the modification of the semiconductor integrated circuit of second embodiment；
Fig. 9 is that diagram determines that circuit and negative pulse determine the state transition diagram of circuit according to the positive pulse of second embodiment；
Figure 10 A are timing diagram of the diagram according to the operation of the receiver of second embodiment；
Figure 10 B are timing diagram of the diagram according to the operation of the receiver of second embodiment；
Figure 11 is figure of the diagram according to the example concrete configuration of the delay circuit of second embodiment；
Figure 12 is figure of the diagram according to the exemplary detailed configuration of the delay circuit of second embodiment；
Figure 13 is timing diagram of the diagram according to the operation of the receiver of second embodiment；
Figure 14 is the block diagram for illustrating semiconductor integrated circuit according to the third embodiment of the invention；
Figure 15 is that diagram determines that circuit and negative pulse determine the exemplary detailed of circuit according to the positive pulse of 3rd embodiment The figure of configuration；
Figure 16 is that diagram determines that circuit and negative pulse determine the state transition diagram of circuit according to the positive pulse of 3rd embodiment；
Figure 17 A are timing diagram of the diagram according to the operation of the receiver of 3rd embodiment；
Figure 17 B are timing diagram of the diagram according to the operation of the receiver of 3rd embodiment；
Figure 18 is the schematic diagram for being shown to illustrate how implementation according to first to 3rd embodiment semiconductor integrated circuit；
Figure 19 is the schematic diagram for being shown to illustrate how implementation according to first to 3rd embodiment semiconductor integrated circuit；
Figure 20 is the schematic diagram for being shown to illustrate how implementation according to first to 3rd embodiment semiconductor integrated circuit；
Figure 21 is the schematic diagram for being shown to illustrate how implementation according to first to 3rd embodiment semiconductor integrated circuit；
Figure 22 is the schematic diagram for being shown to illustrate how implementation according to first to 3rd embodiment semiconductor integrated circuit；
Figure 23 is the schematic diagram for being shown to illustrate how implementation according to first to 3rd embodiment semiconductor integrated circuit；
Figure 24 is the schematic diagram for being shown to illustrate how implementation according to first to 3rd embodiment semiconductor integrated circuit；
Figure 25 is the schematic diagram for being shown to illustrate how implementation according to first to 3rd embodiment semiconductor integrated circuit；
Figure 26 is the figure for the phase inverter that diagram is applied to according to first to 3rd embodiment semiconductor integrated circuit；And And
Figure 27 is the operation for the phase inverter that diagram is applied to according to first to 3rd embodiment semiconductor integrated circuit Timing diagram.
Embodiment
It is now described with reference to the drawings embodiments of the invention.Because accompanying drawing is simplified, so they, which are not applied, comes narrow Free burial ground for the destitute interprets the technical scope of each embodiment.Identical element is indicated with identical reference, and will not redundantly be retouched State.
In to being described below of embodiment, if needed for convenience, will in multiple chapters and sections or embodiment with Separated mode provides the description of this invention, but if do not expressed specifically, then they are not orthogonal but therein One be other in which partly or completely modification, using, describe in detail or the such relation of supplementary notes.Also exist In embodiment as described below, as precedents number (including number of packages, numerical value, quantity, scope etc.), if unit number is not specific Express or be not limited to specific number in addition to the wherein number is obviously limited to situation about specifically counting in principle.It is more than or less than The number of number is specified to be also suitable.
In addition, in the embodiment being described below, their part (including operating procedure etc.) is if not specific bright Show or except wherein part in principle substantially in addition to indispensable situation it is always not indispensable.Similarly, exist In embodiment as described below, when mentioning the shape of part, position relationship between them etc., if specific bright Show or except wherein it is contemplated that including them in addition to substantially excluding the substantially situation of approximate and similar shape etc. in principle. This is equally applicable to foregoing units number (including number of packages, numerical value, quantity, scope etc.).
First embodiment
Fig. 1 is the block diagram for the exemplary configuration for illustrating semiconductor integrated circuit 1, and the semiconductor integrated circuit is included according to this The receiver of the first embodiment of invention is to form isolator.Detect with just or negative amplitude pulse signal and really Determine it after normal burst signal, to be not detected by the pulse with positive amplitude at it according to the receiver of first embodiment and believe Number, be also not detected by before the pulse signal with negative amplitude, it is normal burst signal not know any pulse signal.Therefore, The noise component(s) (including back pulse) generated in signal VR is received can be eliminated according to the receiver of the present embodiment.This causes have (reproduction) data may be received with high accuracy.In this example, correlation technique is different from according to the receiver of the present embodiment Do not include being used for the special circuit that compares of analog voltage and determine that circuit and negative pulse determine that circuit carries out numeral with positive pulse Control.It therefore, it can accurately receive data by using small scale in circuitry configuration.
Semiconductor integrated circuit 1 shown in Fig. 1 at least includes transmitter Tx1, receiver Rx1 and AC coupling element ISO1.
Transmitter Tx1 is formed on semiconductor chip CHP0.Semiconductor chip CHP0 is by belonging to the first power-supply system First power supply (supply voltage VDD0, ground voltage GND0) drives.
AC coupling elements ISO1 and receiver Rx1 is formed on semiconductor chip CHP1.Semiconductor chip CHP1 is by belonging to Driven in the second source (supply voltage VDD1, ground voltage GND) 1 of second source system.
It is that the inductor with primary coil L11 and secondary coil L12 (is hereinafter referred to as transformation in AC coupling elements ISO1 Device) it is such assume under provide and be described below.However, the present embodiment is not limited to using such AC coupling elements.For example, electric capacity Property element (hereinafter referred to as capacitor) or GMR element may be used as AC coupling elements ISO1.In other words, the present embodiment is not It is only applicable to use inductor as AC coupling elements ISO1 inductor isolator and suitable for based on capacitive element The isolator being capacitively coupled and the GMR isolators based on GMR element.
Transformer is to convert the electrical signal to magnetic force by using primary coil and be converted into magnetic force with secondary coil L12 Electric signal to transmit the AC coupling elements of AC signals from primary coil L11 to secondary coil L12.
Fig. 2 is to illustrate the figure for how implementing semiconductor integrated circuit 1 as an example.Fig. 2 mainly illustrates how assembling transmission Device Tx1, receiver Rx1 and the AC coupling elements ISO1 set between transmitter Tx1 and receiver Rx1.
Reference picture 2, the assembling semiconductor chips CHP0 and semiconductor chip CHP1 in semiconductor packages PKG0.Semiconductor core Piece CHP0 and semiconductor chip CHP1 each have pad Pd.Semiconductor chip CHP0 and semiconductor chip CHP1 pad Pd Semiconductor packages PKG0 multiple lead terminals (outside terminal) T is coupled to by being bonded wiring (not shown).
As shown in Figure 2, transmitter Tx1 is formed on semiconductor chip CHP0.The shape on semiconductor chip CHP1 Into receiver Rx1 and configuration AC coupling elements ISO1 primary and secondary coil L11, L12.In addition, in semiconductor chip The pad for the output that will be coupled into transmitter Tx1 is formed on CHP0, and is formed and will coupled on semiconductor chip CHP1 To the pad at primary coil L11 two ends.Transmitter Tx1 is coupled in semiconductor chip by these pads and bonding wiring W The primary coil L11 formed on CHP1.
Shown example in fig. 2, the first wiring layers of vertical stacking neutralize the second wiring layers in single semiconductor chip It is middle to form primary coil L11 and secondary coil L12 respectively.
Fig. 1 is returned, the exemplary configuration of semiconductor integrated circuit 1 is will be described in.Transmitter Tx1 is grasped from the first power supply Make, first power supply belongs to the first power-supply system.On the other hand, receiver Rx1 is operated from second source, and the second source belongs to Second source system.
Transmitter Tx1 output transmission signals, the transmission signal is with the transformation with the transmission data VIN from outside supply The corresponding amplitude in direction direction pulse signal.For example, changing in transmission data VIN from L level to H level (rising) When, transmitter Tx1 temporarily flows to the other end by making electric current I1 from primary coil L11 one end to export the arteries and veins with positive amplitude Rush signal (transmission signal).On the other hand, when transmission data VIN changes (decline) from H level to L level, transmitter Tx1 leads to Crossing makes electric current I1 temporarily flow to the one end from the primary coil L11 other end to export the (transmission of the pulse signal with negative amplitude Signal).
AC coupling elements ISO1 transmits the transmission signal exported from transmitter Tx1 to receiver Rx1 as reception signal VR. More specifically, AC coupling elements ISO1, which is operated, to generate the electricity having with flowing to primary coil L11 in secondary coil L12 The reception signal VR of the corresponding voltage level of change of stream.
For example, transmitter Tx1 export with positive amplitude pulse signal (transmission signal) when, that is, electric current I1 from When primary coil L11 one end temporarily flows to the other end, the positive voltage potential (arteries and veins with positive amplitude is generated in secondary coil L12 Rush signal) as reception signal VR.On the other hand, the pulse signal (transmission signal) with negative amplitude is exported in transmitter Tx1 When, that is, when electric current I1 temporarily flows to the one end from the primary coil L11 other end, negative electricity is generated in secondary coil L12 Kinetic potential (pulse signal with negative amplitude) is used as reception signal VR.
Signal Rx1 is received to reproduce transmission data VIN according to the reception signal VR from AC coupling elements ISO1 and export Transmission data VIN is used as output data VO.
(receiver Rx1 exemplary configuration)
Receiver Rx1 includes pulse-detecting circuit 11, positive pulse and determines that circuit (positive pulse determining section) 12, negative pulse are determined Circuit (negative pulse determining section) 13 and latch cicuit (data generating section) 14.
Pulse-detecting circuit 11 detects that the pulse signal with positive amplitude generated in secondary coil L12 (receives signal VR) and the pulse signal with negative amplitude (receive signal VR) and export the reception signal VR detected and tied respectively as detection Really (the first testing result) d1 and it is used as testing result (the second testing result) d2.For example, receiving signal VR voltage level When being not less than high-level threshold voltage Vth+, pulse-detecting circuit 11 detects the pulse signal with positive amplitude, and in inspection H level testing result d1 is exported during measuring such pulse signal.On the other hand, it is less than in the voltage level for receiving signal VR During high-level threshold voltage Vth+, pulse-detecting circuit 11 is not detected by the pulse signal with positive amplitude and exports L level Testing result d1.Similarly, when the voltage level for receiving signal VR is not higher than low level threshold voltage vt h-, pulse detection electricity Road 11 detects the pulse signal with negative amplitude, and the output H level detection knot during such pulse signal is detected Fruit d2.On the other hand, when the voltage level for receiving signal VR is higher than low level threshold voltage vt h-, pulse-detecting circuit 11 is not Detect the pulse signal with negative amplitude and export L level testing result d2.
Positive pulse determines that circuit 12 determines to have according to testing result d1, d2 exported from pulse-detecting circuit 11 and indicates to pass The pulse signal for the positive amplitude that transmission of data VIN rises, and export determination result to determine result (first determines result) s1.More Specifically, positive pulse determines circuit 12 at the time of testing result d2 is in H level and testing result d1, d2 is in L level Output L level (the first logical value) determines result (first determines result) s1 during period (the first period) between moment, and And if during other periods testing result d1 in H level if export H level (the second logical value) determine result (first determine As a result) s1.
Negative pulse determines that circuit 13 determines to have according to testing result d1, d2 exported from pulse-detecting circuit 11 and indicates to pass The pulse signal for the negative amplitude that transmission of data VIN declines, and export determination result to determine result (second determines result) s2.More Specifically, negative pulse determines circuit 13 at the time of testing result d1 is in H level and testing result d1, d2 is in L level Output L level (the first logical value) determines result (second determines result) s2 during period (the second period) between moment, and And if during other periods testing result d2 in H level if export H level (the second logical value) determine result (second determine As a result) s2.
Positive and negative pulse determines that circuit 12,13 is configured with same circuits.However, positive pulse determines that circuit 12 uses input Terminal IN1 is to receive testing result d1 supply, using input terminal IN2 to receive testing result d2 supply.And use Lead-out terminal OUT determines result s1 to export.Meanwhile, negative pulse determines circuit 13 using input terminal IN1 to receive detection knot Fruit d2 supply, using input terminal IN2 to receive testing result d1 supply, and it is true to export using lead-out terminal OUT Determine result s2.
(positive pulse determines that circuit 12 and negative pulse determine the state transition diagram of circuit 13)
The basic operation that positive pulse determines circuit 12 is described now with reference to Fig. 3.Fig. 3 is that positive pulse determines that circuit 12 is (negative Pulse determines circuit 13) state transition diagram.Symbol " IN1 ", " IN2 " and " OUT " in Fig. 3 represents that positive pulse determines electricity respectively The input terminal and lead-out terminal on road 12 (negative pulse determines circuit 13).It is assumed here that IN1=d1 and IN2=d2 but also vacation If OUT=s1.
First, in stable state (ST1), positive pulse determines that circuit 12 exports L electricity according to L level testing result d1, d2 It is flat to determine result s1.
For example, if testing result d1 rises in stable state, positive pulse determines that the output H level of circuit 12 determines knot Fruit s1 (T12).Positive pulse determines circuit 12 and then changed from stable state (ST1) to H output states (ST2).
Meanwhile, if testing result d2 rises in stable state, positive pulse determines circuit 12, and continuously output L level is true Determine result s1 (T13).Positive pulse determines circuit 12 and then changed from stable state (ST1) to lock-out state (ST3).
Then, if testing result d1 is held in H level in H output states, positive pulse determines no matter circuit 12 is examined It is that all continuous output H level of rising or decline determines result s1 (T22) to survey result d2.In this example, positive pulse is determined Circuit 12 is maintained in H output states (ST2).
Meanwhile, if in H output states, testing result d2 is in L level and testing result d1 declines, then positive pulse is true Determine the output of circuit 12 L level and determine result s1 (T21).Positive pulse determines circuit 12 and then from H output states (ST2) to stablizing shape State (ST1) changes.
If in H output states, testing result d2 determines electricity in H level and testing result d1 declines, then positive pulse The output L level of road 12 determines result s1 (T23).Positive pulse determines circuit 12 and then from H output states (ST2) to lock-out state (ST3) change.
Then, if in lock-out state, one of testing result d1, d2 determines that circuit 12 is continuous in H level, then positive pulse Output L level determine result s1 (T33) but regardless of another testing result in testing result d1, d2 transformation (rise or under Drop).In this example, positive pulse determines that circuit 12 is held in lock-out state (ST3).
Meanwhile, if in lock-out state, one of testing result d1, d2 is another in L level and testing result d1, d2 One testing result declines, then positive pulse determines that continuously output L level determines result s1 (T31) to circuit 12.Positive pulse determines circuit Then 12 change from lock-out state (ST3) to stable state (ST1).
The basic operation that negative pulse determines circuit 13 is described now with reference to Fig. 3.It is assumed here that IN1=d2, and IN2= D1, and it is also supposed that OUT=s2.
First, in stable state (ST1), negative pulse determines that circuit 13 exports L electricity according to L level testing result d1, d2 Flat (the first logical value) determines result s2.
For example, if testing result d2 rises in stable state, negative pulse determines that circuit 13 exports H level (second Logical value) determine result s2 (T12).Negative pulse determines circuit 13 and then turned from stable state (ST1) to H output states (ST2) Become.
Meanwhile, if testing result d1 rises in stable state, negative pulse determines circuit 13, and continuously output L level is true Determine result s2 (T13).Negative pulse determines circuit 13 and then changed from stable state (ST1) to lock-out state (ST3).
Then, if testing result d2 is held in H level in H output states, negative pulse determines that circuit 13 is continuous defeated Go out H level and determine transformations (rise or decline) of the result s2 (T22) but regardless of testing result d1.In this example, arteries and veins is born Punching determines that circuit 13 is held in H output states (ST2).
Meanwhile, if in H output states, testing result d1 is in L level and testing result d2 declines, then negative pulse is true Determine the output of circuit 13 L level and determine result s2 (T21).Negative pulse determines circuit 13 and then from H output states (ST2) to stablizing shape State (ST1) changes.
In H output states, if testing result d1 is in H level and testing result d2 declines, negative pulse determines electricity The output L level of road 13 determines result s2 (T23).Negative pulse determines circuit 13 and then from H output states (ST2) to lock-out state (ST3) change.
Then, in lock-out state, if one of testing result d1, d2 is in H level, negative pulse determines that circuit 13 is continuous Output L level determine result s2 (T33) but regardless of another testing result in testing result d1, d2 transformation (rise or under Drop).In this example, negative pulse determines that circuit 13 is held in lock-out state (ST3).
Meanwhile, in lock-out state, if one of testing result d1, d2 is another in L level and testing result d1, d2 One testing result declines, then negative pulse determines that continuously output L level determines result s2 (T31) to circuit 13.Negative pulse determines circuit Then 13 change from lock-out state (ST3) to stable state (ST1).
Fig. 1 is returned to, latch cicuit 14 determines the determination result s1 and true from negative pulse that circuit 12 is exported according to from positive pulse The determination result s2 for determining the output of circuit 13 exports output data (data) VO.
Latch cicuit 14 is so-called SR latch cicuits.Latch cicuit 14 determines knot using the sub- S of set input to receive Fruit s1 supply, using the sub- R of the RESET input to receive determination result s2 supply, and uses lead-out terminal Q to export Data VO is exported.
(timing diagram)
Receiver Rx1 operation is described now with reference to Fig. 4 A.Fig. 4 A be illustrate receiver Rx1 exemplary operation when Sequence figure.Not only AC couplings can be used as when transformer is used as AC coupling element ISO1 but also in such as capacitor or GMR element The operation described in Fig. 4 A is performed when closing element ISO1.
In original state (time t0), data VIN is in L level for transmission.Therefore, transmitter Tx1 flows to electric current I1 Primary coil L11 (the approximate 0A of I1=).Therefore, receive signal VR and be held in reference voltage.Pulse-detecting circuit 11 is not detected by Pulse signal with positive amplitude or the pulse signal with negative amplitude.Therefore, pulse-detecting circuit 11 is in these cases Export L level testing result d1, d2.Therefore, positive pulse determines that the output of circuit 12 L level determines result s1, and negative pulse is determined The output of circuit 13 L level determines result s2.In other words, positive pulse determines that circuit 12 and negative pulse determine circuit 13 stable In state (ST1).Thus, the output L level output data of latch cicuit 14 VO.
(time t1) when data VIN changes from L level to H level is being transmitted, transmitter Tx1 is by making electric current I1 from primary Coil L11 one end temporarily flows to the other end to export pulse signal (transmission signal) (time t1 to time with positive amplitude t3).Therefore, positive voltage potential corresponding with the electric current change in primary coil L11 is generated in secondary coil L12 (has positive width The pulse signal of degree) it is used as reception signal VR (A in Fig. 4 A) (time t1 to time t2).In this example, if from first The electric current I1 that level coil L11 one end flows to the other end is prevented from, then is also generated and primary coil L11 in secondary coil L12 In electric current change corresponding negative zeta potential (back pulse with negative amplitude) as reception signal VR (B in Fig. 4 A) (times T2 to time t3).
When the pulse signal with positive amplitude is not less than threshold voltage vt h+, the output H level inspection of pulse-detecting circuit 11 Survey result d1 (time t1 to time t2).In addition, when the back pulse with negative amplitude is not higher than threshold voltage vt h-, pulse inspection The output H level testing result d2 of slowdown monitoring circuit 11 (time t2 to time t3).In fact, being adjusted so that testing result d1 is in H The period of level is overlapping in the period of H level with testing result d2.Although the back pulse with negative amplitude be not always equivalent to or Less than threshold voltage vt h-, but inadvertently it is equal to or less than threshold voltage vt h- so in the back pulse with negative amplitude Hypothesis under example shown in Fig. 4 A is described.
Positive pulse determine circuit 12 at the time of at least testing result d1 rises with testing result d1 in H level at the time of it Between time interval during export H level and determine result s1 (time t1 to time t2), and decline (detection in testing result d1 As a result d2 rises) at the time of and testing result d1, d2 at the time of L level between time interval during continuous output L electricity It is flat to determine result s1 (time t2 to time t3).
More specifically, positive pulse determines that circuit 12 is operated according to Fig. 3 state transition diagram.
First, when the testing result d1 supplied to input terminal IN1 rises, positive pulse determines that circuit 12 exports H level Determine result s1 (time t1).Positive pulse determines circuit 12 and then changed from stable state (ST1) to H output states (ST2).
Then, H level is risen to simultaneously in the testing result d2 supplied to input terminal IN2 and testing result d1 decline When, positive pulse determines that the output of circuit 12 L level determines result s1 (time t2).Positive pulse determines circuit 12 and then exports shape from H State (ST2) changes to lock-out state (ST3).
Then, when testing result d2 declines, positive pulse determines that continuously output L level determines the result s1 (times to circuit 12 t3).Positive pulse determines circuit 12 and then changed from lock-out state (ST3) to stable state (ST1).
Meanwhile, negative pulse determines circuit 13 at the time of testing result d1 rises and testing result d1, d2 is in L level Continuous output L level determines result s2 (time t1 to time t3) during time interval between moment.
More specifically, negative pulse determines that circuit 13 is operated also according to Fig. 3 state transition diagram.
First, when the testing result d1 supplied to input terminal IN2 rises, negative pulse determines that circuit 13 exports L level Determine result s2 (time t1).Negative pulse determines circuit 13 and then changed from stable state (ST1) to lock-out state (ST3).
Then, when testing result d1 declines, negative pulse determines that the still continuous output L level of circuit 13 determines result S2 (time t2), because having risen and in H level to the input terminal IN1 testing result d2 supplied.In this reality In example, negative pulse determines that circuit 13 is held in lock-out state (ST3).
Then, when testing result d2 declines, negative pulse determines that continuously output L level determines the result s2 (times to circuit 13 t3).Negative pulse determines circuit 13 and then changed from lock-out state (ST3) to stable state (ST1).
Then, transmit data VIN change from H level to L level when (time t4), transmitter Tx1 by make electric current from The primary coil L11 other end temporarily flows to the one end to export pulse signal (transmission signal) (the time t4 with negative amplitude To time t6).Therefore, negative zeta potential (tool corresponding with the electric current change in primary coil L11 is generated in secondary coil L12 Have the pulse signal of negative amplitude) as reception signal VR (C in Fig. 4 A) (time t4 to time t5).In this example, such as The electric current I1 that fruit flows to the one end from the primary coil L11 other end is prevented from, then is also generated and primary in secondary coil L12 Electric current in coil changes corresponding positive voltage potential (back pulse with positive amplitude) as reception signal VR (D in Fig. 4 A) (time t5 to time t6).
When the pulse signal with negative amplitude is not higher than threshold voltage vt h-, the output H level inspection of pulse-detecting circuit 11 Survey result d2 (time t4 to time t5).In addition, when the back pulse with positive amplitude is not less than threshold voltage vt h+, pulse inspection The output H level testing result d1 of slowdown monitoring circuit 11 (time t5 to time t6).In fact, being adjusted so that testing result d2 is in H The period of level is overlapping in the period of H level with testing result d1.Although the back pulse with positive amplitude be not always equivalent to or Higher than threshold voltage vt h+, but in the back pulse with positive amplitude inadvertently at or above threshold voltage vt h+ so Hypothesis under example shown in Fig. 4 A is described.
Between positive pulse determines circuit 12 at the time of testing result d2 rises and at the time of testing result d2 is in H level Between during time interval and at the time of testing result d2 rises and at the time of testing result d1, d2 is in L level when Between interim continuously output L level determine result s1 (time t4 to time t6).
In fact, positive pulse determines that circuit 12 is operated according to Fig. 3 state transition diagram.Positive pulse will not be described and determine circuit 12 operations performed between time t4 and time t6, because it and negative pulse determine circuit 13 between time t1 and time t3 The operation of execution is identical.However, should by " testing result d1 " and " testing result d2 " be read as respectively " testing result d2 " and " testing result d1 ", and " should will determine that result s2 " is read as " determining result s1 ".
Meanwhile, negative pulse determines circuit 13 at the time of at least testing result d2 rises and testing result d2 is in H level H level is exported during time interval between moment and determines result s2 (time t4 to time t5), and under testing result d2 Drop (testing result d1 rising) at the time of and testing result d1, d2 at the time of L level between time interval during continuously Output L level determines result s2 (time t5 to time t6).
In fact, negative pulse determines that circuit 13 is operated according to Fig. 3 state transition diagram.Negative pulse will not be described and determine circuit 13 operations performed between time t4 and time t6 because it determine with positive pulse circuit 12 time t1 and time t13 it Between the operation that performs it is identical.However, should be by " testing result d1 " and " testing result d2 " is read as " testing result d2 " respectively " testing result d1 ", and " should will determine that result s1 " is read as " determining result s2 ".
Latch cicuit 14 makes output data VO with determining that result s1 rising synchronous rises (time t1), and makes output number According to VO with determining that result s2 rising synchronous declines (time t4).
As described above, receiver Rx1 by eliminate the noise component(s) generated in secondary coil L12 (including Back pulse) receive (reproduction) data with high accuracy.
Reference picture 4A, at the time of testing result d2 is in H level and at the time of testing result d1, d2 is in L level between Period (the first period) be the period between time t4 and time t6 and the period between time t2 and time t3. Testing result d1 at the time of H level and testing result d1, d2 at the time of L level between period (the second period) be Period between time t1 and time t3 and the period between time t5 and time t6.
Fig. 4 A are used for describing wherein to detect the back pulse (time t2 to time t3) with negative amplitude and detect tool There is the situation of the back pulse (time t5 to time t6) of positive amplitude.However, for example according to threshold voltage vt h+, Vth- setting and Operating condition (temperature and supply voltage), can will not detect the back pulse with negative or positive amplitude.Even in such In the case of, it is naturally that receiver Rx1 can be accurately received data.
Fig. 4 B are the timing diagrams for another operation for illustrating receiver Rx1.Fig. 4 B timing diagram is different from Fig. 4 A timing diagram It is not detect back pulse.Fig. 4 B also indicate that receiver Rx1 receives (reproduction) data with high accuracy.It will not describe in figure Another operation described in 4B timing diagram, because it is identical with the operation described in Fig. 4 A.
(positive pulse determines that circuit 12 and negative pulse determine the exemplary detailed configuration of circuit 13)
Fig. 5 is that diagram positive pulse determines that circuit 12 and negative pulse determine the figure of the exemplary detailed configuration of circuit 13.
Reference picture 5, positive pulse determines that circuit 12 includes SR latch cicuits (the first SR latch cicuits) 121 and logic AND electricity Road (the first logic AND circuit) (hereinafter referred to as AND circuit) 122.Negative pulse determines that circuit 13 includes SR latch cicuits (second SR latch cicuits) 131 and AND circuit (the second logic AND circuit) 132.
SR latch cicuits 121 using the sub- S of set input to receive testing result d2 supply from pulse-detecting circuit 11, Exported using the sub- R of the RESET input with receiving the supply of testing result d1 inversion signal from pulse-detecting circuit 11 and using Terminal Q is to export M signal (first M signal).AND circuit 122 exports testing result d1 and from SR latch cicuits 121 M signal logic AND s1 as determining result.
SR latch cicuits 131 using the sub- S of set input to receive testing result d1 supply from pulse-detecting circuit 11, Exported using the sub- R of the RESET input with receiving the supply of testing result d2 inversion signal from pulse-detecting circuit 11 and using Terminal Q is to export M signal (second M signal).AND circuit 132 exports testing result d2 and from SR latch cicuits 131 M signal logic AND s2 as determining result.
Fig. 6 be diagram receiver Rx1 positive pulse determine circuit 12 and negative pulse determine circuit 13 as illustrated in fig. 5 that The timing diagram for the operation that sample is performed when configuring.Fig. 6 timing diagram also describes the output signal of SR latch cicuits 121,131.In Fig. 6 Shown in example, each SR latch cicuits 121,131 set signal and reset signal be it is active (in H level) when export H level signal.In other words, set signal priority.Fig. 6 other parts will not be described, because it and the phase shown in Fig. 4 A Together.
Detect with just or negative amplitude pulse signal and when being defined as normal burst signal, according to this The receiver Rx1 of embodiment is being not detected by the pulse signal with positive amplitude, is also being not detected by the pulse letter with negative amplitude Before both number, it is normal burst signal not know any pulse signal.Therefore, can be with according to the receiver Rx1 of the present embodiment Eliminate the noise component(s) (including back pulse) generated in signal VR is received.This enables receiver Rx1 according to the present embodiment Enough high accuracies receive (reproduction) data.In this example, correlation technique is different from according to the receiver Rx1 of the present embodiment Determine that circuit and negative pulse determine that circuit carries out numeral without the special circuit compared for analog voltage and with positive pulse Control.This makes it possible to configure accurately to receive data using small scale in circuitry.
Second embodiment
Fig. 7 is the block diagram for the exemplary configuration for illustrating semiconductor integrated circuit 2, and the semiconductor integrated circuit is included according to this The receiver Rx2 of the second embodiment of invention is to form isolator.It will be described in second embodiment now.
Semiconductor integrated circuit 2 shown in Fig. 7 is that the former includes connecing with the difference of semiconductor integrated circuit 1 shown in Fig. 1 Device Rx2 is received to replace receiver Rx1.The configuration of the other parts of semiconductor integrated circuit 2 shown in Fig. 7 will not described, because It is identical with the configuration of the other parts of semiconductor integrated circuit 1 shown in Fig. 1.
Receiver Rx2 is that the former also includes delay circuit 15,16 with receiver Rx1 differences.Delay circuit 15,16 is exported Testing result d1 ', d2 ' are notable by the rising by the decline of testing result d1, d2 of pulse-detecting circuit 11 relative to them Postpone to obtain testing result d1 ', d2 '.Delay circuit 15 and positive pulse determine the formation positive pulse of circuit 12 determining section 22.Delay Circuit 16 and negative pulse determine the formation negative pulse of circuit 13 determining section 23.
It will include describing the present embodiment under the such hypothesis of two delay circuits 15,16 in receiver Rx2.However, delay Circuit is in a unlimited number in two.As shown in Figure 8, receiver Rx2 can include the delay circuit 15 that will be shared.
Positive pulse determines that circuit 12 determines result according to the output of testing result d1 ', d2 ' rather than testing result d1, d2.More Specifically, positive pulse determines that circuit 12, to receive testing result d1 ' supply, uses input terminal using input terminal IN1 IN2 is to receive testing result d2 ' supply and determine result s1 using lead-out terminal OUT to export.Therefore, positive pulse is determined Circuit 12 at the time of testing result d2 ' is in H level and at the time of testing result d1 ', d2 ' are in L level between period ( One period) during output L level (the first logical value) determine result (first determine result) s1, and if in other phases period Between testing result d1 ' then export H level (the second logical value) in H level and determine result (first determine result) s1.
Negative pulse determines that circuit 13 determines result according to the output of testing result d1 ', d2 ' rather than testing result d1, d2.More Specifically, negative pulse determines that circuit 13, to receive testing result d2 ' supply, uses input terminal using input terminal IN1 IN2 is to receive testing result d1 ' supply and determine result s2 using lead-out terminal OUT to export.Therefore, negative pulse is determined Circuit 13 at the time of testing result d1 ' is in H level and at the time of testing result d1 ', d2 ' are in L level between period ( Two periods) during output L level (the first logical value) determine result (second determine result) s2, and if in other phases period Between testing result d2 ' then export H level (the second logical value) in H level and determine result (second determine result) s2.
The circuit configuration of receiver Rx2 other parts will not described, because it is identical with receiver Rx1.
(state transition diagram of positive pulse determining section 22 and negative pulse determining section 23)
The basic operation of positive pulse determining section 22 is described now with reference to Fig. 9.Fig. 9 is the (negative pulse of positive pulse determining section 22 Determining section 23) state transition diagram.Symbol " IN1 ", " IN2 " and " OUT " in Fig. 9 represents that positive pulse determining section 22 is (negative respectively Pulse determining section 23) input terminal and lead-out terminal.It is assumed here that IN1=d1 and IN2=d2 and it is also supposed that OUT= s1.To put it more simply, also assume that delay circuit 15 and exported by only postponing the decline of testing result d1, d2 testing result d1 ', d2’。
First, in stable state (ST1), positive pulse determining section 22 exports L level according to L level testing result d1, d2 Determine result s1.
For example, if testing result d1 rises in stable state, the output of positive pulse determining section 22 H level determines result s1(T12).Positive pulse determining section 22 and then the transformation from stable state (ST1) to H output states (ST2).
Meanwhile, if testing result d2 rises in stable state, continuously output L level is determined positive pulse determining section 22 As a result s1 (T12).Positive pulse determining section 22 and then the transformation from stable state (ST1) to lock-out state (ST3).
Then, if testing result d1 is held in H level in H output states, no matter positive pulse determining section 22 detects As a result d2 is that all continuous output H level of rising or decline determines result s1 (T22).In this example, positive pulse determining section 22 are held in H output states (ST2).
Meanwhile, if in H output states, testing result d1 declines, then positive pulse determining section 22 is from H output states (ST2) change to delay wait state (ST4).
When passing scheduled delay after the decline from testing result d1, then positive pulse determining section 22 is waited from delay State (ST4) changes to another state.
For example, if testing result d1, d2 is in L level, testing result d1 ', d2 ' are correspondingly in L level.Cause This, the output of positive pulse determining section 22 L level determines result s1 (T41).Positive pulse determining section 22 is then from delay wait state (ST4) change to stable state (ST1).
Meanwhile, if testing result d1 or testing result d2 is in H level, testing result d1 ' or testing result d2 ' Correspondingly in H level.Therefore, the output of positive pulse determining section 22 L level determines result s1 (T43).Positive pulse determining section 22 is then Change from delay wait state (ST4) to lock-out state (ST3).
Then, if one of testing result d1, d2 in lock-out state in one of H level, testing result d1 ', d2 ' Correspondingly in H level.Therefore, continuously output L level determines result s1 but regardless of testing result d1, d2 to positive pulse determining section 22 The transformation (T33) of another testing result in (d1 ', d2 ').In this example, positive pulse determining section 22 is held in locking shape State (ST3).
Meanwhile, if in lock-out state, one of testing result d1, d2 (d1 ', d2 ') is in L level and testing result Another testing result in d1, d2 declines, then another testing result in testing result d1 ', d2 ' correspondingly declines.Therefore, just Continuously output L level determines result s1 (T31) to pulse determining section 22.Positive pulse determining section 22 then from lock-out state (ST3) to Stable state (ST1) changes.
The basic operation of negative pulse determining section 23 is described now with reference to Fig. 9.It is assumed here that IN1=d1 and IN2=d1, And it is also supposed that OUT=s2.
First, in stable state (ST1), negative pulse determining section 23 exports L level according to L level testing result d1, d2 Determine result s2.
If testing result d2 rises in stable state, the output of negative pulse determining section 23 H level determines result s2 (T12).Negative pulse determining section 23 and then the transformation from stable state (ST1) to H output states (ST2).
Meanwhile, if testing result d1 rises in stable state, continuously output L level is determined negative pulse determining section 23 As a result s2 (T13).Negative pulse determining section 23 and then the transformation from stable state (ST1) to lock-out state (ST3).
Then, if testing result d2 is held in H level, no matter testing result d1 is to rise also to negative pulse determining section 23 It is to decline all continuous output H level to determine result s2 (T22).In this example, negative pulse determining section 23 is held in H output shapes In state (ST2).
Meanwhile, if testing result d2 declines in H output states, negative pulse determining section 23 is from H output states (ST2) To delay wait state (ST4) transformation.
When passing scheduled delay after the decline from testing result d2, then negative pulse determining section 23 is waited from delay State (ST4) changes to another state.
For example, if testing result d1, d2 is in L level, testing result d1 ', d2 ' are correspondingly in L level.Cause This, the output of negative pulse determining section 23 L level determines result s2 (T41).Negative pulse determining section 23 is then from delay wait state (ST4) change to stable state (ST1).
Meanwhile, if testing result d1 or testing result d2 is in H level, testing result d1 ' or testing result d2 ' Correspondingly in H level.Therefore, the output of negative pulse determining section 23 L level determines result s2 (T43).Negative pulse determining section 23 is then Change from delay wait state (ST4) to lock-out state (ST3).
Then, if one of testing result d1, d2 in lock-out state in one of H level, testing result d1 ', d2 ' Correspondingly in H level.Therefore, continuously output L level determines result s2 but regardless of testing result d1, d2 to negative pulse determining section 23 The transformation (T33) of another testing result in (d1 ', d2 ').In this example, negative pulse determining section 23 is held in locking shape State (ST3).
Meanwhile, if in lock-out state, one of testing result d1, d2 (d1 ', d2 ') is in L level and testing result Another testing result in d1, d2 declines, then another testing result in testing result d1 ', d2 ' correspondingly declines.Therefore, bear Continuously output L level determines result s2 (T31) to pulse determining section 23.Negative pulse determining section 23 then from lock-out state (ST3) to Stable state (ST1) changes.
(timing diagram)
Receiver Rx2 operation is described now with reference to Figure 10 A.Figure 10 A are the exemplary operations for illustrating receiver Rx2 Timing diagram.Not only AC can be used as when transformer is used as AC coupling element ISO1 but also in such as capacitor or GMR element The operation described in Figure 10 A is performed during coupling element ISO1.
In original state (time t0), data VIN is in L level for transmission.Therefore, transmitter Tx1 flows to electric current I1 Primary coil L11 (the approximate 0A of I1=).Therefore, receive signal VR and be held in reference voltage.Pulse-detecting circuit 11 is not detected by Pulse signal with positive amplitude or the pulse signal with negative amplitude.Therefore, pulse-detecting circuit 11 is in these cases Export L level testing result d1, d2.Therefore, the output of positive pulse determining section 22 L level determines result s1, and negative pulse determining section 23 output L levels determine result s2.In other words, positive pulse determining section 22 and negative pulse determining section 23 are in stable state (ST1) in.Thus, the output L level output data of latch cicuit 14 VO.
(time t1) when data VIN changes from L level to H level is being transmitted, transmitter Tx1 is by making electric current I1 from primary Coil L11 one end temporarily flows to the other end to export pulse signal (transmission signal) (time t1 to time with positive amplitude t6).Therefore, positive voltage potential corresponding with the electric current change in primary coil L11 is generated in secondary coil L12 (has positive width The pulse signal of degree) it is used as reception signal VR (A in Figure 10 A) (time t1 to time t2).In this example, if from first The electric current I1 that level coil L11 one end flows to the other end is prevented from, then is also generated and primary coil L11 in secondary coil L12 In electric current change corresponding negative zeta potential (back pulse with negative amplitude) as reception signal VR (B in Figure 10 A) (times T2 to time t6).
When the pulse signal with positive amplitude is not less than threshold voltage vt h+, the output H level inspection of pulse-detecting circuit 11 Survey result d1 (time t1 to time t2).In addition, when the back pulse with negative amplitude is not higher than threshold voltage vt h-, pulse inspection The output H level testing result d2 of slowdown monitoring circuit 11 (time t3 to time t5).Although the back pulse with negative amplitude is not always equivalent to Or less than threshold voltage vt h-, but inadvertently it is equal to or less than threshold voltage vt h- in the back pulse with negative amplitude Example shown in Figure 10 A is described under such hypothesis.
D1, d2 of testing result are present in testing result d1 due to tool in the period of L level (time t2 to time t3) Have positive amplitude pulse signal (A in Figure 10 A) and H level period (time t1 to time t2) with testing result d2 by In the back pulse (B in Figure 10 A) with negative amplitude between the period (time t3 to time t5) of H level.
For example, in Fig. 1 in shown receiver Rx1, positive pulse determines circuit 12 (being equivalent to positive pulse determining section) and negative Pulse determines that circuit 13 (being equivalent to negative pulse determining section) (time t2 to time t3) during the above-mentioned period returns to stable state (ST1).Therefore, receiver Rx1 shown in Fig. 1 may mistakenly obtain back pulse (B in Figure 10 A) conduct with negative amplitude Represent the normal burst signal that transmission data VIN declines.
Therefore in the figure 7 in shown receiver Rx2, positive pulse determines that circuit 12 exports true according to testing result d1 ', d2 ' Determine result s1, testing result d1 ', d2 ' are obtained by postponing the decline of testing result d1, d2.Similarly, negative pulse determines electricity Road 13 determines result s2 according to testing result d1 ', d2 ' output, and detection knot is obtained by postponing the decline of testing result d1, d2 Fruit d1 ', d2 '.Therefore, receiver Rx2 prevents from mistakenly obtaining the back pulse with negative amplitude as normal burst signal.Hereafter Provide details.
In positive pulse determining section 22, delay circuit 15 makes testing result d1 ' in testing result d1 rising (time t1) Rise (time t1) immediately afterwards, and it is predetermined testing result d1 ' is passed after testing result d1 decline (time t2) Decline (time t4) during time delay.In addition, delay circuit 15 makes testing result d2 ' in testing result d2 rising (time t3) Rise (time t3) immediately afterwards, and testing result d2 ' is flowed after the decline of testing result d2 decline (time t5) Die scheduled delay when decline (time t7).
In positive pulse determining section 22, positive pulse determines that circuit 12 is tied at the time of at least testing result d1 rises with detection Fruit d1 at the time of H level between time interval during export H level determine result s1 (time t1 to time t3) and At least testing result d2 (d2 ') rise at the time of and testing result d1 ', d2 ' at the time of L level between the time interval phase Between continuous output L level determine result s1 (time t3 to time t7).
More specifically, positive pulse determining section 22 is according to Fig. 9 transformation graphic operation.
First, when the testing result d1 supplied to input terminal IN1 rises, the output of positive pulse determining section 22 H level is true Determine result s1 (time t1).Positive pulse determining section 22 and then the transformation from stable state (ST1) to H output states (ST2).
Then, positive pulse determining section 22 when testing result d1 declines from H output states (ST2) to delay wait state (ST4) change.When the testing result d2 supplied to input terminal IN2 is rising in postponing wait state, positive pulse determining section 22 export its (time t3) after testing result s1 level is changed over into L from H.
Then, after testing result d1 decline pass scheduled delay when, positive pulse determining section 22 from delay etc. Treat that state (ST4) changes (time t4) to lock-out state (ST3).It should be noted that continuously output L level is true for positive pulse determining section 22 Determine result s1.
Then, when testing result d2 ' declines according to testing result d2 decline, positive pulse determining section 22 is continuously exported L level determines result s1 (time t7).Positive pulse determining section 22 and then the transformation from lock-out state (ST3) to stable state (ST1).
Meanwhile, in negative pulse determining section 23, delay circuit 16 make testing result d1 ' testing result d1 rising (when Between t1) after immediately rise (time t1) and make testing result d1 ' testing result d1 decline (time t2) after pass Decline (time t4) during scheduled delay.In addition, delay circuit 16 make testing result d2 ' testing result d2 rising (when Between t3) after immediately rise (time t3) and make testing result d2 ' testing result d2 decline (time t5) decline it Decline (time t7) during passage scheduled delay afterwards.
In negative pulse determining section 23, negative pulse determines circuit 13 at the time of testing result d1 (d1 ') rises with detecting As a result continuous output L level determines that (time, t1 was arrived result s2 during the time interval between d1 ', d2 ' are at the time of L level Time t7).
More specifically, transformation graphic operation of the negative pulse determining section 23 also according to Fig. 9.
First, when the testing result d1 supplied to input terminal IN2 rises, the output of negative pulse determining section 23 L level is true Determine result s2 (time t1).Negative pulse determining section 23 and then the transformation from stable state (ST1) to lock-out state (ST3).
Then, continuously output L level determines result s2 (time t4) to negative pulse determining section 23, is because while detection knot Fruit d1 ' declines according to testing result d1 decline, but to input terminal IN1 supply testing result d2 (d2 ') on Rise and in H level.In the example present, negative pulse determining section 23 is held in lock-out state (ST3).
Then, when testing result d2 ' declines according to testing result d2 decline, negative pulse determining section 23 is continuously exported L level determines result s2 (time t7).Negative pulse determining section 23 and then the transformation from lock-out state (ST3) to stable state (ST1).
Then, transmit data VIN change from H level to L level when (time t8), transmitter Tx1 by make electric current from The primary coil L11 other end temporarily flows to the one end to export pulse signal (transmission signal) (the time t8 with negative amplitude To time t13).Therefore, negative zeta potential (tool corresponding with the electric current change in primary coil L11 is generated in secondary coil L12 Have the pulse signal of negative amplitude) as reception signal VR (C in Figure 10 A) (time t8 to time t9).In this example, such as The electric current I1 that fruit flows to the one end from the primary coil L11 other end is prevented from, then is also generated and primary in secondary coil L12 Electric current in coil changes corresponding positive voltage potential (back pulse with positive amplitude) as reception signal VR (D in Figure 10 A) (time t9 to time t13).
When the pulse signal with negative amplitude is not higher than threshold voltage vt h-, the output H level inspection of pulse-detecting circuit 11 Survey result d2 (time t8 to time t9).In addition, when the back pulse with positive amplitude is not less than threshold voltage vt h+, pulse inspection The output H level testing result d1 of slowdown monitoring circuit 11 (time t10 to time t12).Although the back pulse with positive amplitude is not always etc. In or higher than threshold voltage vt h+, but threshold voltage is inadvertently at or above in the back pulse with positive amplitude Vth+ is such to assume example shown in lower description Figure 10 A.
D1, d2 of testing result are present in testing result d2 due to tool in the period of L level (time t9 to time t10) Have negative amplitude pulse signal (C in Figure 10 A) and H level period (time t8 to time t9) with testing result d2 by In the back pulse (D in Figure 10 A) with positive amplitude between the period (time t10 to time t12) of H level.
For example, in Fig. 1 in shown receiver Rx1, positive pulse determines circuit 12 (being equivalent to positive pulse determining section) and negative Pulse determines that circuit 13 (being equivalent to negative pulse determining section) (time t9 to time t10) during the above-mentioned period returns to stable state (ST1).Therefore, receiver Rx1 shown in Fig. 1 may mistakenly obtain back pulse (D in Figure 10 A) conduct with positive amplitude Indicate the normal burst signal that transmission data VIN rises.
Therefore in the figure 7 in shown receiver Rx2, positive pulse determines that circuit 12 exports true according to testing result d1 ', d2 ' Determine result s1, testing result d1 ', the d2 ' obtained by postponing the decline of testing result d1, d2.Similarly, negative pulse is determined Circuit 13 determines result s2 according to testing result d1 ', d2 ' output, the inspection obtained by postponing the decline of testing result d1, d2 Survey result d1 ', d2 '.Therefore, receiver Rx2 prevents from mistakenly obtaining the back pulse with positive amplitude as normal burst signal. Details described below.
In positive pulse determining section 22, delay circuit 15 makes testing result d2 ' in testing result d2 rising (time t8) Rise (time t8) immediately afterwards, and it is predetermined testing result d2 ' is passed after testing result d2 decline (time t9) Decline (time t11) during time delay.In addition, delay circuit 15 makes testing result d1 ' in the testing result d1 rising (time T10) after immediately rise (time t10) and make testing result d1 ' testing result d1 decline (time t12) decline it Decline (time t14) during passage scheduled delay afterwards.
In positive pulse determining section 22, positive pulse determines circuit 12 at the time of testing result d2 (d2 ') rises with detecting As a result continuous output L level determines that (time, t8 was arrived result s1 during the time interval between d1 ', d2 ' are at the time of L level Time t14).
In fact, positive pulse determining section 22 is operated according to Fig. 9 state transition diagram.Positive pulse determining section 22 will not be described to exist The operation performed between time t8 and time t14, because it and negative pulse determining section 23 are performed between time t1 and time t7 Operation it is identical.However, should be by " testing result d1 ", " testing result d2 ", " testing result d1 " ' and " testing result d2 ' " Be read as respectively " testing result d2 ", " testing result d1 ", " testing result d2 " ' and " testing result d1 ' ", and should be by " determine that result s2 " is read as " determining result s1 ".
Meanwhile, in negative pulse determining section 23, delay circuit 16 make testing result d2 ' testing result d2 rising (when Between t8) after immediately rise (time t8) and make testing result d2 ' testing result d2 decline (time t9) after pass Decline (time t11) during scheduled delay.In addition, delay circuit 16 make testing result d1 ' testing result d1 rising (when Between t10) after immediately rise (time t10) and make testing result d1 ' testing result d1 decline (time t12) after flow Die and decline (time t14) in scheduled delay.
In negative pulse determining section 23, negative pulse determines that circuit 13 is tied at the time of at least testing result d2 rises with detection Fruit d2 at the time of H level between time interval during export H level determine result s2 (time t8 to time t10), and During time interval between at the time of testing result d1 (d1 ') rises and at the time of testing result d1 ', d2 ' are in L level Continuous output L level determines result s2 (time t10 to time t14).
In fact, negative pulse determining section 23 is operated according to Fig. 9 state transition diagram.Negative pulse determining section 23 will not be described to exist The operation performed between time t8 and time t14, because it and positive pulse determining section 22 are between time t1 and time t7 The operation of execution is identical.However, should be by " testing result d1 ", " testing result d2 ", " testing result d1 " ' and " testing result D2 " ' is read as " testing result d2 ", " testing result d1 ", " testing result d2 " ' and " testing result d1 " ', and should respectively " it will determine that result s1 " is read as " determining result s2 ".
Latch cicuit 14 makes output data VO with determining result s1 rising synchronous rising (time t1) and making output number According to VO with determining that result s2 rising synchronous declines (time t4).
As described above, in receiver Rx2, positive pulse determines that circuit 12 and negative pulse determine the basis of circuit 13 Testing result d1 ', d2 ' export determination result s1, s2 respectively, the detection obtained by postponing the decline of testing result d1, d2 As a result d1 ', d2 '.Testing result d1 ', d2 ' are not present in testing result d1 ' (or d2 ') due to just in the period of L level Pulse signal and the period of H level and testing result d2 ' (d1 ') due to back pulse between the period of H level.Thus connect (reproduction) data can accurately be received by receiving device Rx2, because it can be compensated at the time of positive pulse signal is detected with detecting Any time between at the time of back pulse is delayed.
Reference picture 10A, at the time of testing result d2 ' is in H level and at the time of testing result d1 ', d2 ' are in L level Between period (the first period) be period between time t8 and time t14 and between time t3 and time t7 when Section.Period (second between at the time of testing result d1 ' is in H level and at the time of testing result d1 ', d2 ' are in L level Period) it is the period between time t1 and time t7 and the period between time t10 and time t14.
Figure 10 A are used for describing wherein to detect the back pulse (time t3 to time t5) with negative amplitude and detect tool There is the situation of the back pulse (time t10 to time t12) of positive amplitude.However, for example according to threshold voltage vt h+, Vth- setting The back pulse with negative or positive amplitude may not be detected with operating condition (temperature and supply voltage).Even in such feelings It is naturally that receiver Rx2 can accurately receive data under condition.
Figure 10 B are the timing diagrams for another operation for illustrating receiver Rx2.Figure 10 B timing diagram and Figure 10 A timing diagram are not It is same to be not detect back pulse.Figure 10 B also indicate that receiver Rx2 receives (reproduction) data with high accuracy.It will not describe in figure Other operations described in 10B timing diagram, because it is identical with the operation described in Figure 10 A.
(the first exemplary detailed configuration of delay circuit 15,16)
The first exemplary detailed configuration of delay circuit 15,16 will now be described.Deferred telegram hereafter will be described typically Road 15, because delay circuit 15,16 is configured with same circuits.
Figure 11 is the figure for the exemplary detailed configuration for illustrating delay circuit 15.Delay circuit 15 shown in Figure 11 includes non-OR Circuit (hereinafter referred to as NOR circuit) 151 to 153,161 to 163, non-AND circuit (hereinafter referred to as NAND circuit) 154, 155th, 164,165 and inverter circuit (hereinafter referred to as INV circuits) 156,166.
The output testing result of NOR circuit 151 d1 non-OR.NAND circuit 154 exports the non-of the output of NOR circuit 151 AND.The non-OR of the output of the output NAND circuit 154 of NOR circuit 152.The non-AND of the output of NAND155 output NOR circuits 152. The non-OR of the output of the output NAND circuit 155 of NOR circuit 153.The anti-phase letter of the output of the output NOR circuit 153 of INV circuits 156 Number it is used as testing result d1 '.
The output testing result of NOR circuit 161 d2 non-OR.NAND circuit 164 exports the non-of the output of NOR circuit 161 AND.The non-OR of the output of the output NAND circuit 164 of NOR circuit 162.NAND circuit 165 exports the non-of the output of NOR circuit 162 AND.The non-OR of the output of the output NAND circuit 165 of NOR circuit 163.INV circuits 166 export the anti-of the output of NOR circuit 163 Phase signals are used as testing result d2 '.
Because delay circuit 15 shown in Figure 11 is configured with above-described circuit, so it is by by testing result D1, d2 decline export testing result d1 ', d2 ' relative to their rising significantly delay.
(the second exemplary detailed configuration of delay circuit 15,16)
The second exemplary detailed configuration of delay circuit 15,16 will now be described.Deferred telegram hereafter will be described typically Road 15, because delay circuit 15,16 is configured with same circuits.
Figure 12 is the figure for the exemplary detailed configuration for illustrating delay circuit 15.Delay circuit 15 shown in Figure 12 includes P ditches Road MOS transistor (hereinafter referred to as transistor) MP11, MP12, MP21, MP22 and N-channel MOS transistor are (hereinafter referred to as brilliant Body pipe) MN11, MN12, MN21, MN22.Transistor MP11, MP21, MN12, MN22 conducting resistance are respectively higher than transistor MN11, MN21, MP12, MP22 conducting resistance.
Transistor MP11, MN11 the first phase inverter of formation.Transistor MP12, MN12 the second phase inverter of formation.First is anti-phase Device output testing result d1 inversion signal.The inversion signal that second phase inverter exports the output of the first phase inverter is tied as detection Fruit d1 '.
Transistor MP21, MN21 the 3rd phase inverter of formation.Transistor MP22, MN22 the 4th phase inverter of formation.3rd is anti-phase Device output testing result d2 inversion signal.The inversion signal that 4th phase inverter exports the output of the 3rd phase inverter is tied as detection Fruit d2 '.
In fig. 12 in shown delay circuit 15, when testing result d1 rises, the transistor with low on-resistance MN11, MP12 are turned on, and MP11, MN12 with high conducting resistance are turned off.Therefore, testing result d1 ' determines relatively early Shi Shangsheng.Similarly, in fig. 12 in shown delay circuit 15, when testing result d2 rises, the crystalline substance with low on-resistance Body pipe MN21, MP22 are turned on and transistor MP21, MN22 with high conducting resistance are turned off.Therefore, testing result d2 ' is in phase Early timing is risen.
Meanwhile, in fig. 12 in shown delay circuit 15, when testing result d1 rises, the crystal with high conducting resistance Pipe MP11, MN12 are turned on, and transistor MN11, MP12 with low on-resistance are turned off.Therefore, testing result d1 ' is in phase Timing to evening rises.Similarly, in fig. 12 in shown delay circuit 15, when testing result d2 rises, with height conducting Transistor MP21, MN22 conducting of resistance, and transistor MN21, MP22 with low on-resistance shut-off.Therefore, detection knot Fruit d2 ' rises in relatively late timing.
Because delay circuit 15 shown in Figure 12 is configured with above-described circuit, so it is by by testing result D1, d2 decline export testing result d1 ', d2 ' relative to their rising significantly delay.
Figure 13 is that diagram receiver Rx2 determines that circuit 12 and negative pulse determine circuit 13 by as shown in Figure 5 in positive pulse The timing diagram of the operation performed when configuring like that.In Figure 13 timing diagram, also describe the defeated of each SR latch cicuits 121,131 Go out signal.Figure 13 other parts will not be described, because it is identical with the other parts described in Figure 10 A.
As described above, provided and the receiver according to first embodiment according to the receiver Rx2 of the present embodiment Identical advantage.In addition, in the receiver Rx2 according to the present embodiment, positive pulse determines that circuit 12 and negative pulse determine circuit 13 export determination result s1, s2 according to testing result d1 ', d2 ' respectively, are obtained by postponing the decline of testing result d1, d2 Testing result d1 ', d2 '.Therefore, receiver Rx2 can accurately receive (reproduction) data, detected because it can be compensated Any time between at the time of normal burst signal and at the time of detecting back pulse is delayed.
Even if in addition, when detecting multiple noise component(s)s using time lag after detecting normal burst signal When (including back pulse), data still can accurately be received according to the receiver Rx2 of the present embodiment, because it can pass through delay The decline of testing result d1, d2 caused by noise component(s) compensates time lag.
3rd embodiment
Figure 14 is the block diagram for the exemplary configuration for illustrating semiconductor integrated circuit 3, and the semiconductor integrated circuit includes basis The receiver Rx3 of the third embodiment of the present invention is to form isolator.It will be described in 3rd embodiment now.
Semiconductor integrated circuit 3 shown in Figure 14 is that the former includes connecing with the difference of semiconductor integrated circuit 1 shown in Fig. 1 Device Rx3 is received to replace receiver Rx1.The configuration of the other parts of semiconductor integrated circuit 3 shown in Figure 14 will not described, because It is identical with the configuration of the other parts of semiconductor integrated circuit 1 shown in Fig. 1.
Receiver Rx3 and receiver Rx1 differences are that the former determines circuit 32 to replace positive pulse to determine including positive pulse Circuit 12 and negative pulse determine circuit 33 to replace negative pulse to determine circuit 13.
Positive pulse determines that circuit 32 determines the pulse signal with positive amplitude that pulse-detecting circuit 11 is detected.Positive pulse Determine the uncertain pulse signal with positive amplitude of circuit 32 for normal burst signal until detecting the arteries and veins with negative amplitude Scheduled time slot of passing is rushed after signal.More specifically, positive pulse determines that circuit 32 is pre- after H level in testing result d2 L level (the first logical value) is exported during timing section and determines result (first determines result) s1, and if testing result d1 exists H level (the second logical value) is then exported in H level determine result (first determines result) s1 during other periods.
Negative pulse determines that circuit 33 determines the pulse signal with negative amplitude that pulse-detecting circuit 11 is detected.Negative pulse Determine that the uncertain pulse signal with negative amplitude of circuit 33 is normal burst signal until detecting the arteries and veins with positive amplitude Scheduled time slot of passing is rushed after signal.More specifically, negative pulse determines that circuit 33 is pre- after H level in testing result d1 L level (the first logical value) is exported during timing section and determines result (second determines result) s2, and if testing result d2 exists H level (the second logical value) is then exported in H level determine result (second determines result) s2 during other periods.
Figure 15 is that diagram positive pulse determines that circuit 32 and negative pulse determine the figure of the exemplary detailed configuration of circuit 33.Reference Figure 15, positive pulse determines that circuit 32 includes delay circuit (the first delay circuit) 321 and AND circuit 322.Delay circuit 321 leads to The rising by input signal relative to it is crossed significantly to postpone it to export its decline.Negative pulse determines that circuit 33 includes deferred telegram Road (the second delay circuit) 331 and AND circuit 332.Delay circuit 331 is by the way that input signal is significantly prolonged relative to its rising It exports its decline late.
Delay circuit 321 is by the way that the testing result d2 of pulse-detecting circuit 11 decline is significantly prolonged relative to its rising Belated output testing result d2 '.Included by using the configuration of the delay circuit 15 (16) shown in such as Figure 11 and 12 Path forms delay circuit 321.The testing result d1's and testing result d2 ' of the output pulse-detecting circuit 11 of AND circuit 322 The logic AND of inversion signal s1 as determining result.Therefore, positive pulse determines circuit 32 during testing result d2 ' rising Shelter testing result d1.
Delay circuit 331 is by the way that the testing result d1 of pulse-detecting circuit 11 decline is significantly prolonged relative to its rising Belated output testing result d1 '.Included by using the configuration of the delay circuit 15 (16) shown in such as Figure 11 and 12 Path forms delay circuit 331.The testing result d2's and testing result d1 ' of the output pulse-detecting circuit 11 of AND circuit 332 The logic AND of inversion signal s2 as determining result.Therefore, negative pulse determines circuit 33 during testing result d1 ' rising Shelter testing result d2.
The circuit configuration of receiver Rx3 other parts will not described, because its electricity with receiver Rx1 other parts Road configuration is identical.
(positive pulse determines that circuit 32 and negative pulse determine the state transition diagram of circuit 33)
Figure 16 is the state transition diagram that positive pulse determines circuit 32 (negative pulse determines circuit 33).Figure 16 state transition diagram It is to delete transformation T43 with Fig. 9 state transition diagram difference.More specifically, positive pulse determines that circuit 32 waits shape from delay State (ST4) consistently changes to stable state (ST1) and not changed to lock-out state.Similarly, negative pulse determine circuit 33 from Delay wait state (ST4) does not change to stable state (ST1) constant transformation to lock-out state.It will not describe shown in Figure 16 Other transformations, because they are identical with other transformations described in Fig. 9.
As described above, positive pulse determines that circuit 32 and negative pulse determine that circuit 33 is constant from delay wait state Ground changes to stable state and not changed to lock-out state.Therefore, delay wait state need to continue period for fully growing with Just the noise component(s) generated in signal VR is received is eliminated.
(timing diagram)
Figure 17 A are the timing diagrams for the operation for illustrating receiver Rx3.Not only AC coupling elements ISO1 can be used as in transformer When and perform the operation described in Figure 17 A when such as capacitor or GMS elements are used as AC coupling element ISO1.
Figure 17 A timing diagram and Figure 10 A timing diagram difference be testing result d1 ' fall time (t4 ', t14) and Testing result is more late to the fall time of d2 ' fall time (t7, t11 ') than being indicated in Figure 10 A timing diagram.In addition, just Pulse determines that circuit 32 shelters testing result d2 during testing result d2 ' rising.Therefore, positive pulse determines that circuit 32 only exists H level is exported during period between time t1 and time t2 and determines result s1.Meanwhile, negative pulse determines that circuit 33 is tied in detection Testing result d2 is sheltered during fruit d1 ' rising.Therefore, negative pulse determine circuit 33 only between time t8 and time t9 when H level is exported during section and determines result s2.By other operations indicated in the timing diagram for not describing Figure 17 A, because it and Figure 10 A Other operations of middle instruction are substantially the same.
Reference picture 17A, in the scheduled time slot after H level is between time t8 and time t11 ' in testing result d2 Period and the period between time t3 and time t7.In addition, testing result d1 the scheduled time slot after H level be when Between the period between t1 and time t4 ' and the period between time t10 and time t14.
The description that reference picture 17A is provided is based on the back pulse (time t3 to time t5) and inspection detected with negative amplitude Measure the such hypothesis of the back pulse (time t1O to time t12) with positive amplitude.However, for example according to threshold voltage vt h+, Vth- setting and operating condition (temperature and supply voltage) can will not detect the back pulse with negative or positive amplitude.Even if In this case, it is naturally that receiver Rx3 can accurately receive data.
Figure 17 B are the timing diagrams for another operation for illustrating receiver Rx3.Figure 17 B timing diagram and Figure 17 A timing diagram are not It is same to be not detect back pulse.Figure 17 B also indicate that receiver Rx3 receives (reproduction) data with high accuracy.Figure 17 B will not be described Timing diagram in describe other operation because it is identical with other operations described in Figure 17 A.
As described above, it is straight that any pulse signal is not defined as into normal burst signal according to the receiver Rx3 of the present embodiment To detect with just or negative amplitude pulse signal and be defined as pre- timing of passing after normal burst signal Section.Therefore, provided the advantage provided with the first and second embodiments equivalent advantage according to the receiver Rx3 of the present embodiment.
As described in more early, detect with just or negative amplitude pulse signal and be defined as normal After pulse signal, the pulse signal with positive amplitude is being not detected by also not according to the receiver of first or second embodiment Any pulse signal normal burst signal is not defined as before detecting both pulse signals with negative amplitude.Therefore, root The noise component(s) (including back pulse) generated in signal VR is received can be eliminated according to the receiver of first or second embodiment. This makes it possible to receive (reproduction) data with high accuracy.In this example, connect according to first or second embodiment Device is received to be different from correlation technique without the special circuit compared for analog voltage and determine circuit and negative arteries and veins with positive pulse It is digital control that punching determines that circuit is carried out.It therefore, it can accurately receive data by using small scale in circuitry configuration.
In addition, even in detecting making an uproar including back pulse using the time lag after normal burst signal is detected During sound component, according to the receiver of second embodiment still can by delay pulse detect circuit testing result decline come It is accurate to receive data.
In addition, according to the receiver of 3rd embodiment detect with just or negative amplitude pulse signal and by its It is defined as any pulse signal not being defined as into normal burst signal before passage scheduled time slot after normal burst signal.Cause And, provided the advantage provided with the first and second embodiments equivalent advantage according to the receiver of 3rd embodiment.
(Alternate implementations of semiconductor integrated circuit 1 to 3)
The implementation of semiconductor integrated circuit 1 to 3 is not limited to the implementation described in Fig. 2.Semiconductor integrated circuit 1 The Alternate implementations that reference picture 18 to 25 describes semiconductor integrated circuit 1 to 3 will be used for as representative example now.Figure 18 Wherein Alternate implementations of the transformer as AC coupling elements ISO1 are shown to 23.Figure 24 shows that wherein capacitor is used as AC couplings Close an element ISO1 Alternate implementations.Figure 25 shows wherein alternative realizations of the GMR element as AC coupling elements ISO1 Mode.
In figure 18 in shown implementation, transmitter Tx1 and configuration AC couplings are formed on semiconductor chip CHP0 Close element ISO1 primary and secondary coil L11, L12, and the formation receiver Rx1 on semiconductor chip CHP1.In addition, The pad at the two ends that will be coupled into secondary coil L12 is formed on semiconductor chip CHP0.In addition, in semiconductor chip CHP1 On formed will be coupled into receiver Rx1 input pad.Receiver Rx1 is coupled to by these pads and bonding wiring W The secondary coil L12 formed on semiconductor chip CHP0.
In figure 18 in shown implementation, the first wiring layers of vertical stacking neutralize second in single semiconductor chip Primary coil L11 and secondary coil L12 are formed in wiring layers respectively.
Shown in Figure 19 in implementation, transmitter Tx1 is formed on semiconductor chip CHP0, in semiconductor chip Receiver Rx1 is formed on CHP1, and is formed on the semiconductor chip CHP3 different from semiconductor chip CHP0, CHP1 Configure AC coupling elements ISO1 primary and secondary coil L11, L12.Will coupling in addition, being formed on semiconductor chip CHP0 To the pad of transmitter Tx1 output.The weldering for the input that will be coupled into receiver Rx1 is formed on semiconductor chip CHP1 Disk.In addition, forming the pad at the two ends that will be coupled into primary coil L11 on semiconductor chip CHP3 and will be coupled into secondary The pad at coil L12 two ends.Transmitter Tx1 by these pads and bonding wiring W be coupled to semiconductor chip CHP3 it The primary coil of upper formation.Receiver Rx1 is coupled to the shape on semiconductor chip CHP3 by these pads and bonding wiring W Into secondary coil L12.
Shown in Figure 19 in implementation, the first wiring layers of vertical stacking neutralize second in single semiconductor chip Primary coil L11 and secondary coil L12 are formed in wiring layers respectively.
In fig. 20 in shown implementation, transmitter Tx1 and primary coil are formed on semiconductor chip CHP0 L11, forms receiver Rx1 and secondary coil on semiconductor chip CHP1, and stacked semiconductor chips CHP0 and partly leads Body chip CHP1.In addition, when stacked semiconductor chips CHP0 and semiconductor chip CHP1, primary coil L11 center with Secondary coil L12 center alignment.
In figure 21 in shown implementation, transmitter Tx1, receiver are formed on common semiconductor chip CHP4 Rx1 and configuration AC coupling elements ISO1 primary and secondary coil L11, L12.In figure 21 in shown example, in semiconductor The first wiring layers of vertical stacking neutralize in the second wiring layers and form primary coil L11 and secondary coil respectively in chip CHP4 L12.In addition, setting transmitter Tx1 region wherein and setting receiver Rx1 region to pass through in semiconductor chip wherein The insulating barrier formed in CHP4 substrate is mutually isolated.
Figure 22 and 23 is the cross-sectional view of semiconductor chip CHP4 substrate shown in pictorial image 21.It is exemplified in fig. 22 In son, the region for forming transmitter Tx1 wherein and the region that forms receiver Rx1 wherein by insulating barrier it is mutually electric every From.Primary coil L11 and secondary coil L12 is set in the region for wherein forming receiver Rx1.Meanwhile, it is shown in fig 23 In example, the region for forming transmitter Tx1 wherein and the region that forms receiver Rx1 wherein by insulating barrier it is mutually electric every From.Primary coil L11 and secondary coil L12 is set in the region for wherein forming transmitter Tx1.
Figure 24 shows that wherein capacitor is substituted in the transformer for being used as AC coupling elements ISO1 shown in Fig. 2 in implementation Situation.More specifically, Figure 24 shows the electrode C11 substitution coil L11 of capacitor and another electrode of capacitor C12 substitution coils L12 situation.
Figure 25 shows that wherein GMR element is substituted in the transformation for being used as AC coupling elements ISO1 shown in Fig. 2 in implementation The situation of device.More specifically, Figure 25 shows wherein to use coil L11 as former state and GMR element R12 replaces coil L12 feelings Condition.
As mentioned earlier, non-concrete restriction AC coupling elements ISO1 type and setting.Although in semiconductor core Formed on piece under the such hypothesis of AC coupling elements ISO1 and provide described above, but AC coupling element ISO1 conducts can be set Exterior section.
(example for being applied to product)
Power transistor is for example controlled according to the semiconductor integrated circuit of first, second or 3rd embodiment.At this In example, the data VO that is reproduced according to receiver is passed through according to the semiconductor integrated circuit of first, second or 3rd embodiment Carry out and the on-off of power transistor is controlled to control the conduction between power supply and load.
In addition, according to first, second or 3rd embodiment semiconductor integrated circuit suitable for such as such as Figure 26 institute Show the inverter of drive motor (load).The height and downside of inverter shown in Figure 26, which each have, to be used to calculate according to from micro- The PWM transmission data (such as UH, UL) (referring to Figure 27) of machine output carry out the electric current (such as IU) to flowing to motor Simulate three gate drivers of control.
(being compared with correlation technique)
In " A2.5kV isolation35kV/us CMR250Mbps0.13mA/Mbps digital isolator in Standard CMOS with an on-chip small transformer " (S.Kaeriyama, S.Uchida, M.Furumiya, M.Okada, M.Mizuno, 2010Symposium on VLSI Circuits, Technical Digest Of Technical Papers, 2010, the 197-198 pages) disclosed in semiconductor integrated circuit compare the arteries and veins with positive amplitude The amplitude of signal is rushed with having the amplitude of the pulse signal of negative amplitude to determine which pulse signal is to represent data transformation just Normal pulse signal.However, the semiconductor integrated circuit of this correlation technique is unable to the increase of suppression circuit size, because it needs to use The special circuit (being specially passive element) compared in analog voltage.In addition, for example due to being difficult to adjust this correlation technique The characteristic of semiconductor integrated circuit and can not easily design it.It is, for example, with reference to electricity for the special circuit that analog voltage compares Press generator circuit, resistance element, capacitive element or peak holding circuit.On the other hand, according to first, second or The receiver of 3rd embodiment is different from easily suppression circuit size to increase to the technology of closing, because it is digitally determined normally Pulse signal.Furthermore it is possible to relatively easily be related to the receiver according to first, second or 3rd embodiment, because it is carried For digital control.
In addition, the semiconductor integrated circuit of correlation technique requires that the amplitude of back pulse is sufficiently smaller than the width of normal burst signal Degree.This makes it necessary to finely tune the electric current for flowing to transmission coil.On the other hand, according to first, second or 3rd embodiment Receiver eliminates back pulse without let it be amplitude.This avoids the necessity that fine setting flows to the electric current of transmission coil.
Although specifically describing the present invention that the present inventor contemplates in terms of preferred embodiment, it will be understood that The invention is not restricted to those preferred embodiments, but extend to still fall within the various modifications in scope of the following claims.
Determine that circuit and negative pulse determine that circuit is described under having the such hypothesis of same circuits configuration in positive pulse First to 3rd embodiment.However, the invention is not restricted to such configuration.It is suitable for wherein positive pulse determines circuit Determine that circuit has the different configurations of identical function with negative pulse.
In first had been described above into 3rd embodiment, positive pulse determines that circuit exports L during the first period Level determines result s1.If detecting the pulse signal with positive amplitude during the period in addition to the first period, Positive pulse determines that circuit output H level determines result s1.In addition, negative pulse determines that circuit exports L level during the second period Determine result s2.If detecting the pulse signal with negative amplitude during the period in addition to the second period, arteries and veins is born Punching determines that circuit output H level determines result.However, determine that the logical value of result s1, s2 is determined temporarily.Therefore, positive and negative As long as pulse determine any one circuit in circuit or the two they fall within the scope of the appended claims just can be with defeated Go out determination result s1, s2 of inverse logic value.In this case, the configuration of downstream data generating unit is changed when appropriate.
For example included according to the receiver of previous embodiment：Pulse-detecting circuit, positive pulse determine that circuit, negative pulse are determined Circuit and data generating section.Pulse-detecting circuit detection has positive amplitude from transmitter by what AC coupling elements were transmitted Pulse signal and the pulse signal with negative amplitude.Positive pulse determines that circuit exports the of the first logical value during the first period One determines result, and the first period was with being not detected by with positive amplitude at the time of the pulse signal with negative amplitude is detected Time interval between at the time of pulse signal is also not detected by the pulse signal with negative amplitude, and if except first The first determination result that the pulse signal with positive amplitude then exports the second logical value is detected during period outside period.It is negative Pulse determines that circuit exports second of a logical value in the first and second logical values during the second period and determines result, the Two periods were with being not detected by the pulse signal with positive amplitude also not at the time of the pulse signal with positive amplitude is detected Time interval between at the time of detecting the pulse signal with negative amplitude, and if in addition to the second period when The pulse signal with negative amplitude is detected during section and then exports the second true of another logical value in the first and second logical values Determine result.Data generating section determines result generation data according to first and second.For example figure 5 illustrates for implementing above-mentioned connect Receive the physical circuit configuration of device.
More specifically, included according to the receiver of previous embodiment：Pulse-detecting circuit, detection passes through AC from transmitter What the pulse signal with positive amplitude and the pulse signal with negative amplitude of coupling element transmission and respectively output were detected Pulse signal is used as the first and second detection signals；Positive pulse determines circuit, and output first determines result；Negative pulse determines electricity Road, output second determines result；And data generating section, determine result generation data according to first and second.Positive pulse is determined Circuit includes：First SR latch cicuits, it is using set input to input the second testing result, using the RESET input To input the inversion signal of the first testing result and using lead-out terminal to export first M signal；And first logic AND circuit, it exports the inversion signal of first M signal and the logic AND of the first testing result as first and determines result. Negative pulse determines that circuit includes：2nd SR latch cicuits, it is using set input to input the first testing result, using multiple Position input terminal is to input the inversion signal of the second testing result and using lead-out terminal to export second M signal；And The logic AND of second logic AND circuit, its inversion signal for exporting second M signal and the second testing result is true as second Determine result.
In addition, for example being included according to the receiver of previous embodiment：Pulse-detecting circuit, positive pulse determine circuit, negative arteries and veins Punching determines circuit and data generating section.Pulse-detecting circuit detection has just from transmitter by what AC coupling elements were transmitted The pulse signal of amplitude and the pulse signal with negative amplitude.Positive pulse determines that circuit is detecting the pulse letter with negative amplitude First that the first logical value is exported during scheduled time slot after number determines result, and if in addition to scheduled time slot The first determination result that the pulse signal with positive amplitude then exports the second logical value is detected during period.Negative pulse determines electricity Road exports one in the first and second logical values during the scheduled time slot after detecting the pulse signal with positive amplitude The second of logical value determines result, and if the arteries and veins with negative amplitude is detected during the period in addition to scheduled time slot Rush the second determination result that signal then exports another logical value in the first and second logical values.Data generating section is according to the first He Second determines result generation data.For example figure 15 illustrates the physical circuit configuration for implementing above-mentioned receiver.
More specifically, included according to the receiver of previous embodiment：Pulse-detecting circuit, it is detected passes through from transmitter The pulse signal with positive amplitude and the pulse signal with negative amplitude of AC coupling elements transmission, and output is detected respectively Pulse signal be used as the first and second testing results；Positive pulse determines circuit, and it exports first and determines result；Negative pulse is determined Circuit, it exports second and determines result；And data generating section, it determines result generation data according to first and second.Positive arteries and veins Punching determines that circuit includes：First delay circuit and the first logic AND circuit.First delay circuit uses delay output indication still It is not detected by the part of the second testing result of the pulse signal with negative amplitude.First logic AND circuit output first postpones The inversion signal of second testing result of circuit delay and the logic AND of the first testing result determine result as first.Negative arteries and veins Punching determines that circuit includes：Second delay circuit and the second logic AND circuit.Second delay circuit uses delay output indication still It is not detected by the part of the first testing result of the pulse signal with positive amplitude.Second logic AND circuit output second postpones The inversion signal of first testing result of circuit delay and the second testing result logic AND determines result as second.

Claims (7)

1. a kind of receiver, including：
Pulse-detecting circuit, detects the pulse signal with positive amplitude that is transmitted from transmitter by AC coupling elements and with bearing The pulse signal of amplitude；
Positive pulse determines circuit, exported during the first period the first logical value first determine result, and if except The pulse signal with positive amplitude then exports the second logical value described is detected during period outside first period One determines result, and first period is with being not detected by with positive width at the time of the pulse signal with negative amplitude is detected Time interval between at the time of the pulse signal of degree is also not detected by the pulse signal with negative amplitude；
Negative pulse determines circuit, and one in first logical value and second logical value is exported during the second period Second determines result, and if the pulse letter with negative amplitude is detected during the period in addition to second period Number then export described the second of first logical value and another logical value in second logical value and determine result, described the Two periods were with being not detected by the pulse signal with positive amplitude also not at the time of the pulse signal with positive amplitude is detected Time interval between at the time of detecting the pulse signal with negative amplitude；And
Data generating section, determines that result and described second determines result generation data according to described first；
The wherein described pulse signal of the pulse-detecting circuit detection with positive amplitude is examined with exporting the first testing result Measuring tool has the pulse signal of negative amplitude to export the second testing result；
Wherein described positive pulse determines that circuit includes：
First SR latch cicuits, using set input to input second testing result, using the RESET input with Input the inversion signal of first testing result, and using lead-out terminal to export first M signal；And
First logic AND circuit, exports the inversion signal of the first M signal and the logic AND of first testing result Result is determined as described first；And
Wherein described negative pulse determines that circuit includes：
2nd SR latch cicuits, using set input to input first testing result, using the RESET input with Input the inversion signal of second testing result, and using lead-out terminal to export second M signal；And
Second logic AND circuit, exports the inversion signal of the second M signal and the logic AND of second testing result Result is determined as second.
2. receiver according to claim 1, in addition to：
Delay circuit, testing result, the instruction of the delay output pulse-detecting circuit are not yet detected with positive amplitude The part of pulse signal, and postpone to export the pulse-detecting circuit it is testing result, indicate not yet to detect with negative The part of the pulse signal of amplitude；
Wherein described positive pulse determines that circuit and the negative pulse determine the detection of the circuit according to the delay circuit delays As a result described first is exported respectively determines that result and described second determines result.
3. receiver according to claim 1, in addition to：
Delay circuit, delay output first testing result, indicate not yet to detect the pulse signal with positive amplitude Part, and postpone output second testing result, indicate not yet to detect the part of the pulse signal with negative amplitude,
Wherein described positive pulse determines that circuit and the negative pulse determine circuit respectively according to the delay circuit delays First testing result and second testing result output described first determine that result and described second determines result.
4. receiver according to claim 1, wherein the data generating section is SR latch cicuits, the SR latch cicuits Result is determined to input described first using set input, determines to tie to input described second using the RESET input Really, and using lead-out terminal to export the data.
5. a kind of receiver, including：
Pulse-detecting circuit, detects the pulse signal with positive amplitude that is transmitted from transmitter by AC coupling elements and with bearing The pulse signal of amplitude；
Positive pulse determines circuit, and the first logic is exported during the scheduled time slot after detecting the pulse signal with negative amplitude The first of value determines result, and if the arteries and veins with positive amplitude is detected during the period in addition to the scheduled time slot Rush the first determination result that signal then exports the second logical value；
Negative pulse determines circuit, and described first is exported during the scheduled time slot after detecting the pulse signal with positive amplitude The second determination result of one in logical value and second logical value, and if in addition to the scheduled time slot The pulse signal with negative amplitude is detected during period and then exports another in first logical value and second logical value Described the second of one determines result；And
Data generating section, determines that result and described second determines result generation data according to described first；
The wherein described pulse signal of the pulse-detecting circuit detection with positive amplitude is examined with exporting the first testing result Measuring tool has the pulse signal of negative amplitude to export the second testing result；
Wherein described positive pulse determines that circuit includes：
First delay circuit, delay output second testing result, indicate not yet to detect the pulse letter with negative amplitude Number part；And
First logic AND circuit, exports inversion signal and the institute of second testing result of first delay circuit delays The logic AND of the first testing result is stated as the described first determination result；And
Wherein described negative pulse determines that circuit includes：
Second delay circuit, delay output first testing result, indicate not yet to detect the pulse letter with positive amplitude Number part；And
Second logic AND circuit, exports inversion signal and the institute of first testing result of second delay circuit delays The logic AND of the second testing result is stated as the described second determination result.
6. receiver according to claim 5, wherein the data generating section is SR latch cicuits, the SR latch cicuits Result is determined to input described first using set input, determines to tie to input described second using the RESET input Really, and using lead-out terminal to export the data.
7. a kind of semiconductor integrated circuit, including：
Transmitter, generation has the pulse signal in the corresponding amplitude direction that turns of the data with being supplied from outside and defeated Go out the pulse signal as transmission signal；
Receiver according to claim 1, the data according to receiving signal reproduction；And
AC coupling elements, make the transmitter and the receiver be spaced from each other and transmit the transmission signal and are connect as described The collection of letters number.
CN201310118543.9A 2012-03-30 2013-04-01 Receiver and the semiconductor integrated circuit with the receiver Expired - Fee Related CN103368535B (en)

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Publication number Priority date Publication date Assignee Title
US5701037A (en) * 1994-11-15 1997-12-23 Siemens Aktiengesellschaft Arrangement for inductive signal transmission between the chip layers of a vertically integrated circuit
CN201298823Y (en) * 2008-09-27 2009-08-26 美芯集成电路(深圳)有限公司 CMOS current self-control crystal oscillator
JP2011142175A (en) * 2010-01-06 2011-07-21 Nec Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5701037A (en) * 1994-11-15 1997-12-23 Siemens Aktiengesellschaft Arrangement for inductive signal transmission between the chip layers of a vertically integrated circuit
CN201298823Y (en) * 2008-09-27 2009-08-26 美芯集成电路(深圳)有限公司 CMOS current self-control crystal oscillator
JP2011142175A (en) * 2010-01-06 2011-07-21 Nec Corp Semiconductor device

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