JP4191602B2 - スケーラブル・アーキテクチャを備えた再構成可能な集積回路 - Google Patents

スケーラブル・アーキテクチャを備えた再構成可能な集積回路 Download PDF

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JP4191602B2
JP4191602B2 JP2003535333A JP2003535333A JP4191602B2 JP 4191602 B2 JP4191602 B2 JP 4191602B2 JP 2003535333 A JP2003535333 A JP 2003535333A JP 2003535333 A JP2003535333 A JP 2003535333A JP 4191602 B2 JP4191602 B2 JP 4191602B2
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JP2005505978A (ja
JP2005505978A5 (enExample
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レブレウスキー,フレデリック
ルパップ,オリヴィエ
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エム2000
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/64Distributing or queueing
    • H04Q3/68Grouping or interlacing selector groups or stages
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1302Relay switches
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1304Coordinate switches, crossbar, 4/2 with relays, coupling field
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13109Initializing, personal profile
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13322Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2003535333A 2001-10-04 2002-10-02 スケーラブル・アーキテクチャを備えた再構成可能な集積回路 Expired - Lifetime JP4191602B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/971,349 US6594810B1 (en) 2001-10-04 2001-10-04 Reconfigurable integrated circuit with a scalable architecture
PCT/EP2002/011075 WO2003032492A2 (en) 2001-10-04 2002-10-02 A reconfigurable integrated circuit with a scalable architecture

Publications (3)

Publication Number Publication Date
JP2005505978A JP2005505978A (ja) 2005-02-24
JP2005505978A5 JP2005505978A5 (enExample) 2006-01-05
JP4191602B2 true JP4191602B2 (ja) 2008-12-03

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JP2003535333A Expired - Lifetime JP4191602B2 (ja) 2001-10-04 2002-10-02 スケーラブル・アーキテクチャを備えた再構成可能な集積回路

Country Status (6)

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US (1) US6594810B1 (enExample)
EP (1) EP1433257B1 (enExample)
JP (1) JP4191602B2 (enExample)
AU (1) AU2002347046A1 (enExample)
CA (1) CA2461540C (enExample)
WO (1) WO2003032492A2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6978186B2 (en) * 2002-03-22 2005-12-20 International Rectifier Corporation Modular functional block for an electronic control system
US6975139B2 (en) 2004-03-30 2005-12-13 Advantage Logic, Inc. Scalable non-blocking switching network for programmable logic
US7698118B2 (en) * 2004-04-15 2010-04-13 Mentor Graphics Corporation Logic design modeling and interconnection
US7460529B2 (en) * 2004-07-29 2008-12-02 Advantage Logic, Inc. Interconnection fabric using switching networks in hierarchy
US7224184B1 (en) * 2004-11-05 2007-05-29 Xilinx, Inc. High bandwidth reconfigurable on-chip network for reconfigurable systems
US7263456B2 (en) * 2006-01-10 2007-08-28 M2000 On circuit finalization of configuration data in a reconfigurable circuit
US7768301B2 (en) * 2006-01-17 2010-08-03 Abound Logic, S.A.S. Reconfigurable integrated circuits with scalable architecture including a plurality of special function elements
US7274215B2 (en) * 2006-01-17 2007-09-25 M2000 Sa. Reconfigurable integrated circuits with scalable architecture including one or more adders
US7368943B2 (en) * 2006-03-28 2008-05-06 Advantage Logic, Inc. Enhanced scheme to implement an interconnection fabric using switching networks in hierarchy
US7739647B2 (en) * 2006-09-12 2010-06-15 Infosys Technologies Ltd. Methods and system for configurable domain specific abstract core
US7714611B1 (en) * 2008-12-03 2010-05-11 Advantage Logic, Inc. Permutable switching network with enhanced multicasting signals routing for interconnection fabric
US7705629B1 (en) 2008-12-03 2010-04-27 Advantage Logic, Inc. Permutable switching network with enhanced interconnectivity for multicasting signals
US7999570B2 (en) * 2009-06-24 2011-08-16 Advantage Logic, Inc. Enhanced permutable switching network with multicasting signals for interconnection fabric
US8341580B2 (en) * 2009-09-28 2012-12-25 Advantage Logic, Inc. Modular routing fabric using switching networks
JP2017169118A (ja) 2016-03-17 2017-09-21 株式会社東芝 集積回路および電子機器

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4020469A (en) 1975-04-09 1977-04-26 Frank Manning Programmable arrays
USRE34363E (en) 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4642487A (en) 1984-09-26 1987-02-10 Xilinx, Inc. Special interconnect for configurable logic array
US4700187A (en) 1985-12-02 1987-10-13 Concurrent Logic, Inc. Programmable, asynchronous logic cell and array
US4918440A (en) 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
US5255203A (en) 1989-08-15 1993-10-19 Advanced Micro Devices, Inc. Interconnect structure for programmable logic device
FR2660510A1 (fr) 1990-03-27 1991-10-04 Dune Technologies Procede et dispositif d'interconnexion programmable entre deux ensembles de circuits electroniques et application a un circuit logique programmable.
US5260610A (en) 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
US5208491A (en) 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
US5396126A (en) 1993-02-19 1995-03-07 At&T Corp. FPGA with distributed switch matrix
GB2280293B (en) 1993-07-19 1997-12-10 Hewlett Packard Co Architecture for programmable logic
US5457410A (en) 1993-08-03 1995-10-10 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
US5455525A (en) 1993-12-06 1995-10-03 Intelligent Logic Systems, Inc. Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
US5648911A (en) * 1993-12-21 1997-07-15 Grodstein; Joel Joseph Method of minimizing area for fanout chains in high-speed networks
US6294928B1 (en) 1996-04-05 2001-09-25 Altera Corporation Programmable logic device with highly routable interconnect
US5594363A (en) 1995-04-07 1997-01-14 Zycad Corporation Logic cell and routing architecture in a field programmable gate array
AU5718196A (en) 1995-05-03 1996-11-21 Btr, Inc. Scalable multiple level interconnect architecture
US5909126A (en) 1995-05-17 1999-06-01 Altera Corporation Programmable logic array integrated circuit devices with interleaved logic array blocks
US5963049A (en) 1995-05-17 1999-10-05 Altera Corporation Programmable logic array integrated circuit architectures
US5574388A (en) 1995-10-13 1996-11-12 Mentor Graphics Corporation Emulation system having a scalable multi-level multi-stage programmable interconnect network
JP3486725B2 (ja) 1995-11-28 2004-01-13 株式会社ルネサステクノロジ 可変論理集積回路
US5742181A (en) 1996-06-04 1998-04-21 Hewlett-Packard Co. FPGA with hierarchical interconnect structure and hyperlinks
US6094066A (en) * 1996-08-03 2000-07-25 Mission Research Corporation Tiered routing architecture for field programmable gate arrays
US5796268A (en) 1996-10-02 1998-08-18 Kaplinsky; Cecil H. Programmable logic device with partial switch matrix and bypass mechanism
US6289494B1 (en) * 1997-11-12 2001-09-11 Quickturn Design Systems, Inc. Optimized emulation and prototyping architecture
US6137308A (en) 1998-01-20 2000-10-24 Cypress Semiconductor Corporation Programmable interconnect matrix architecture for complex programmable logic device
US6218859B1 (en) 1998-05-26 2001-04-17 Altera Corporation Programmable logic device having quadrant layout
US6215326B1 (en) 1998-11-18 2001-04-10 Altera Corporation Programmable logic device architecture with super-regions having logic regions and a memory region
US6693456B2 (en) * 2000-08-04 2004-02-17 Leopard Logic Inc. Interconnection network for a field programmable gate array

Also Published As

Publication number Publication date
AU2002347046A1 (en) 2003-04-22
CA2461540A1 (en) 2003-04-17
EP1433257A2 (en) 2004-06-30
JP2005505978A (ja) 2005-02-24
EP1433257B1 (en) 2013-09-11
WO2003032492A2 (en) 2003-04-17
WO2003032492A3 (en) 2004-02-26
CA2461540C (en) 2005-08-30
US6594810B1 (en) 2003-07-15

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