JP4176615B2 - Digital amplifier - Google Patents

Description

  The present invention relates to a ΔΣ modulator and a ΔΣ modulator such as a 1-bit ADC (Analog-to-Digital Converter) and a 1-bit DAC (Digital-to-Analog Converter). The present invention relates to a digital amplifier such as a 1-bit digital amplifier provided.

  Conventionally, there are many devices that perform audio reproduction and signal processing using ΔΣ modulation. For example, a ΔΣ modulator such as a 1-bit ADC (Analog-to-Digital Converter) or a 1-bit DAC (Digital-to-Analog Converter) is a typical one.

  There is also a digital amplifier such as a 1-bit digital amplifier that performs sound reproduction by switching a constant voltage using a 1-bit signal obtained by ΔΣ modulation as a control signal, and passing the switching-amplified signal through a low-pass filter.

  The ΔΣ modulation used in these ΔΣ modulators and digital amplifiers inputs an input signal that is ΔΣ-modulated and obtains a 1-bit signal.

  A conventional general circuit of the above-described ΔΣ modulator is disclosed in Patent Document 1 and the like. For example, as shown in FIG. 5, for example, a seventh-order ΔΣ modulator circuit in which seven stages of integrators I1 to I7 are cascade-connected. Thus, negative feedback is provided from the quantizer Q to the first-stage integrator I1 via the delay unit Z.

  On the other hand, a 1-bit digital amplifier that switches a constant voltage by using a ΔΣ modulator, for example, receives a signal output from a quantizer Q (described later) of a ΔΣ modulator 102, which is a ΔΣ modulator, as shown in FIG. As a control signal, a constant voltage from the constant voltage power source 104 is switched and amplified by a switching unit 103 that forms a bridge circuit with an element capable of high-speed switching such as a power MOSFET. The switching-amplified signal passes through the low-pass filter 105, becomes an analog audio signal, and is reproduced. The signal output from the switching unit 103 is attenuated by the attenuator 106 and negatively fed back to the first-stage integrator I1 of the ΔΣ modulation unit 102 through the delay unit 107 and the adder 101.

For example, as shown in FIG. 7, the ΔΣ modulation unit 102 is a seventh-order ΔΣ modulation circuit in which integrators I1 to I7 are cascade-connected in seven stages, and a 1-bit signal is output from the quantizer Q. It has become so.
JP 2000-2224040 A (released on August 11, 2000)

  However, in the conventional seventh-order ΔΣ modulation circuit shown in FIG. 5, when the output from the quantizer G is negatively fed back to the first-stage integrator I1 and the ΔΣ modulation operation is started, a plurality of integrations constituting the ΔΣ modulation circuit are performed. The ΔΣ modulation operation starts when the outputs of the devices I1 to I7 are indefinite.

  Similarly, in the digital amplifier shown in FIG. 6, the output of the quantizer Q shown in FIG. 7 is switched and amplified by the switching unit 103 which is a switching amplification means, and this switching amplification signal is attenuated through the attenuator 106, Even when the attenuated pulse signal is negatively fed back to the first-stage integrator I1 to start the ΔΣ modulation operation, the outputs of the plurality of integrators I1 to I7 constituting the ΔΣ modulation circuit are in an indefinite state. The modulation operation is started.

  As can be seen from FIGS. 5 and 7, the quantizer Q serving as the output stage of the 1-bit digital signal in the ΔΣ modulation circuit receives a signal obtained by adding the outputs of the integrators I1 to I7. Here, when the output of the adder K5 input to the quantizer Q is input at a large level that is positive or negative with respect to the quantization threshold, data is output to the output of the quantizer Q for several tens of microseconds. It appears as a DC component without switching.

  For example, when a level that is positively larger than the quantization threshold is input, “1” appears at the output of the quantizer Q for several tens of μsec. On the other hand, when a negatively large level is input, “0” appears for several tens of microseconds at the output of the quantizer.

  This phenomenon converges and stabilizes due to the negative feedback of ΔΣ modulation, but the ΔΣ modulation circuit instantaneously oscillates, causing device latch-up and causing noise and overcurrent. Has a problem.

  The present invention has been made in view of the above-described conventional problems. The object of the present invention is to perform a stable modulation operation at the start of the ΔΣ modulation operation, to avoid the oscillation state of the ΔΣ modulation circuit, and to prevent noise and noise. It is an object of the present invention to provide a ΔΣ modulator and a digital amplifier that can avoid current generation.

  In order to solve the above-described problem, the ΔΣ modulator of the present invention is a high-order ΔΣ modulator including cascaded multistage integrators, and each integration is performed as a reset operation when starting the ΔΣ modulation operation. It is characterized in that an integrator output control means is provided to make all the outputs of the generator zero.

  In order to solve the above problems, the digital amplifier according to the present invention provides a switching amplification means for outputting the output of the quantizer in a delta-sigma modulation circuit including a cascaded multistage integrator and a quantizer. At the same time, the output signal amplified by switching is output through the low-pass filter to the analog reproduction signal. At the same time, the pulse output signal amplified by switching is attenuated by passing through an attenuator. In the digital amplifier that negatively feeds back to the first-stage integrator of the ΔΣ modulation circuit, all the outputs of the integrators of the ΔΣ modulation circuit are all set to 0 before the switching amplification by the switching amplification means is started. An integrator output control means for outputting is provided.

In order to solve the above problems, the digital amplifier according to the present invention provides a switching amplification means for outputting the output of the quantizer in a delta-sigma modulation circuit including a cascaded multistage integrator and a quantizer. At the same time, the output signal amplified by switching is output through the low-pass filter to the analog reproduction signal. At the same time, the pulse output signal amplified by switching is attenuated by passing through an attenuator. In the digital amplifier for negative feedback to the first-stage integrator of the ΔΣ modulation circuit, the ΔΣ modulation circuit is:
A feedback path that negatively feeds back the output of the quantizer to the first-stage integrator; and a switching control means that is provided in the path of the feedback circuit and that can control connection / disconnection of the path. Before starting the switching amplification by the switching amplification means, the feedback path is connected so that the output of the quantizer can be negatively fed back, and immediately after the switching amplification is started, the feedback path is disconnected. It is characterized by.

  In the ΔΣ modulation apparatus of the present invention, the integrator output control means sets all the outputs of the integrators to 0 output as a reset operation when starting the ΔΣ modulation operation.

  Therefore, the output of the quantizer of the ΔΣ modulation circuit is negatively fed back to the first-stage integrator, and when the ΔΣ modulation operation is started, the addition signal of each integrator output input to the quantizer is Since the level is almost the same as the quantization threshold value, a ΔΣ modulation operation that has already converged and stabilized can be performed, and the ΔΣ modulation circuit does not oscillate when the operation starts.

  Therefore, a stable modulation operation can be performed at the start of the ΔΣ modulation operation, an oscillation state of the ΔΣ modulation circuit can be avoided, and a ΔΣ modulation device that can avoid noise and overcurrent can be provided.

  In the digital amplifier of the present invention, the integrator output control means also outputs the output of each integrator of the ΔΣ modulation circuit before starting the switching amplification by the switching amplification means for the ΔΣ modulation circuit constituting the digital amplifier. Set all outputs to 0.

  Therefore, when the ΔΣ modulation operation is started, the added signal of each integrator output input to the quantizer is almost the same level as the quantization threshold of the quantizer, so it has already converged and stabilized. The ΔΣ modulation operation can be performed, and the ΔΣ modulation circuit does not oscillate at the start of operation, and as a digital amplifier, the generation of noise and overcurrent due to the oscillation state can be eliminated.

  Therefore, a stable modulation operation can be performed at the start of the ΔΣ modulation operation, an oscillation state of the ΔΣ modulation circuit can be avoided, and a digital amplifier capable of avoiding noise and overcurrent can be provided.

  Further, in the digital amplifier of the present invention, the output of the quantizer of the ΔΣ modulation circuit is negatively supplied to the first-stage integrator through switching control means capable of connection / disconnection control, that is, ON / OFF control. Before starting switching amplification, the switching control means is turned on so that the quantizer output can be negatively fed back. Immediately after switching amplification is started, the feedback path for the negative feedback of the quantizer output is provided. The switching control means is turned OFF so as to cut off.

  Therefore, even in this method, when starting the ΔΣ modulation operation, the ΔΣ modulation circuit has already received a negative feedback from the quantizer, and is in a stable operation region in which a converged and stable ΔΣ modulation operation is performed. It is possible to shift to the ΔΣ modulation operation by negative feedback from the switching amplification means while maintaining the stable operation region. Therefore, at the time of delta-sigma modulation operation transition by negative feedback from the switching amplifier means, that is, at the start of delta-sigma modulation operation of the delta-sigma modulation circuit constituting the digital amplifier, the oscillation state does not occur, and noise and overcurrent are generated due to the oscillation state Can be eliminated.

  Therefore, it is possible to provide a digital amplifier capable of performing a stable modulation operation at the start of the ΔΣ modulation operation, avoiding the oscillation state of the ΔΣ modulation circuit, and avoiding noise and overcurrent generation.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, the seventh-order ΔΣ modulation circuit 10 as the ΔΣ modulation device according to the present embodiment is formed by cascade-connecting integrators I1 to I7, and each of the integrators I1 to I7. The outputs are added by an adder K5, and a 1-bit signal is output from the quantizer Q. In the seventh-order ΔΣ modulation circuit 10, the output of the quantizer Q is returned to the adder K1 via the delay unit Z, so that the 1-bit signal from the quantizer Q is negatively fed back to the first-stage integrator I1. It has become so. In the present embodiment, the integrators I1 to I7 are cascade-connected in seven stages. However, the present invention is not limited to this, and other plural stages may be used.

  Here, in the seventh-order ΔΣ modulation circuit 10 of the present embodiment, the outputs of the integrators I1 to I7 are grounded 11 via the switches SW1 to SW7. The switches SW1 to SW7 and the ground 11 have a function as integrator output control means of the present invention. Thereby, by turning on the switches SW1 to SW7 with respect to the outputs of the cascaded integrators I1 to I7, the outputs of the integrators I1 to I7 become zero potential.

  The switches SW1 to SW7 are ON / OFF controlled substantially simultaneously. As for the timing, the power supply voltage is supplied and the output of the quantizer Q is negatively fed back to the first-stage integrator I1 and is turned on simultaneously with the start of the ΔΣ modulation operation, while the integrator I1 is turned on by turning on the switches SW1 to SW7. Turns OFF immediately after setting the output of ~ I7 to 0 potential. Alternatively, the power supply voltage is already turned on when the power supply voltage is supplied, and can be turned off immediately after the outputs of the integrators I1 to I7 are set to zero potential.

  Here, the zero potential is the same as the quantization threshold level of the quantizer Q. When the seventh-order ΔΣ modulation circuit 10 operates with ± power supply voltage, it is the GND potential, and when it operates with single power supply voltage Vdd. Is preferably Vdd / 2. The power supply voltage indicates a power supply voltage (not shown) supplied for operating the ΔΣ modulation circuit. As described above, this power supply voltage may be ± power supply or single power supply.

  In this way, the output of the adder K5 that adds the outputs of the integrators I1 to I7 at the start of the ΔΣ modulation operation can be made substantially the same level as the quantization threshold value of the quantizer Q. A stable modulation operation can be performed from the start of the operation.

  As described above, in the seventh-order ΔΣ modulation circuit 10 of the present embodiment, all outputs of the integrators I1 to I7 are output as 0 by the switches SW1 to SW7 and the ground 11 as a reset operation when the ΔΣ modulation operation is started. To be.

  Therefore, the output of the quantizer Q of the seventh-order ΔΣ modulation circuit 10 is negatively fed back to the first-stage integrator I1, and when the ΔΣ modulation operation is started, the integrators I1 to I7 input to the quantizer Q are started. Since the output addition signal is substantially at the same level as the quantization threshold value of the quantizer Q, the already-converged and stable ΔΣ modulation operation can be performed, and the seventh-order ΔΣ modulation circuit 10 oscillates when the operation starts. Will not cause.

Accordingly, it is possible to provide a seventh-order ΔΣ modulation circuit 10 that can perform a stable modulation operation at the start of the ΔΣ modulation operation, can avoid the oscillation state of the seventh-order ΔΣ modulation circuit 10, and can avoid noise and overcurrent generation. it can.
[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted.

  In the present embodiment, a digital amplifier provided with a ΔΣ modulation device will be described.

  As shown in FIG. 2, a 1-bit digital amplifier 20 as a digital amplifier according to the present embodiment includes an adder K1, a ΔΣ modulation unit 21, a switching unit 22, a constant voltage power supply 23, a low-pass filter 24, It comprises an attenuator 25 and a delay unit 26. The switching unit 22 and the constant voltage power source 23 have a function as the switching amplification means of the present invention.

  In the 1-bit digital amplifier 20, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or the like is used with a signal output from a quantizer Q (described later) of the ΔΣ modulator 21 as a control signal. The constant voltage from the constant voltage power supply 23 is amplified by switching by the switching unit 22 having a bridge circuit composed of elements capable of high-speed switching. The switching-amplified signal passes through the low-pass filter 24, becomes an analog audio signal, and is reproduced.

  The signal output from the switching unit 22 is attenuated by the attenuator 25, passes through the delay unit 26, and is returned to the adder K1, thereby negative feedback to the first-stage integrator I1 (described later) of the ΔΣ modulation unit 21. Is done.

  As shown in FIG. 3, the ΔΣ modulation unit 21 includes, for example, a seventh-order ΔΣ modulation circuit 30. That is, the seventh-order ΔΣ modulation circuit 30 is composed of cascaded integrators I1 to I7, and the outputs of the integrators I1 to I7 are added by the adder K5, and the quantizer Q A 1-bit signal is output. However, the seventh-order ΔΣ modulation circuit 30 does not have a negative feedback loop for negatively feeding back the output of the quantizer Q to the first-stage integrator I1. In the present embodiment, the integrators I1 to I7 are cascade-connected in seven stages. However, the present invention is not limited to this, and other plural stages may be used.

  Here, in the seventh-order ΔΣ modulation circuit 30 of the present embodiment, the outputs of the integrators I1 to I7 are grounded 31 via the switches SW1 to SW7. The switches SW1 to SW7 and the ground 31 have a function as integrator output control means of the present invention. Thereby, by turning on the switches SW1 to SW7 with respect to the outputs of the cascaded integrators I1 to I7, the outputs of the integrators I1 to I7 become zero potential.

  The switches SW1 to SW7 are ON / OFF controlled substantially simultaneously. As the timing, first, when the power supply voltage is supplied to the ΔΣ modulator 21, it is turned on substantially simultaneously, and the outputs of the integrators I1 to I7 are set to zero potential. Then, the constant voltage from the constant voltage power supply 23 is supplied to the switching unit 22 and turns OFF at the same time. Here, the zero potential is the same as the quantization threshold level of the quantizer Q. When the seventh-order ΔΣ modulation circuit 30 operates with ± power supply voltage, it is the GND potential and operates with the single power supply voltage Vdd. If so, Vdd / 2 is recommended. After turning off the switches SW1 to SW7, as shown in FIG. 2, the switching amplified signal passes through the attenuator 25 and the delay unit 26, and the first-stage integrator of the seventh-order ΔΣ modulation circuit 30 which is the ΔΣ modulation unit 21. Negative feedback to I1 starts ΔΣ modulation for the input signal.

  By doing this, at the start of the ΔΣ modulation operation, the output of the adder K5 that adds the outputs of the integrators I1 to I7 can be made substantially the same level as the quantization threshold of the quantizer Q, and ΔΣ A stable modulation operation can already be performed from the start of the modulation operation.

  Here, in the seventh-order ΔΣ modulation circuit 30, the outputs of the integrators I1 to I7 are turned on by grounding 31 the outputs of the integrators I1 to I7 via the switches SW1 to SW7, thereby turning on the switches SW1 to SW7. Is set to 0 potential.

  However, in order to obtain an equivalent effect by setting the output of the adder K5, which adds the outputs of the integrators I1 to I7 at the start of the ΔΣ modulation operation, to substantially the same level as the quantization threshold of the quantizer Q. Does not necessarily require the respective outputs of the integrators I1 to I7 to be at zero potential.

  For example, as shown in FIG. 4, a feedback path 41 for returning from the quantizer Q to the adder K1 is provided, and the delay path Z and a switch SW0 as switching control means are provided in the feedback path 41, and this switch SW0. It is possible to provide a seventh-order ΔΣ modulation circuit 40 that controls ON / OFF.

  The timing for ON / OFF control of the switch SW0 in the seventh-order ΔΣ modulation circuit 40 is as follows.

  First, a power supply voltage is supplied to the ΔΣ modulator 21 shown in FIG. At this time, the switch SW0 is closed and turned on. When the constant voltage from the constant voltage power supply 23 is supplied to the switching unit 22 and the switching amplified signal passes through the attenuator 25 and the delay unit Z and is negatively fed back to the first-stage integrator I1 of the ΔΣ modulation unit 21. At the same time, the switch SW0 is turned off.

  As described above, since the power supply voltage is supplied to the ΔΣ modulation unit 21 and the switch SW0 is turned on, before the constant voltage is supplied to the switching unit 22 and the switching amplification is performed, the seventh-order ΔΣ modulation circuit 40 has already been supplied. Is in the stable operation region, and when the switch SW0 is turned OFF while performing the stable operation, it can shift to the ΔΣ modulation operation by negative feedback from the switching unit 22.

  As described above, in the 1-bit digital amplifier 20 according to the present embodiment, the switches SW1 to SW7 and the ground 31 are connected to the switching unit 22 and the constant in the ΔΣ modulation unit 21, that is, the seventh-order ΔΣ modulation circuit 30 constituting the digital amplifier. Before starting the switching amplification by the voltage power supply 23, the outputs of the integrators I1 to I7 of the seventh-order ΔΣ modulation circuit 30 are all set to zero.

  Therefore, when the ΔΣ modulation operation is started, the added signals of the integrators I1 to I7 input to the quantizer Q are at substantially the same level as the quantization threshold of the quantizer Q. A converged and stable ΔΣ modulation operation can be performed, and the seventh-order ΔΣ modulation circuit 30 does not oscillate at the start of operation, and as a digital amplifier, generation of noise and overcurrent due to the oscillation state can be eliminated.

  Therefore, it is possible to provide a 1-bit digital amplifier 20 that can perform a stable modulation operation at the start of the ΔΣ modulation operation, can avoid the oscillation state of the seventh-order ΔΣ modulation circuit 30, and can avoid noise and overcurrent generation. .

  Further, in the 1-bit digital amplifier 20 of the present embodiment, the output of the quantizer Q of the seventh-order ΔΣ modulation circuit 40 is turned on / off for the ΔΣ modulation unit 21, that is, the seventh-order ΔΣ modulation circuit 40 constituting the digital amplifier. A feedback path 41 is provided for negative feedback to the first-stage integrator I1 through the switch SW0 that can be turned off. Before starting the switching amplification, the switch SW0 is turned on so that the quantizer Q can perform negative feedback, and the switching amplification is performed. After the start, the switch SW0 is turned OFF so that the feedback path 41 of the negative feedback of the output of the quantizer Q is cut.

  Therefore, also in this method, when the ΔΣ modulation operation is started, the seventh-order ΔΣ modulation circuit 40 has already received a negative feedback from the quantizer Q and enters a stable operation region in which a converged and stable ΔΣ modulation operation is performed. Thus, it is possible to shift to the ΔΣ modulation operation by negative feedback from the switching unit 22 while maintaining the stable operation region. Therefore, at the time of transition to the ΔΣ modulation operation due to the negative feedback from the switching unit 22, that is, at the start of the ΔΣ modulation operation of the seventh-order ΔΣ modulation circuit 40 constituting the digital amplifier, the oscillation state does not occur, and noise and excess due to the oscillation state are not caused. Generation of current can be eliminated.

  Therefore, it is possible to provide a 1-bit digital amplifier 20 that can perform a stable modulation operation at the start of the ΔΣ modulation operation, can avoid the oscillation state of the seventh-order ΔΣ modulation circuit 40, and can avoid noise and overcurrent generation. .

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and the present invention can be obtained by appropriately combining technical means disclosed in different embodiments. Such embodiments are also included in the technical scope of the present invention.

  The present invention can be used for a ΔΣ modulation apparatus and a digital amplifier that obtain a 1-bit signal by ΔΣ modulation and perform audio reproduction or the like using the 1-bit signal.

FIG. 3 is a circuit diagram showing a seventh-order ΔΣ modulation circuit as a ΔΣ modulation device according to the present invention. FIG. 10 is a block diagram illustrating another embodiment of the present invention and illustrating a configuration of a 1-bit digital amplifier. FIG. 3 is a circuit diagram showing a configuration of a ΔΣ modulation unit in the 1-bit digital amplifier and showing a seventh-order ΔΣ modulation circuit. FIG. 10 is a circuit diagram showing another configuration of the ΔΣ modulation unit in the 1-bit digital amplifier, showing a seventh-order ΔΣ modulation circuit. It is a circuit diagram which shows the structure of the conventional 7th order delta-sigma modulation circuit. It is a block diagram which shows the structure of the conventional 1 bit digital amplifier. FIG. 3 is a circuit diagram showing a configuration of a ΔΣ modulation unit in the 1-bit digital amplifier and showing a seventh-order ΔΣ modulation circuit.

Explanation of symbols

10 7th-order ΔΣ modulation circuit 11 Grounding (integrator output control means)
I1 to I7 Integrator 20 1-bit digital amplifier (digital amplifier)
21 ΔΣ modulator 22 Switching unit (switching amplification means)
23 Constant voltage power supply (switching amplification means)
24 Low-pass filter 25 Attenuator 26 Delay device 30 7th-order ΔΣ modulation circuit 31 Ground 40 7th-order ΔΣ modulation circuit 41 Feedback path K1 to K5 Adder Q Quantizer SW0 Switch (switching control means)
SW1 to SW7 switch (integrator output control means)

Claims (1)

The output of the quantizer in a delta-sigma modulation circuit having a cascaded multistage integrator and a quantizer is switching-amplified by a switching amplification means, and the switching-amplified output signal is passed through a low-pass filter. In the digital amplifier that outputs the analog reproduction signal and simultaneously attenuates the switching amplified pulse output signal through an attenuator and negatively feeds back the attenuated pulse output signal to the first-stage integrator of the ΔΣ modulation circuit.
The ΔΣ modulation circuit is
A feedback path for negatively feeding back the output of the quantizer to the first-stage integrator;
While provided with a switching control means provided in the return path and capable of controlling connection / disconnection of the path,
The switching control means sets the feedback path in a connected state so that the output of the quantizer can be negatively fed back before starting the switching amplification by the switching amplification means, while immediately after starting the switching amplification, A digital amplifier characterized by having a disconnected state.

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