JP2008042521A - Current glitch reducing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current glitch reducing circuit capable of reducing a glitch without reducing a dynamic range, increasing the number of elements, and increasing an offset due to element relative variance. <P>SOLUTION: In a current mirror circuit having an input transistor M1 and an output transistor M2, a switching transistor M3 is connected in series between a control electrode of the input transistor M1 and a control electrode of the output transistor M2 to form a current path. Further, a capacitor C1 is provided which has one terminal connected to the control electrode of the output transistor M2 and the other terminal grounded. Then a binary control signal is input to a control electrode of the switching transistor M3 to control its ON/OFF operation. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a current glitch reduction circuit for reducing a glitch included in an input signal.

  A binary-type current DAC (DAC: Digital to Analog Converter), which is one of D / A converters, generates a glitch due to a time difference at which each bit is switched during current switching.

  For example, if a glitch is output from the current DAC that drives the laser in the optical disk drive, the laser outputs with a power different from the desired power, and accurate data cannot be written to the optical disk or data is erased. In addition, lasers can lead to destruction.

In order to reduce the glitch, for example, it is conceivable to output the output of the current DAC through a constant current circuit having noise resistance. As a constant current circuit having noise resistance, for example, in a current mirror circuit having an input transistor and an output transistor, a low-pass filter (hereinafter also referred to as LPF) is provided between the base electrode of the input transistor and the base electrode of the output transistor. Some are provided to remove high-frequency noise (see, for example, Patent Document 1).
JP-A-3-65715

  However, since the constant current circuit always transmits a signal to the LPF, the time constant must be increased. Therefore, the switching settling time becomes long.

  In addition, since current must be converted into voltage, I / V and V / I conversion circuits are required. As a result, problems such as reduction in dynamic range, increase in the number of elements, and increase in offset due to relative variations in elements occur. It is possible to do.

  The present invention has been made paying attention to the above problems, and the switching settling time is not lengthened, and the glitch can be reduced without reducing the dynamic range, increasing the number of elements, and increasing the offset due to element relative variation. An object is to provide a current glitch reduction circuit.

In order to solve the above problems, one embodiment of the present invention provides:
A current glitch reduction circuit for reducing a glitch included in an input signal,
A current mirror circuit having an input transistor for receiving the input signal and an output transistor;
A switching transistor connected in series so as to form a current path between the control electrode of the input transistor and the control electrode of the output transistor, and having one terminal connected to the output of the binary control signal. A sample-and-hold circuit having a capacitance connected between the control electrodes of the transistor and having the other terminal grounded;
It is provided with.

  According to the present invention, the S / H circuit is inserted into the gate (base) coupling portion of the current mirror circuit, so that during the period when there is a glitch, the current held by the S / H circuit is used to output the current mirror circuit. Since the current can be held, the switching settling time is not lengthened, and the glitch can be reduced without reducing the dynamic range, increasing the number of elements, and increasing the offset due to the relative variation of the elements.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of each embodiment, components having the same functions as those described once are given the same reference numerals and description thereof is omitted.

Embodiment 1 of the Invention
FIG. 1 is a diagram showing a configuration of a current glitch reduction circuit 100 according to Embodiment 1 of the present invention. The current glitch reduction circuit 100 is a circuit that reduces the current glitch of the current output by the current DAC 110 (binary current DAC).

  In this example, the current DAC 110 includes constant current sources I1 and I2 and switches SW1 and SW2. The constant current source I1 is a constant current source with an output of 10 μA, and the constant current source I2 is a constant current source with an output of 20 μA. One terminal of the switch SW1 is connected to the output of the constant current source I1, and one terminal of the switch SW2 is connected to the output of the constant current source I2. The other terminal of the switch SW1 and the other terminal of the switch SW2 are connected to each other. That is, by switching the switch SW1 and the switch SW2, a four-stage output current (Iout) can be obtained.

(Configuration of Current Glitch Reduction Circuit 100)
As shown in FIG. 1, the current glitch reduction circuit 100 includes an input transistor M1, an output transistor M2, a switching transistor M3, and a capacitor C1.

  The input transistor M1 is an NMOS transistor, and the output of the current DAC 110 is supplied to the drain and gate, and the source is grounded.

  The output transistor M2 is an NMOS transistor, the drain is connected to the external terminal, and the source is grounded.

  The switching transistor M3 is an NMOS transistor, the drain is connected to the gate of the input transistor M1, and the source is connected to the gate of the output transistor M2.

  Therefore, when a predetermined voltage is applied to the gate of the switching transistor M3 and the switching transistor M3 is turned on, the gates of the input transistor M1 and the output transistor M2 are connected to each other. A circuit is constructed. When the switching transistor M3 is on, the Ids of the input transistor M1 (Ids is the drain current) and the Ids of the output transistor M2 are the L / W value of the input transistor M1 (L is the gate length, W is the gate width W) , Which is equal to the ratio with the L / W value of the output transistor M2. That is, if the L / W values of the input transistor M1 and the output transistor M2 are the same, the output current Iout of the current DAC 110 and the Ids of the output transistor M2 are equal.

  On the other hand, one end of the capacitor C1 is connected to the source of the switching transistor M3. The other terminal of the capacitor C1 is grounded. That is, the switching transistor M3 and the capacitor C1 constitute a sample and hold circuit (hereinafter also referred to as an S / H circuit).

(Operation of Current Glitch Reduction Circuit 100)
The current glitch reduction circuit 100 is exemplified when the switch SW1 is turned on and the switch SW2 is turned off, and when the switch SW1 is turned off and the switch SW2 is turned on, that is, when the output current Iout is switched from 10 μA to 20 μA. The operation of will be described.

  First, when the output current Iout is 10 μA, that is, when the switch SW1 is on and the switch SW2 is off, the switching transistor M3 is turned on. Thereby, the capacitor C1 is charged.

  Next, when the output current Iout of the current DAC 110 is switched from 10 μA to 20 μA, the switching transistor M3 is turned off before switching, and then the switch SW1 and the switch SW2 are switched.

  It is impossible to switch the switch SW1 and the switch SW2 at the same time due to factors such as wiring delay on an actual circuit. In general, there is a period in which both the switches SW1 and SW2 are on or both are off for several tens of nsec. When both are on, the output current Iout is 30 μA, and when both are off, the output current Iout is 0 μA, which is a glitch output.

  In the current glitch reduction circuit 100, if the L / W values of the input transistor M1 and the output transistor M2 are the same, the charge charged in the capacitor C1 when the switching transistor M3 is turned off immediately before switching the switches SW1 and SW2. Thus, the gate potential of the output transistor M2 is held, and the Ids of the output transistor M2 remains at 10 μA.

  When the switching transistor M3 is turned on after the switching of the switches SW1 and SW2, the current mirror circuit is constituted again by the input transistor M1 and the output transistor M2, and the output current of the output transistor M2 is the output of the constant current source I2. That is, the output current Iout is 20 μA.

  As described above, since the switching transistor M3 is turned off when the switches SW1 and SW2 are switched, the gate potential of the output transistor M2 is held by the charge charged in the capacitor C1. That is, the period during which a glitch (30 μA or 0 μA current in the above example) is output can be eliminated, and the output current Iout can be switched smoothly. In addition, a wider dynamic range can be obtained than when I / V conversion is performed using a resistor and buffering it, and further, the number of elements can be greatly reduced, so that offset factors due to relative variations in elements can be reduced. . In addition, since the S / H circuit only requires time to charge the hold capacitor, the operation state can be switched at a high speed with a smaller capacity than the LPF. That is, the switching settling time does not become long.

<< Embodiment 2 of the Invention >>
FIG. 2 is a diagram showing a configuration of a current glitch reduction circuit 200 according to Embodiment 2 of the present invention. The current glitch reduction circuit 200 is configured by adding a unity gain amplifier A1 (voltage follower) to the current glitch reduction circuit 100 of the first embodiment.

  The unity gain amplifier A1 is an amplifier having a slew rate faster than the hold time of the S / H circuit, and is connected between the input transistor M1 and the switching transistor M3. For example, the unity gain amplifier A1 can be composed of an operational amplifier. In this case, one input terminal of the operational amplifier is connected to the gate (control electrode) of the input transistor M1, and the other input terminal and the output terminal are connected to the drain (current input electrode) of the switching transistor M3. .

  In the present embodiment, a current DAC 210 is connected as a binary current DAC. The current DAC 210 includes more constant current sources and switches than the current DAC 110. That is, this is an example in which the number of bits is larger than that of the current DAC of the first embodiment.

  As described above, by connecting the unity gain amplifier A1 before the capacitor C1 of the S / H circuit, in this embodiment, charging and discharging of the capacitor C1 can be performed stably.

  In other words, when the number of bits of the current DAC is large, or when there is a large difference in the current value between the bits of the current DAC, without the unity gain amplifier A1, when switching from a large current to a small current, When switching, the time for charging and discharging the capacitor C1 becomes long. However, the unity gain amplifier A1 having a slew rate faster than the hold time is connected for charging / discharging before the capacitance C1 of the S / H circuit, so that the charging / discharging time becomes equal in any switching, The glitch can be eliminated by the S / H circuit.

<< Embodiment 3 of the Invention >>
FIG. 3 is a diagram showing a configuration of a current glitch reduction circuit 300 according to Embodiment 3 of the present invention. The current glitch reduction circuit 300 is configured by adding an NMOS transistor M4 to the current glitch reduction circuit 100 of the first embodiment.

  The drain of the NMOS transistor M4 is connected to the terminal on the opposite side of the ground side terminal of the capacitor C1, and the source is grounded.

  With the above configuration, when it is desired to quickly set the output of the output transistor M2 to 0 μA, by applying a predetermined potential to the gate of the NMOS transistor M4, the charge charged in the capacitor C1 is quickly discharged by the NMOS transistor M4. Can do.

<< Embodiment 4 of the Invention >>
FIG. 4 is a diagram showing a configuration of a current glitch reduction circuit 400 according to Embodiment 4 of the present invention. The current glitch reduction circuit 400 is configured by adding an NMOS transistor M4 to the current glitch reduction circuit 200 of the second embodiment.

  Also in this embodiment, the NMOS transistor M4 has a drain connected to a terminal opposite to the ground side terminal of the capacitor C1, and a source grounded.

  Therefore, also in this embodiment, when it is desired to quickly set the output of the output transistor M2 to 0 μA, by applying a predetermined potential to the gate of the NMOS transistor M4, the charge charged in the capacitor C1 is quickly transferred by the NMOS transistor M4. It can be discharged.

  Each of the above embodiments is an example in which an Nch CMOS transistor is used as a transistor. However, this can be replaced with a Pch MOS transistor or a bipolar transistor.

  In the current glitch reduction circuit according to the present invention, an S / H circuit is inserted into the gate (base) coupling portion of the current mirror circuit, so that during the period when the glitch is present, the current held by the S / H circuit is Since the output current of the mirror circuit can be maintained, the switching settling time is not lengthened, and the glitch can be reduced without reducing the dynamic range, increasing the number of elements, and increasing the offset due to element relative variation. This is useful as a current glitch reduction circuit or the like that reduces glitches included in a signal output from a DAC circuit or the like.

1 is a diagram illustrating a configuration of a current glitch reduction circuit according to Embodiment 1. FIG. It is a figure which shows the structure of the current glitch reduction circuit which concerns on Embodiment 2. FIG. It is a figure which shows the structure of the current glitch reduction circuit which concerns on Embodiment 3. FIG. It is a figure which shows the structure of the current glitch reduction circuit which concerns on Embodiment 4. FIG.

Explanation of symbols

100 current glitch reduction circuit 110 current DAC
200 Current glitch reduction circuit 210 Current DAC
300 Current glitch reduction circuit 400 Current glitch reduction circuit SW1-SW2 switch
A1 unity gain amplifier
C1 capacity I1-In constant current source
M1 input transistor
M2 output transistor
M3 switching transistor
M4 NMOS transistor

Claims (5)

A current glitch reduction circuit for reducing a glitch included in an input signal,
A current mirror circuit having an input transistor for receiving the input signal and an output transistor;
A switching transistor connected in series so as to form a current path between the control electrode of the input transistor and the control electrode of the output transistor, and having one terminal connected to the output of the binary control signal. A sample-and-hold circuit having a capacitance connected between the control electrodes of the transistor and having the other terminal grounded;
A current glitch reduction circuit comprising: The current glitch reduction circuit of claim 1, comprising:
In addition, it has a voltage follower,
The voltage follower has a slew rate faster than the hold time of the sample hold circuit, an input terminal is connected to the control electrode of the input transistor, and an output terminal is connected to the current input electrode of the switching transistor. Current glitch reduction circuit. The current glitch reduction circuit of claim 2,
The voltage follower is an operational amplifier, wherein one input terminal is connected to the control electrode of the input transistor, and the other input terminal and the output terminal are connected to the current input electrode of the switching transistor. A current glitch reduction circuit. The current glitch reduction circuit of claim 1, comprising:
The current glitch reduction circuit further comprises a transistor having one terminal connected to the control electrode of the output transistor, the other terminal grounded, and a binary control signal input to the control electrode. The current glitch reduction circuit of claim 2,
The current glitch reduction circuit further comprises a transistor having one terminal connected to the control electrode of the output transistor, the other terminal grounded, and a binary control signal input to the control electrode.

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