JP2006191176A - Switching amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching amplifier adaptable to a digital input which is reduced in power consumption and circuit area. <P>SOLUTION: The switching amplifier 10 is configured so that the output of a DAC 12 is directly transmitted to the switching amplifier 13 adaptable to an analog input, and the signal transfer function between an input and an output becomes the characteristic of a low pass filter. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  Inputs the digital modulator that converts multi-bit digital signals into low-bit oversampled digital signals, the digital-analog converter that converts the low-bit digital signals into analog signals, and the output of the digital-analog converter The present invention relates to a digital input compatible switching amplifier.

  Audio information is digitally stored in currently widely used audio devices. In order to drive the speaker, the stored information is converted into an analog audio signal by a digital-to-analog converter (DAC: Digital To Analog Converter). Furthermore, a switching amplifier is used to realize a high efficiency amplifier.

  FIG. 10 shows one configuration of a switching amplifier 200 which is a conventional digital input compatible switching amplifier (see Non-Patent Document 1). The switching amplifier 200 includes a digital delta sigma modulator (hereinafter referred to as a ΔΣ modulator) 201, a DAC 202, and an analog input corresponding switching amplifier 203.

  In the switching amplifier 200, the multi-bit m-bit digital input signal is converted into a low-bit digital signal, here, a 1-bit signal by the digital ΔΣ modulator 201, and the 1-bit signal is converted into an analog signal by the DAC 202. The analog input compatible switching amplifier 203 converts the analog signal generated by the DAC 202 into a 1-bit signal, and amplifies the signal by controlling the power switch in the analog input compatible switching amplifier 203 using the generated 1-bit signal. And output as an analog output signal.

  Further, like the switching amplifier 300 shown in FIG. 11, in order to attenuate noise outside the audio band in the digital ΔΣ modulator 201, the output of the DAC 202 is analog input through a low-pass filter (hereinafter referred to as LPF: Low Pass Filter) 303. There is also a configuration for transmitting to the corresponding switching amplifier 203 (see, for example, Patent Document 1).

As conventionally known, by using a multi-bit output instead of a 1-bit output, the quantization noise of the digital ΔΣ modulator can be reduced and the stability of the digital ΔΣ modulator can be increased. FIG. 12 shows a block diagram of a switching amplifier 400 which is a conventional digital input compatible switching amplifier using the effect (see Non-Patent Document 2). The switching amplifier 400 shown in the figure includes a digital ΔΣ modulator 401, a DAC 402, an LPF 403, and an analog input corresponding switching amplifier 404. The m-bit digital input signal is converted by the digital ΔΣ modulator 401 into an n-bit digital signal (m>n> 1) as a low-bit digital signal. The generated n-bit digital signal is converted into an analog signal through the DAC 402 and the LPF 403. The analog input compatible switching amplifier 404 converts the analog signal generated by the DAC 402 into a 1-bit signal, and amplifies the signal by controlling the power switch in the analog input compatible switching amplifier 404 using the generated 1-bit signal. Output as an analog output signal.
US Pat. No. 5,396,244 (published March 7, 1995) PowerDAC: A Single-Chip Audio DAC with a 70% -Efficient Power Stage in 0.5μm CMOS, Kathleen Philips et al., Proceedings of International Solid-State Circuits Conference 1999, February 1999, Paper 8.5 Texas Instruments Audio Solution Guide, 1Q 2004, p17-19, PCM1725 + TPA2000D4 Asynchronous Delta Sigma Modulation, CJ Kikkert et al., Proceedings of the Institution of Radio and Electronics Engineers, April 1975, pp.83-88 A Noise-Shaping Coder Topology for 15+ Bit Converters, LR Carley, IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, April 1989, pp.267-273

  In the conventional switching amplifier 400 corresponding to digital input as shown in FIG. 12, the n-bit digital signal is converted into an analog signal by the DAC 402 and transmitted to the analog input corresponding switching amplifier 404 through the LPF 403. Generally, the LPF 403 is composed of active elements. Further, since the LPF 403 needs to maintain a required dynamic range, low noise and high speed operation are required. Therefore, generally, the power consumption of the LPF 403 is large. Also, the circuit area is large.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to realize a digital input compatible switching amplifier with reduced power consumption and circuit area.

  In order to solve the above problems, a switching amplifier according to the present invention includes a digital ΔΣ modulator that converts a multi-bit m-bit digital signal into an n-bit digital signal (m> n> 1), and the n-bit digital signal analog A switching amplifier comprising a digital-to-analog converter for converting into a signal and an analog input-compatible switching amplifier for amplifying the analog signal generated by the digital-to-analog converter. The transfer function has a characteristic of a low-pass filter.

  According to the above invention, since the signal transfer function between the input and output of the analog input compatible switching amplifier has the characteristics of a low-pass filter, the analog input compatible switching amplifier includes the digital ΔΣ modulation included in the output of the digital-analog converter. Filtering processing of quantization noise generated by the device. Therefore, it is not necessary to input the analog signal output from the digital / analog converter to the analog input compatible switching amplifier through the low pass filter. If a low-pass filter is not provided in front of the analog input-compatible switching amplifier, power consumption and occupied area by the low-pass filter can be reduced.

  As described above, there is an effect that it is possible to realize a digital input compatible switching amplifier in which power consumption and circuit area are suppressed.

  In order to solve the above-described problems, the switching amplifier of the present invention includes an analog loop filter and a 1-bit quantizer that converts a signal that has passed through the analog loop filter into a 1-bit signal. And a power switch that receives the 1-bit signal, and the output of the power switch is fed back to the analog loop filter.

  According to the above invention, the analog input compatible switching amplifier performs the switching amplification using ΔΣ modulation, and therefore, noise in the voice band is compared with the analog input compatible switching amplifier using PWM (pulse width modulation). There is an effect that can be reduced.

  Further, when the power switch enters the loop that performs ΔΣ modulation, there is an effect that noise and distortion mixed in the signal in the power switch can be reduced.

  In order to solve the above problems, the switching amplifier of the present invention is characterized in that the analog loop filter is configured using a discrete-time integrator.

  According to the above invention, the analog input compatible switching amplifier performs ΔΣ modulation using a discrete-time integrator for the analog loop filter. A switched capacitor circuit is used to realize a discrete-time integrator, but even if there is a manufacturing variation in the capacitor of the integrator using the switched capacitor circuit, the influence on the integration characteristics is small. Matching accuracy to circuit characteristics is high. Therefore, there is an effect that stable filter performance can be obtained.

  In order to solve the above problems, the switching amplifier of the present invention is characterized in that the analog loop filter is configured using a time-continuous integrator.

  According to the above invention, since the time-continuous integrator is used for the analog loop filter, an anti-aliasing filter can be realized in the analog loop filter, the attenuation of quantization noise, and the discrete-time integrator There is an effect that it is possible to reduce the aliasing distortion caused by sampling in the case of using.

  In order to solve the above problems, the switching amplifier of the present invention is characterized in that the analog loop filter includes both a time-continuous integrator and a discrete-time integrator.

  According to the above invention, when a plurality of integrators are used for the analog loop filter, the zero point of the noise shaping characteristic is determined by the integrator on the subsequent stage side. It becomes an integrator commensurate with the importance of increasing the matching accuracy to the circuit characteristics of the constituent elements. In addition, since the first-stage integrator is a time-continuous type, it is possible to reduce current consumption and to avoid aliasing distortion due to sampling of the feedback signal.

  In order to solve the above problems, the switching amplifier of the present invention includes an analog loop filter and an asynchronous 1-bit quantum that converts an analog loop filter and a signal that has passed through the analog loop filter into a 1-bit signal. And a power switch having the asynchronous 1-bit signal as an input, and the output of the power switch is fed back to the analog loop filter.

  According to the above invention, the analog input-compatible switching amplifier performs asynchronous ΔΣ modulation, and a clock signal becomes unnecessary. Therefore, there is an effect that noise and jitter effects due to the clock signal are eliminated. In addition, the dynamic range is increased compared to the synchronous ΔΣ modulation of the same order.

  In the switching amplifier of the present invention, in order to solve the above problems, the digital-to-analog converter includes correction means for correcting non-linearity of the relationship between input and output in the digital-to-analog converter. It is said.

  According to said invention, there exists an effect that generation | occurrence | production of the noise by a digital / analog converter can be suppressed.

  As described above, since the signal transfer function between the input and output of the analog input compatible switching amplifier has the characteristics of a low-pass filter, the switching amplifier of the present invention realizes a digital input compatible switching amplifier with reduced power consumption and circuit area. There is an effect that can be done.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a switching amplifier 10 which is a digital input compatible switching amplifier according to the present embodiment. The switching amplifier 10 converts a digital ΔΣ modulator 11 that converts a multi-bit m-bit digital input signal into an n-bit digital signal (m> n> 1), and converts an output signal of the digital ΔΣ modulator 11 into an analog signal. A DAC 12 and an analog input corresponding switching amplifier 13 for amplifying an output analog signal generated by the DAC 12 are provided.

  FIG. 2 shows an example of a more detailed configuration of each block of the switching amplifier 10. As shown in the figure, the digital ΔΣ modulator 11 includes an adder 111, a digital loop filter 112, and an n-bit quantizer 113. The adder 111 calculates the difference between the m-bit digital input and the output of the n-bit quantizer 113. The DAC 12 includes a digital part 121 and an analog part 122. The digital part 121 and the analog part 122 will be described in detail later. The analog input compatible switching amplifier 13 includes an adder 131, an analog loop filter 132, a 1-bit quantizer 133, and a power switch 134. The difference between the output of the DAC 12 and the output of the power switch 134 fed back is calculated by the adder 131, and the analog input corresponding switching amplifier 13 is configured as an analog ΔΣ modulator. With this configuration, the switching noise mixed by the power switch 134 can be shaped out of the voice band.

  In the conventional digital input compatible switching amplifier 400 shown in FIG. 12, the output of the DAC 402 is transmitted to the analog input compatible switching amplifier 404 through the LPF 403. According to the present embodiment, the output of the DAC 12 is directly transmitted to the analog input compatible switching amplifier 13, and the analog input compatible switching amplifier 13 has a low-pass filter characteristic in terms of the signal transfer function between input and output. It is comprised so that it may become. The analog loop filter 132 of the analog input compatible switching amplifier 13 performs a filtering process of quantization noise included in the output of the DAC 12 generated by the digital ΔΣ modulator 11.

  The digital ΔΣ modulator 11 shown in FIG. 2 is a simplified block diagram. The digital ΔΣ modulator 11 is composed of a Feed-Forward type (hereinafter referred to as FF type), a Distributed Feedback type (hereinafter referred to as DFB type), a MASH type, an Error Feedback type, or other architectures. Has the same effect as this embodiment.

  FIG. 3 shows an example of the switching amplifier 13 for analog input. The analog input compatible switching amplifier 13 shown in the figure is configured like an analog ΔΣ modulator using a fifth-order DFB type loop filter. The analog input signal enters the adder 131 through the input gain block Ai, enters the adder 1321 through the discrete-time integrator I1 and the gain block B1, enters the adder 1322 through the discrete-time integrator I2 and the gain block B2, The adder 1323 is entered through the time type integrator I3 and the gain block B3, the adder 1324 is entered through the discrete time type integrator I4 and the gain block B4, and the 1-bit quantizer 133 is passed through the discrete time type integrator I5 and the gain block B5. And converted into a 1-bit signal. The power switch 134 is controlled by the generated 1-bit signal.

  The output of the power switch 134 is fed back to the adders 131 and 1321 to 1324 in order through the gain blocks A1 to A5. The output of the gain block B3 is fed back to the adder 1321 through the gain block C1. The output of the gain block B5 is fed back to the adder 1323 through the gain block C2.

  Signal transfer characteristics (hereinafter referred to as STF: Signal Transfer Function) between the input and output of the analog input compatible switching amplifier 13 made with the configuration shown in FIG. 3, that is, the input and output of the configuration in which ΔΣ modulation is performed using a discrete-time integrator. Is written in the following formula.

  Here, α is the DC gain of the STF, polei (i = 1 to 5) is the pole of the STF, and the values of the gains A1 to A5, B1 to B5 and C1 and C2 in the block diagram shown in FIG. Determined.

  By setting the gain of the analog input corresponding switching amplifier 13 shown in FIG. 1 to an appropriate value, it is possible to obtain an STF showing a required low-pass filter characteristic. FIG. 4 shows STF characteristics of an example of the ΔΣ modulator shown in FIG. In this graph, the horizontal axis represents the frequency normalized by the sampling frequency fs of the analog input-compatible switching amplifier 13, and the vertical axis represents the signal attenuation caused by the STF and is displayed in dB. Due to the low-pass filter characteristics of FIG. 4, the analog input compatible switching amplifier 13 functions as a low-pass filter for the analog input signal, so that the quantization noise component of the digital ΔΣ modulator 11 appearing at the output terminal of the switching amplifier 10 is attenuated. Can do.

  Note that the STF is not limited to the above formula, but includes all those showing low-pass filter characteristics, which are determined according to the system.

  Thus, according to the present embodiment, the signal transfer function between the input and output of the analog input corresponding switching amplifier 13 has the characteristics of a low-pass filter, so the analog input compatible switching amplifier 13 is included in the output of the DAC 12. Filtering processing of quantization noise generated by the ΔΣ modulator 11 is performed. Therefore, it is not necessary to input the analog signal output from the DAC 12 to the analog input corresponding switching amplifier 13 through the low pass filter. If a low-pass filter is not provided in front of the analog input-compatible switching amplifier 13, the power consumption and occupied area by the low-pass filter can be reduced.

  As described above, it is possible to realize a digital input compatible switching amplifier with reduced power consumption and circuit area.

  The switching amplifier 13 corresponding to the analog input includes an analog loop filter 132, a 1-bit quantizer 133, and a power switch 134, and the output of the power switch 134 is fed back to the analog loop filter 132. As described above, switching amplification is performed using ΔΣ modulation. Therefore, noise in the voice band can be reduced as compared with an analog input compatible switching amplifier using PWM (pulse width modulation). Further, when the power switch 134 enters a loop in which ΔΣ modulation is performed, noise and distortion mixed in the signal in the power switch 134 can be reduced.

  Further, since the analog loop filter 132 is configured using a discrete-time integrator, the analog input-compatible switching amplifier 13 performs ΔΣ modulation using the discrete-time integrator. A switched-capacitor circuit is used to realize a discrete-time integrator. Even if there is manufacturing variation in the capacitor of the integrator using the switched-capacitor circuit, the characteristics of the integrator depend on the capacitance ratio of the capacitor and the sampling time. Therefore, the influence on the integral characteristic is small, and the matching accuracy of the capacitance value of the capacitor to the circuit characteristic is high. Therefore, stable filter performance can be obtained.

  The graph shown in FIG. 5A is an example of the system simulation result of this embodiment, and shows the spectrum of the output signal of the power switch 134. The digital ΔΣ modulator 11 is configured by a 3-bit third-order FF type, and the analog input compatible switching amplifier 13 is configured by a fifth-order discrete-time DFB type shown in FIG. The sampling frequency (operating frequency) of the digital signal and analog signal was set to 2.8 MHz. . The horizontal axis of the graph shown in FIG. 5A represents the frequency normalized by the sampling frequency fs of the analog input corresponding switching amplifier 13, and the vertical axis represents the output displayed in dBFS units. The input is a 1 kHz sine wave with an amplitude of 0.76 and an OSR (oversampling ratio) of 64. The maximum value (hereinafter referred to as SNDR) of the signal component / (noise + distortion) in this embodiment is 71.4 dB.

  For comparison, FIG. 5B shows the output spectrum of the conventional switching amplifier 400 for digital input (FIG. 12). The configurations of the digital ΔΣ modulator 401 and the analog input compatible switching amplifier 404 are the same as those of the digital ΔΣ modulator 11 and the analog input compatible switching amplifier 13 of the present embodiment shown in FIG. However, as shown in FIG. 12, an LPF 403 is added before the input of the analog input corresponding switching amplifier 404. This filter uses a discrete-time third-order Chebischev type 1 transfer function. The minimum gain in the band was set to -1 dB, and the cutoff frequency was set to 30 kHz. The conventional SNDR is 72.06 dBFS.

  In addition, the maximum allowable input amplitude in the conventional example and the embodiment is determined by the analog input compatible switching amplifier. In this simulation, the maximum allowable input amplitude value according to the present embodiment and the related art is 0.76. When the input amplitude becomes larger than this value, the analog input compatible switching amplifier oscillates.

  Comparing FIG. 5A and FIG. 5B, according to the present embodiment, the SNDR is substantially the same as a conventional digital input compatible switching amplifier. There is no difference in SNDR and maximum input with and without LPF 403 (FIG. 12) and without (FIG. 1). Therefore, the LPF 403 can be removed, and the power consumption and the chip area (circuit area) can be reduced.

  The switching amplifier 13 corresponding to analog input shown in FIG. 1 can also be constituted by an analog loop filter 132 using a time continuous integrator. In this case, a loop filter having a low-pass filter characteristic can be designed. Therefore, the time-continuous analog loop filter 132 can perform the filtering process of the quantization noise included in the output of the DAC 12 generated by the digital ΔΣ modulator 11. When using a time-continuous integrator, the output signal of the analog loop filter 132 is sampled and then transmitted to the quantizer in the configuration of the present embodiment so far. Therefore, filtering processing is performed by the analog loop filter 132 before sampling, and an antialias filter can be realized in the analog loop filter 132. As a result, not only the attenuation of the quantization noise but also the aliasing distortion caused by the sampling when using the discrete-time integrator can be reduced.

  Also, the analog loop filter 132 can be configured using both a time continuous integrator and a discrete time integrator. FIG. 6 shows the configuration. In the analog input compatible switching amplifier 13 shown in FIG. 6, the analog loop filter 132 is configured by a third-order integrator, a time-continuous integrator is added to the first-stage integrator I1, and a second-stage integrator I2 and A discrete-time integrator is used as the third-stage integrator I3.

  The analog input signal enters adder 131 through input gain block Ai, enters adder 1328 through discrete time integrator I1 and gain block B1, enters adder 1329 through discrete time integrator I2 and gain block B2, The signal enters the 1-bit quantizer 133 through the time integrator I3 and the gain block B3 and is converted into a 1-bit signal. The power switch 134 is controlled by the generated 1-bit signal.

  The output of the power switch 134 is fed back to the adders 131, 1328, and 1329 in order through the gain blocks A1 to A3. The output of the gain block B3 is fed back to the adder 1328 through the gain block C1.

  When a plurality of integrators are used for the analog loop filter, the zero point of the noise shaping characteristic is determined by the integrator on the rear stage side. Therefore, by integrating the integrator into a discrete time type like the integrators I2 and I3, the integration is performed. It becomes an integrator commensurate with the importance of increasing the matching accuracy to the circuit characteristics of the elements constituting the device. Further, by making the first-stage integrator a time continuous type like the integrator I1, current consumption can be reduced and aliasing distortion caused by sampling of the feedback signal can be avoided.

  FIG. 7 is a block diagram showing another configuration example of the analog input corresponding switching amplifier 13. The analog input compatible switching amplifier 13 shown in the figure has a configuration based on an asynchronous ΔΣ modulator that does not sample an input signal. The asynchronous ΔΣ modulator is a ΔΣ modulator that does not use a clock signal. An input signal to the analog input corresponding switching amplifier 13 is transmitted to an asynchronous comparator 135 as a 1-bit quantizer 133 through a time continuous filter.

  As shown in FIG. 7, the analog input signal enters the adder 131 through the input gain block Ai. The output of the adder 131 enters a time continuous integrator I1. The output of the integrator I1 enters the time continuous integrator I2 through the gain block B0. The output of the integrator I2 is fed back to the adder 131 through the gain block C1. The outputs of the integrators I1 and I2 enter the adder 1325 through the gain blocks B2 and B1 in order. The difference between the sum calculated by the adder 1325 and the output of the power switch 134 through the gain block A2 is calculated by the adder 1326. The calculated difference is transmitted to the asynchronous comparator 135 through the LPF 1327 of the loop. The LPF 1327 is a third-order low-pass filter in which three first-order low-pass filters including resistors and capacitors are connected in series. The power switch 134 is controlled by a 1-bit signal generated by the asynchronous comparator 135. The output of the power switch 134 is fed back to the adder 131 through the gain block A1.

  According to the analog input-compatible switching amplifier 13, a clock signal is not necessary, and noise and jitter effects due to the clock signal are eliminated. In addition, the dynamic range is increased as compared with synchronous ΔΣ modulation of the same order.

  Further, by using the asynchronous analog input-compatible switching amplifier 13 as shown in FIG. 7, low-pass filtering processing and anti-aliasing filtering of signals in an FF (feed forward) path composed of a low-pass filter 1327 and integrators I1 and I2 are performed. Processing can be performed.

  Next, FIG. 8 is a block diagram showing a configuration example of the DAC 12 shown in FIG. In this configuration, a well-known Dynamic Element Matching (hereinafter referred to as DEM) method is used. The DEM is a system that can correct the distortion mixed by the analog portion 122 of the DAC 12 by the digital portion 121 of the DAC 12. Since the DAC 12 includes correction means for correcting the nonlinearity of the relationship between input and output in the DAC 12, it is possible to suppress the occurrence of noise by the DAC 12.

  The digital part 121 includes a digital encoder and a scrambler. The n-bit digital input is converted by the digital part 121 into a 2n × 1 bit signal. The generated 1-bit signal is converted into an analog signal by the 1-bit DAC of the analog portion 122, and an analog output is generated by adding the outputs of all the 1-bit DACs. In order to remove the distortion, the 1-bit DAC to be used is randomly selected. Since the 1-bit DAC is connected at random, the power of the DAC error (distortion, etc.) spreads over a wide band, and the power within the audio band becomes small. There are many algorithms for selecting at random (for example, see Non-Patent Document 4).

  Next, the circuit diagram shown in FIG. 9 is an example of a specific configuration example of the gain blocks Ai, A1, B0, and C1, the integrator I1, and the adder 131 of the analog input corresponding switching amplifier 13 shown in FIG. One. According to the circuit diagram shown in FIG. 9, the integrator I1 is composed of a time-continuous differential integrator. The output signal of the power switch 134 is fed back to the resistor R. The gains of the gain block Ai and the gain block A1 shown in FIG. 7 can be set by the input resistor R and the feedback capacitor C of the amplifier (AMP). The output signal of the integrator I2 shown in FIG. 7 is fed back to the resistor Rc connected to the input terminal of the amplifier (AMP), and the gain of the gain block C1 can be set by the resistor Rc and the feedback capacitor C of the amplifier (AMP). . The differential output of the amplifier (AMP) is input to the integrator I2.

Further, by inputting the signal generated by the analog portion 122 of the DAC 12 to the amplifier, an adder 131 that calculates the difference between the signal generated by the DAC 12 and the output signal of the power switch 134 can be realized. Further, as shown in FIG. 9, the analog portion 122 of the DAC 12 can be realized by a current source. The 1-bit DAC shown in FIG. 8 includes a pair of current sources (for example, 1221 and 1224) and a pair of switches (for example, 1222 and 1223) as shown in FIG. The switch is controlled by a 1-bit signal (eg, a ₀ , a ₁ ) generated by the digital part 121 of the DAC 12. For example, the ON / OFF of the switches 1222 and 1223 is controlled by the 1-bit signal a _0, and the current flow generated by the current sources 1221 and 1224 is controlled. The current source 1221 is connected to the power supply terminal 1220 and is configured such that current flows from the power supply terminal 1220 side to the amplifier side. The current source 1224 is connected to the ground terminal 1225 and is configured such that current flows from the amplifier side to the ground terminal 1225 side.

  Further, the 1-bit DAC shown in FIG. 9 can be configured by a resistor or a capacitor.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be suitably used for a digital audio amplifier.

1, showing an embodiment of the present invention, is a block diagram showing a configuration of a switching amplifier. FIG. FIG. 2 is a block diagram showing a more detailed configuration of the switching amplifier of FIG. 1. FIG. 3 is a block diagram illustrating a configuration example of an analog input compatible switching amplifier illustrated in FIG. 2. It is a graph which shows the filtering characteristic by the switching amplifier corresponding to an analog input shown in FIG. (A) is a graph which shows the simulation result of the switching amplifier by this embodiment, (b) is a graph which shows the simulation result of the conventional switching amplifier. FIG. 3 is a block diagram showing another configuration example of the analog input-compatible switching amplifier shown in FIG. 2. FIG. 5 is a block diagram showing still another configuration example of the analog input-compatible switching amplifier shown in FIG. 2. FIG. 3 is a block diagram illustrating a configuration example of a DAC illustrated in FIG. 2. FIG. 3 is a block diagram showing a configuration example of an input stage of the analog input-compatible switching amplifier shown in FIG. 2. It is a block diagram which shows a prior art and shows the structure of the switching amplifier using a 1 bit digital delta-sigma modulator. It is a block diagram which shows a prior art and shows the structure of the switching amplifier using 1 bit digital delta-sigma modulator and LPF. It is a block diagram which shows a prior art and shows the structure of the switching amplifier using a multibit digital delta-sigma modulator and LPF.

Explanation of symbols

10 Switching Amplifier 11 Digital Delta Sigma Modulator 12 DAC (Digital to Analog Converter)
13 Analog input compatible switching amplifier 132 Analog loop filter 133 1-bit quantizer 134 Power switch 135 Asynchronous comparator (asynchronous 1-bit quantizer)

Claims (7)

A digital delta-sigma modulator that converts a multi-bit m-bit digital signal into an n-bit digital signal (m>n>1); a digital-analog converter that converts the n-bit digital signal into an analog signal; In a switching amplifier comprising an analog input compatible switching amplifier for amplifying an analog signal generated by an analog converter,
A switching amplifier characterized in that a signal transfer function between input and output of the analog input compatible switching amplifier has a low-pass filter characteristic. The analog input-compatible switching amplifier includes an analog loop filter, a 1-bit quantizer that converts a signal that has passed through the analog loop filter into a 1-bit signal, and a power switch that receives the 1-bit signal. And
2. The switching amplifier according to claim 1, wherein an output of the power switch is fed back to the analog loop filter.   3. The switching amplifier according to claim 2, wherein the analog loop filter is configured using a discrete time type integrator.   3. The switching amplifier according to claim 2, wherein the analog loop filter is configured using a time-continuous integrator.   3. The switching amplifier according to claim 2, wherein the analog loop filter is configured by using both a time-continuous integrator and a discrete-time integrator. The analog input-compatible switching amplifier includes an analog loop filter, an asynchronous 1-bit quantizer that converts a signal passing through the analog loop filter into a 1-bit signal, and a power switch that receives the asynchronous 1-bit signal. And
2. The switching amplifier according to claim 1, wherein the output of the power switch is fed back to the analog loop filter.   2. The switching amplifier according to claim 1, wherein the digital-to-analog converter includes correction means for correcting non-linearity in the relationship between input and output in the digital-to-analog converter.

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