JP4167381B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a high-speed and low power consumption MOS semiconductor device that enables high integration.
[0002]
[Prior art]
With the ultra-high integration of semiconductor integrated circuits, there is a strong demand for miniaturization of MOS type semiconductor devices, particularly MOS type transistors. In order to miniaturize a MOS transistor, a method for manufacturing a transistor having a so-called shallow junction in which the junction depth of a diffusion layer formed on a semiconductor substrate is reduced is essential.
[0003]
Hereinafter, a conventional method for manufacturing a MOS transistor will be described with reference to the drawings.
[0004]
FIG. 8A to FIG. 8E show cross-sectional structures in the order of steps of a conventional MOS transistor manufacturing method.
[0005]
First, as shown in FIG. 8A, a gate electrode 103 made of polysilicon is selectively formed on a semiconductor substrate 101 made of P-type silicon with a gate oxide film 102 interposed therebetween.
[0006]
Next, as shown in FIG. 8B, a shallow N-type extension diffusion layer 101a is formed by implanting N-type first impurity ions into the upper portion of the semiconductor substrate 101 using the gate electrode 103 as a mask. Form.
[0007]
Next, as shown in FIG. 8C, a silicon nitride film or a silicon oxide film is deposited on the entire surface of the semiconductor substrate 101 at a relatively low temperature of about 700 ° C., and then the deposited silicon nitride film Then, an anisotropic etch back is performed to form a sidewall 104 on the side surface of the gate electrode 103.
[0008]
Next, as shown in FIG. 8D, the N-type second impurity ions are deeper than the extension diffusion layer 101a with respect to the upper portion of the semiconductor substrate 101 using the gate electrode 103 and the sidewall 104 as a mask. By implantation, a high concentration source / drain diffusion layer 101b is formed. Thereafter, a so-called rapid thermal treatment (RTA), which is a thermal treatment with a temperature of about 900 ° C. to 1000 ° C. and a heating time of about 10 seconds, is performed to activate the impurity ions in the extension diffusion layer 101a and the source / drain diffusion layer 101b, respectively. .
[0009]
Next, as shown in FIG. 8E, a metal film made of cobalt or titanium having a thickness of about 10 nm and a titanium nitride film having a thickness of about 20 nm are sequentially deposited on the entire surface of the semiconductor substrate 101 by sputtering. Subsequently, a heat treatment is performed at a temperature of about 550 ° C. for a heating time of about 10 seconds, and the titanium nitride film and the unreacted metal film are selectively etched with a mixture of sulfuric acid, hydrogen peroxide, and water. And remove. Next, a heat treatment is performed at a temperature of about 800 ° C. and a heating time of about 10 seconds, so that a metal silicide 105 having a thickness of about 30 nm is self-aligned on the bonding surface of the metal film to the semiconductor substrate 101 and the gate electrode 103. To form.
[0010]
In the conventional MOS transistor, the junction depths of the extension diffusion layer 101a and the source / drain diffusion layer 101b are made shallow by reducing the implantation energy of the first impurity ions and the second impurity ions in this way. It is said. At this time, in order to reduce the parasitic resistance value of the source / drain diffusion layer 101b, the implantation doses of the N-type first and second impurity ions tend to increase.
[0011]
[Problems to be solved by the invention]
However, in the conventional method for manufacturing a MOS transistor, when ion implantation is performed at a high dose and energy is reduced, transient accelerated diffusion of impurity ions occurs due to low-temperature heat treatment during sidewall formation, and the junction depth as designed is reduced. There is a problem that cannot be obtained. Here, excessively enhanced diffusion means that point defects that exist excessively between lattices in the crystal lattice and the implanted impurity ions diffuse due to interaction, and the impurity ions diffuse beyond the diffusion coefficient of their thermal equilibrium state. The phenomenon that occurs.
[0012]
Due to this excessively enhanced diffusion, the impurity concentration distribution in each cross section of the substrate main surface direction and the depth direction of each diffusion layer 101a, 101b is not a constant slope of the impurity concentration with respect to the depth from the substrate surface, As the impurity concentration becomes lower, the resistance value of each of the diffusion layers 101a and 101b becomes higher due to the flared shape.
[0013]
In addition, since an inactive region of impurity ions that does not contribute to the actual operation of the transistor is formed, there is a problem that the ratio (activation rate) between the implantation concentration of impurity ions and the activation concentration after diffusion becomes small. is doing. If the activation rate is not sufficiently high, the parasitic resistance of the source / drain diffusion layer 101b is increased. Further, as described above, if the activation rate of impurity ions is small, it is necessary to increase the implantation dose in order to compensate for this.
[0014]
By the way, as one method of avoiding the low temperature heat treatment at the time of forming the sidewall 104, the sidewall 104 is removed after the N-type second impurity is implanted, and the first impurity for the N-type extension is implanted. There is a way to do it. However, in this method, it is necessary to form a sidewall again when forming the metal silicide 105, and a low-temperature heat treatment at the time of forming the sidewall is added, resulting in excessively accelerated diffusion.
[0015]
Thus, unless the transient enhanced diffusion of impurity ions is suppressed, a shallower junction depth cannot be obtained. For example, in a 0.1 μm CMOS process, a junction depth of the extension diffusion layer 101a is required to be 20 nm to 30 nm. However, it is predicted that impurity ions move by several tens of nanometers due to transient enhanced diffusion caused by low-temperature heat treatment during sidewall formation. This means that if the semiconductor device is further miniaturized, the interface of the junction becomes deeper than the target value due to the heat treatment in the subsequent process, no matter how much the energy of the impurity ions is reduced.
[0016]
An object of the present invention is to solve the above-mentioned conventional problems and to realize a semiconductor device having a shallow junction depth by suppressing excessively enhanced diffusion.
[0017]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, there is provided a method of manufacturing a semiconductor device comprising: an extension region located under a side surface of a gate electrode in a semiconductor substrate; The impurity region having the same conductivity type as that of the channel region is implanted into the region through the implantation protective film so that the extension region is positively made amorphous.
[0018]
Specifically, in the first method for manufacturing a semiconductor device according to the present invention, a first conductivity type diffusion serving as a channel region is formed by implanting a first conductivity type first impurity into an upper portion of a semiconductor substrate. A step of forming a layer, a step of forming a gate electrode on the semiconductor substrate via a gate insulating film, a step of forming an implantation protective film made of an insulating film over the entire surface of the semiconductor substrate, and a side surface of the gate electrode Forming a sidewall through an implantation protective film, and implanting a second impurity of the second conductivity type into the semiconductor substrate through the implantation protective film by using the gate electrode and the sidewall as a mask. Forming a first high-concentration diffusion layer of the mold, and after removing the sidewall, the extension located below the side surface of the gate electrode in the semiconductor substrate using the gate electrode as a mask A third impurity of the first conductivity type is implanted into the impurity region through the implantation protective film, and the step of amorphizing the extension region and the second conductivity type fourth impurity with respect to the semiconductor substrate using the gate electrode as a mask Forming a second high-concentration diffusion layer of the second conductivity type having a junction depth shallower than that of the first high-concentration diffusion layer in the extension region by injecting impurities through the implantation protective film and performing heat treatment. I have.
[0019]
According to the first method for manufacturing a semiconductor device, a first high-concentration diffusion layer serving as a source / drain region is formed by injecting impurities into the semiconductor substrate through the implantation protective film using the gate electrode and the sidewall as a mask. After removing the sidewall, the extension region is amorphized by implanting impurities of the same conductivity type as the channel region into the extension region located below the side surface of the gate electrode in the semiconductor substrate through the implantation protective film. . Thereafter, an impurity having the same conductivity type as that of the source / drain region is implanted into the semiconductor substrate through the implantation protective film using the gate electrode as a mask, and heat treatment is performed, so that the junction region shallower than the first high-concentration diffusion layer is formed in the extension region. Forming a second high-concentration diffusion layer having Thereby, since the extension region is preamorphized, excess point defects that cause excessively accelerated diffusion are reduced. In addition, since the second high-concentration diffusion layer is formed after the sidewall is formed and removed, the second high-concentration diffusion layer is not exposed to the low-temperature heat treatment during the formation of the sidewall. The high concentration diffusion layer can be formed into a shallow junction. Furthermore, since the impurity implantation of the first high-concentration diffusion layer serving as the source / drain region is performed through the implantation protective film, the first high-concentration diffusion layer can be formed into a shallow junction.
[0020]
In the first method for fabricating a semiconductor device, it is preferable that the step of forming the first high-concentration diffusion layer includes a step of performing a heat treatment on the semiconductor substrate into which the second impurity has been implanted. In this way, excess point defects that cause accelerated diffusion can be reduced, so that the junction depth of the first high-concentration diffusion layer can be reduced. In addition, since it is possible to prevent excess point defects from entering the extension region when forming the extension diffusion layer in a later step, the junction depth of the shallow second high-concentration diffusion layer that is the extension region is surely reduced. Can do.
[0021]
In the present specification, pre-amorphization means that the extension region is amorphized before the second high-concentration diffusion layer that is the extension region is formed.
[0022]
The first semiconductor device manufacturing method includes a step of forming a sidewall made of an insulating film on a side surface of the gate electrode after the step of forming the second high-concentration diffusion layer at least on the upper portion of the semiconductor substrate. And removing the exposed portion of the implantation protective film on the semiconductor substrate, and then depositing a metal film over the entire surface including the gate electrode on the semiconductor substrate, and joining the deposited metal film to the gate electrode and the semiconductor substrate. It is preferable to further comprise a step of forming a silicide film in a self-aligned manner on the gate electrode and the second high-concentration diffusion layer by reacting each other. In this way, depending on the extension region and the implantation conditions, even the pocket region below the extension region is amorphized, so even if a new sidewall for forming a silicide film is formed, each high-concentration diffusion layer Excessive diffusion can be suppressed.
[0023]
In the first method for fabricating a semiconductor device, the third impurity is preferably made of ions having a relatively large mass number. In this way, the extension region can be preamorphized reliably.
[0024]
According to the second method for manufacturing a semiconductor device of the present invention, the first conductivity type serving as the channel region is formed by implanting the first impurity of the first conductivity type into the upper portion of the semiconductor substrate at least the upper portion made of silicon. Forming a diffusion layer, forming a gate electrode on the semiconductor substrate via a gate insulating film, and forming an implantation protective film made of an insulating film over the entire surface including the gate electrode on the semiconductor substrate And forming a sidewall made of an insulating film on the side surface of the gate electrode through an implantation protective film, and implanting and protecting the second impurity of the second conductivity type to the semiconductor substrate using the gate electrode and the sidewall as a mask. By implanting through the film, the step of forming the first high-concentration diffusion layer of the second conductivity type and the portion of the implantation protective film exposed on the semiconductor substrate were removed Then, a metal film is deposited over the entire surface including the gate electrode on the semiconductor substrate, and the bonded surfaces of the deposited metal film, the gate electrode, and the semiconductor substrate are caused to react with each other, thereby forming the gate electrode and the first high-concentration diffusion layer. A step of forming a silicide film on the upper surface in a self-aligned manner, and after removing the sidewalls, an extension region located below the side surface of the gate electrode in the semiconductor substrate using the gate electrode and the silicide film as a mask; Implanting the third impurity through the implantation protective film to selectively amorphize the extension region, and implanting the second impurity of the second conductivity type into the semiconductor substrate using the gate electrode as a mask. By implanting through and performing heat treatment, the extension region has a shallower junction depth than the first high-concentration diffusion layer. And a step of forming a second high concentration diffusion layer of the second conductivity type having.
[0025]
According to the second method for manufacturing a semiconductor device, a first high-concentration diffusion layer serving as a source / drain region is formed by injecting impurities into the semiconductor substrate through the implantation protective film using the gate electrode and the sidewall as a mask. . Subsequently, after removing the exposed portion of the implantation protective film on the semiconductor substrate, a metal film is deposited on the entire surface including the gate electrode on the semiconductor substrate, and the deposited metal film is bonded to the gate electrode and the semiconductor substrate. By reacting the surfaces with each other, a silicide film is formed in a self-aligned manner on the gate electrode and the first high-concentration diffusion layer. Thereafter, the sidewall is removed, and the extension region located under the side surface of the gate electrode in the semiconductor substrate is selectively amorphized, and then an impurity is implanted into the semiconductor substrate using the gate electrode as a mask and a protective film The second high-concentration diffusion layer is formed in the extension region by injecting through and performing heat treatment. Thus, since the extension region is preamorphized, excess point defects that cause excessively accelerated diffusion are reduced. In addition, since the second high-concentration diffusion layer is formed after the sidewall is formed and removed, the second high-concentration diffusion layer is not exposed to the low-temperature heat treatment during the formation of the sidewall. The high concentration diffusion layer can be formed into a shallow junction. Further, since the gate electrode and the upper portion of the first high-concentration diffusion layer are silicided before the sidewall is removed, it is not necessary to newly provide a sidewall for silicidation. In addition, since the extension region is selectively pre-amorphized after siliciding the upper portion of the first high-concentration diffusion layer, the surface of the first high-concentration diffusion layer is protected by the silicide film and is not amorphized. The dislocation loop is not formed in the vicinity of the surface of the first high-concentration diffusion layer, and the occurrence of leakage current due to the dislocation loop can be prevented.
[0026]
In the second method for fabricating a semiconductor device, it is preferable that the step of forming the first high-concentration diffusion layer includes a step of performing a heat treatment on the semiconductor substrate into which the second impurity has been implanted.
[0027]
In the second method for manufacturing a semiconductor device, the metal film is preferably made of a laminate made of titanium and cobalt or an alloy of titanium and cobalt. In this way, the heat resistance of the metal silicide is improved, so that the silicide film can be reliably formed.
[0028]
In the second method for fabricating a semiconductor device, the third impurity is preferably made of ions having a relatively large mass number.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.
[0030]
FIG. 1A to FIG. 1D and FIG. 2A to FIG. 2D show cross-sectional structures in order of steps of the method for manufacturing a MOS transistor according to the first embodiment.
[0031]
First, as shown in FIG. 1A, an impurity ion such as indium (In) ion having a relatively large mass number is implanted into a semiconductor substrate 11 made of P-type silicon at an energy of about 200 KeV. The implantation dose is about 1 × 10 ¹² / Cm ² Injection is performed under the following injection conditions. Subsequent to the ion implantation, the temperature is raised to a high temperature of about 1025 ° C. at a rate of about 100 ° C./second, and a short-time heat treatment that maintains this temperature for a maximum of about 10 seconds, that is, rapid heat treatment (RTA) is performed. As a result, a P-type diffusion layer 11 a serving as a channel region is formed on the semiconductor substrate 11.
[0032]
Next, as shown in FIG. 1B, a gate insulating film 12 having a thickness of about 3 nm is formed on the semiconductor substrate 11, and a polycrystalline film having a thickness of about 250 nm is formed on the gate insulating film 12. A gate electrode 13 made of silicon is formed. Subsequently, an implantation protective film 14 made of a silicon oxide film having a thickness of about 5 nm is formed on the semiconductor substrate 11 over the entire surface including the gate electrode 13.
[0033]
Next, as shown in FIG. 1C, a silicon nitride film having a film pressure of about 50 nm is deposited on the entire surface of the implantation protection film 14 so as to cover the gate electrode 13, and the deposited silicon nitride film is applied to the deposited silicon nitride film. By performing anisotropic etching having strong anisotropy in the direction perpendicular to the substrate surface, the first sidewall 15 made of a silicon nitride film is formed on the side surface of the gate electrode 13 on the gate length direction side.
[0034]
Next, as shown in FIG. 1D, for example, arsenic (As) ions, which are N-type impurity ions, are implanted and protected into the semiconductor substrate 11 using the gate electrode 13 and the first sidewall 15 as a mask. Through the film 14, the implantation energy is about 30 KeV and the implantation dose is about 3 × 10. ¹⁵ / Cm ² Injection is performed under the following injection conditions. After the implantation, the temperature is raised to a high temperature of about 1025 ° C. at a rate of about 100 ° C./second, and a rapid heat treatment is performed to maintain this temperature for about 10 seconds. A first high concentration diffusion layer 16 is formed.
[0035]
Next, as shown in FIG. 2A, the first sidewall 15 is removed using a mixed solution of hydrofluoric acid and hot phosphoric acid, and then the gate electrode in the semiconductor substrate 11 using the gate electrode 13 as a mask. In the pocket region located on the lower side of the side surface 13, P-type impurity ions having a relatively large mass number, for example, In ions are passed through the implantation protective film 14, the implantation energy is about 200 keV, and the implantation dose amount is about 5 × 10 ¹³ / Cm ² By implanting under the above implantation conditions, a P-type pocket diffusion layer 17 is formed. By performing so-called pocket implantation using In ions which are heavy ions, the pocket diffusion layer 17 including the extension region on the upper portion is selectively preamorphized.
[0036]
Next, as shown in FIG. 2B, the gate electrode 13 is used as a mask and the semiconductor substrate 11 is filled with N-type impurity ions, for example, As ions, through the implantation protective film 14, and the implantation energy is about 10 keV. The implantation dose is about 5 × 10 ¹⁴ / Cm ² Injection is performed under the following injection conditions. After the As ions are implanted, the temperature is raised to a high temperature of about 1025 ° C. at a rate of about 100 ° C./second, and a rapid heat treatment is performed to maintain this temperature for about 10 seconds to activate the implanted As ions. Thus, the N-type second high concentration diffusion layer 18 having a shallower junction depth than the first high concentration diffusion layer 16 is formed in the extension region located above the pocket diffusion layer 17 in the semiconductor substrate 11. To do.
[0037]
Next, as shown in FIG. 2C, a silicon nitride film having a film pressure of about 50 nm is deposited over the entire surface of the implantation protective film 14 so as to cover the gate electrode 13 again. On the other hand, by performing anisotropic etching having strong anisotropy in the direction perpendicular to the substrate surface, the second sidewall 19 made of a silicon nitride film is formed on the side surface of the gate electrode 13 on the gate length direction side. . Subsequently, the upper surface portion of the gate electrode 13 and the upper surface portion of the second high concentration diffusion layer 18 in the implantation protective film 14 are removed by etching.
[0038]
Next, as shown in FIG. 2D, titanium (Ti) having a film thickness of, for example, about 30 nm is formed on the entire surface including the gate electrode 13 and the second sidewall 19 on the semiconductor substrate 11 by sputtering. ) And then a rapid heat treatment at a heating temperature of about 680 ° C. for about 10 seconds, whereby the deposited metal film and the gate electrode 13 and the second high-concentration diffusion layer 18 of the semiconductor substrate 11 are deposited. The joint surfaces with each other react with each other. Subsequently, the gate electrode 13 and the second high-concentration diffusion layer 18 and the unreacted metal film are removed by selective etching with a mixed solution of sulfuric acid, hydrogen peroxide, and water. Thereafter, a rapid heat treatment is performed at a heating temperature of about 900 ° C. for about 10 seconds, so that the metal silicide film 20 having a thickness of about 50 nm is formed on the gate electrode 13 and the second high-concentration diffusion layer 18 in a self-aligned manner. Form.
[0039]
3A and 3B are impurity concentration distributions of the second high-concentration diffusion layer 18 in the MOS transistor shown in FIG. 2D, and FIG. ₁ -A ₂ This represents the impurity concentration in the depth direction from the substrate surface along the line, and FIG. ₁ -B ₂ The impurity concentration in the substrate surface direction along the line is shown. Here, the vertical axis in each graph represents the impurity concentration C _A Logarithmic display.
[0040]
As can be seen from FIG. 3A, according to the first embodiment, after forming the N-type first high-concentration diffusion layer 16 in the step shown in FIG. When the P-type pocket diffusion layer 17 is formed by implanting In ions, which are heavy ions having a relatively large size, the pocket diffusion layer 17 including the extension region on the upper portion is positively amorphous due to the implantation damage caused by In ions. Turn into. Since the pocket diffusion layer 17 including the extension region in the upper portion is made amorphous before forming the second high concentration diffusion layer 17 as the extension diffusion layer, that is, preamorphized, the second high concentration diffusion is performed. It is possible to reduce excess point defects that cause excessively accelerated diffusion when forming the layer 17. Furthermore, pre-amorphization can suppress channeling that occurs during the implantation of As ions in the second high-concentration diffusion layer 17, and as a result, the junction surface of the second high-concentration diffusion layer 17 becomes shallow. The effect can be suppressed.
[0041]
In addition, since the implantation protective film 14 made of a silicon oxide film is provided on the entire surface of the semiconductor substrate 11 after the gate electrode 13 is formed, the junction between the first high concentration diffusion layer 16 and the second high concentration diffusion layer 18 is formed. Each depth can be reduced, and as can be seen from FIG. 3B, the As ions in the second high-concentration diffusion layer 18 can also be prevented from entering the region below the gate electrode 13.
[0042]
In the first embodiment, since In ions having a relatively large mass number are used as impurity ions forming the P-type diffusion layer 11a which is the channel region, impurities in a region near the surface of the semiconductor substrate 11 are used. Since the impurity concentration is small and a steep impurity concentration distribution can be formed in a region away from the region in the vicinity of the surface, miniaturization can be achieved without reducing the driving force of the transistor. In addition, since the rapid heat treatment is performed after the heavy ions are implanted into the channel region, crystal damage due to In ions in the semiconductor substrate 11 can be reliably and promptly recovered.
[0043]
Further, the solid solution limit of impurities is increased by rapid heat treatment in which the heating temperature exceeds 1000 ° C., which is performed after the ion implantation into the source / drain region shown in FIG. 1D and the ion implantation into the extension region shown in FIG. Clustering can be suppressed. In addition, since the injection damage is quickly recovered and the increase in diffusion is suppressed by the high temperature increase rate of 100 ° C./second, the first high concentration diffusion layer 16 and the second high concentration diffusion layer 18 are suppressed. The activity efficiency of each impurity ion is improved, and the impurity concentration gradient of each junction surface between the substrate surface direction and the depth direction in each high-concentration diffusion layer 16, 18 is 1 × 10. ⁶ (atom / cm ^Three ) / μm or more profile can be realized.
[0044]
As described above, the activation efficiency, which is an index from the impurity implantation concentration to the impurity concentration after diffusion, increases, so that the parasitic resistance of each of the high concentration diffusion layers 16 and 18 is reduced, and the driving capability of the transistor is improved. Since the second high-concentration diffusion layer 18 has a shallow junction depth, the short channel effect can be suppressed. In the step shown in FIG. 2D, even if the second sidewall 19 for forming the metal silicide film 20 is formed after the second high-concentration diffusion layer 18 is formed, the pocket diffusion layer 17 is not formed. Since it has been made amorphous, the excessively accelerated diffusion in the second high-concentration diffusion layer 18 is suppressed even when exposed to a low-temperature heat treatment when forming the second sidewall 19.
[0045]
In the first embodiment, rapid thermal processing is performed for each implantation of the first high-concentration diffusion layer 16 and the second high-concentration diffusion layer 18, but after the second high-concentration diffusion layer 18 is implanted. You may perform only.
[0046]
Further, the exposed portion of the implantation protective film 14 may be removed when forming the first sidewall 15 in FIG. However, in this case, as the As ion implantation conditions, for example, the implantation energy is about 30 keV, and the implantation dose is set so that the impurity profile of the first high-concentration diffusion layer 16 is not significantly changed from that before the removal. About 3.6 × 10 ¹⁵ / Cm ² It is preferable that
[0047]
Further, although polycrystalline silicon is used for the gate electrode 13, polymetal may be used.
[0048]
Moreover, although the silicon nitride film is used for the first sidewall 15 and the second sidewall 19, a TEOS film may be used. In the case where the sidewalls 15 and 19 are formed of a TEOS film, it is preferable that the implantation protective film 14 is formed of a silicon nitride film.
[0049]
Further, although titanium silicide is used for the metal silicide film 20, cobalt silicide may be used.
[0050]
Although the MOS transistor is an N-channel MOS transistor, it may be a P-channel MOS transistor instead. In the case of a P-channel MOS transistor, it is preferable to use antimony (Sb) ions as N-type heavy ions implanted into the channel region and the pocket region.
[0051]
(Second Embodiment)
A semiconductor device manufacturing method according to the second embodiment of the present invention will be described below with reference to the drawings.
[0052]
4 (a) to 4 (d) and FIGS. 5 (a) to 5 (d) show cross-sectional structures in the order of steps of the MOS transistor manufacturing method according to the second embodiment.
[0053]
First, as shown in FIG. 4A, for example, boron (B) ions, which are P-type impurity ions, are implanted into a semiconductor substrate 21 made of P-type silicon at an implantation energy of about 200 KeV and an implantation dose amount. About 1 × 10 ¹² / Cm ² Injection is performed under the following injection conditions. Subsequent to the ion implantation, the temperature is raised to a high temperature of about 1025 ° C. at a rate of about 100 ° C./second, and a rapid heat treatment is performed to maintain this temperature for a maximum of about 10 seconds. A P-type diffusion layer 21a to be a channel region is formed.
[0054]
Next, as shown in FIG. 4B, a gate insulating film 22 having a thickness of about 3 nm is formed on the semiconductor substrate 21, and a polycrystalline film having a thickness of about 250 nm is formed on the gate insulating film 22. A gate electrode 23 made of silicon is formed. Subsequently, an implantation protective film 24 made of a silicon oxide film having a thickness of about 5 nm is formed on the semiconductor substrate 21 over the entire surface including the gate electrode 23.
[0055]
Next, as shown in FIG. 4C, a silicon nitride film having a film pressure of about 50 nm is deposited on the entire surface of the implantation protective film 24 so as to cover the gate electrode 23, and the deposited silicon nitride film is applied to the deposited silicon nitride film. By performing anisotropic etching, a sidewall 25 made of a silicon nitride film is formed on the side surface of the gate electrode 23 on the gate length direction side.
[0056]
Next, as shown in FIG. 4D, the gate electrode 23 and the sidewall 25 are used as a mask, and for example, As ions, which are N-type impurity ions, are injected into the semiconductor substrate 21 through the implantation protective film 24 and the implantation energy is increased. About 30 KeV and implantation dose is about 3 × 10 ¹⁵ / Cm ² Injection is performed under the following injection conditions. After the implantation, the temperature is raised to a high temperature of about 1025 ° C. at a temperature rising rate of about 100 ° C./second, and a rapid heat treatment is performed to maintain this temperature for about 10 seconds. A first high concentration diffusion layer 26 is formed.
[0057]
Next, as shown in FIG. 5A, the upper surface portion of the gate electrode 23 and the upper surface portion of the first high-concentration diffusion layer 26 in the implantation protective film 24 are removed by etching, and subsequently, sputtering is used. A metal film 27A made of Ti having a film thickness of, for example, about 30 nm is deposited on the semiconductor substrate 21 over the entire surface including the gate electrode 23 and the sidewalls 25.
[0058]
Next, as shown in FIG. 5B, the first high concentration of the deposited metal film 27A, the gate electrode 23, and the semiconductor substrate 21 is performed by performing a rapid heat treatment at a heating temperature of about 680 ° C. for about 10 seconds. The joint surface with the diffusion layer 26 reacts with each other. Subsequently, the gate electrode 23, the first high-concentration diffusion layer 26, and the unreacted metal film are removed by selective etching with a mixed solution of sulfuric acid, hydrogen peroxide, and water. Thereafter, a rapid heat treatment is performed at a heating temperature of about 900 ° C. for about 10 seconds, whereby a metal silicide film 27A having a thickness of about 50 nm is formed on the gate electrode 23 and the first high-concentration diffusion layer 26 in a self-aligning manner. Form.
[0059]
Next, as shown in FIG. 5C, the sidewall 25 is removed using a mixed solution of hydrofluoric acid and hot phosphoric acid, and then the side surface of the gate electrode 23 in the semiconductor substrate 21 using the gate electrode 23 as a mask. In the pocket region located on the lower side, P type impurity ions having a relatively large mass number, for example, In ions are passed through the implantation protective film 24, the implantation energy is about 200 keV, and the implantation dose is about 5 × 10. ¹³ / Cm ² By implanting under the following implantation conditions, the P-type pocket diffusion layer 28 is formed. By performing pocket implantation with heavy ions, the pocket diffusion layer 28 including the extension region in the upper portion is selectively preamorphized.
[0060]
Next, as shown in FIG. 5D, N-type impurity ions, for example, As ions are implanted into the semiconductor substrate 21 through the implantation protective film 24 using the gate electrode 23 and the metal silicide film 27B as a mask. The energy is about 10 keV and the implantation dose is about 5 × 10 ¹⁴ / Cm ² The injection is selectively performed under the following injection conditions. After selective implantation of As ions, the temperature is raised to a high temperature of about 1025 ° C. at a rate of about 100 ° C./second, and a rapid heat treatment is performed to maintain this temperature for about 10 seconds. By activating, an N-type second high concentration diffusion layer 29 having a junction depth shallower than that of the first high concentration diffusion layer 26 is formed in the extension region of the semiconductor substrate 21.
[0061]
Thereafter, for example, B ions are implanted into the pocket diffusion layer 28 through the implantation protective film 24, the implantation energy is about 30 keV, and the implantation dose amount is about 1 × 10. ¹³ / Cm ² If the selective implantation is performed under these implantation conditions, the short channel effect can be further suppressed.
[0062]
As described above, according to the second embodiment, the N-type first high-concentration diffusion layer 26 is formed in the step shown in FIG. 4D, and the gate electrode 23 is formed in the step shown in FIG. A metal silicide film 27B is formed on the first high-concentration diffusion layer 26. Thereafter, in the process shown in FIG. 5C, when the P-type pocket diffusion layer 28 is formed by implanting In ions having a relatively large mass number using the gate electrode 23 and the metal silicide film 27B as a mask. The pocket diffusion layer 28 including the extension region thereon is selectively and positively amorphized by implantation damage due to In ions. Thus, since the pocket diffusion layer 28 is preamorphized prior to the formation of the second high-concentration diffusion layer 29 that is the extension diffusion layer, the excessive amount when forming the second high-concentration diffusion layer 29 is increased. Excess point defects that cause accelerated diffusion can be reduced. Furthermore, pre-amorphization can also suppress channeling that occurs during the implantation of As ions in the second high-concentration diffusion layer 29, so that the junction surface of the second high-concentration diffusion layer 29 can be made shallow and the short channel effect can be suppressed. it can.
[0063]
In addition, since the implantation protective film 24 made of a silicon oxide film is provided on the entire surface of the semiconductor substrate 21 after the gate electrode 23 is formed, the junction between the first high concentration diffusion layer 26 and the second high concentration diffusion layer 29 is formed. Each of the depths can be made shallow, and the As ions in the second high-concentration diffusion layer 29 can also be prevented from entering the region below the gate electrode 23.
[0064]
In addition, after forming the sidewall 25 and the metal silicide film 27B for performing the heat treatment at a relatively low temperature, the second high-concentration diffusion layer 29, which is the extension region, is formed. There is no exposure to low-temperature heat treatment, which also causes increased diffusion.
[0065]
Further, the first high-concentration diffusion layer 26 and the second high-concentration diffusion layer are formed by rapid thermal processing performed after ion implantation into the source / drain region shown in FIG. 4D and ion implantation into the extension region shown in FIG. Since the activation efficiency of each impurity ion of 29 is improved, the impurity concentration gradient of each junction surface between the substrate surface direction and the depth direction in each of the high concentration diffusion layers 26 and 29 is 1 × 10. ⁶ (atom / cm ^Three ) / μm or more profile can be realized.
[0066]
As described above, the activation efficiency, which is an index from the impurity implantation concentration to the impurity concentration after diffusion, increases, so that the driving capability of the transistor is improved and the second high-concentration diffusion layer 29 has a shallow junction depth. By having it, the short channel effect can be suppressed.
[0067]
In the second embodiment, rapid thermal processing is performed every time the first high-concentration diffusion layer 26 and the second high-concentration diffusion layer 29 are implanted. You may perform only.
[0068]
Further, in the second embodiment, as shown in FIG. 5C, when performing pocket implantation with In ions, the first high-concentration diffusion layer 26 is masked with the metal silicide film 27B. The vicinity of the surface of the first high concentration diffusion layer 26 is not amorphized. As a result, a dislocation loop does not occur at the interface between the amorphous layer and the crystal layer during the heat treatment for forming the second high-concentration diffusion layer 29, so that there is no possibility of junction leakage due to the dislocation loop.
[0069]
In addition, when the sidewall 25 in FIG. 4C is formed, the exposed portion of the implantation protective film 24 may be removed. However, in this case, as the As ion implantation conditions, for example, the implantation energy is about 30 keV, and the implantation dose is set so that the impurity profile of the first high-concentration diffusion layer 26 does not change significantly. About 3.6 × 10 ¹⁵ / Cm ² It is preferable that
[0070]
Further, although polycrystalline silicon is used for the gate electrode 23, polymetal may be used.
[0071]
Further, although the silicon nitride film is used for the sidewall 25, a TEOS film may be used. In the case where the sidewall 25 is formed of a TEOS film, it is preferable that the implantation protective film 24 be formed of a silicon nitride film.
[0072]
Further, although titanium silicide is used for the metal silicide film 27B, cobalt silicide may be used. More preferably, the metal film 27A to be silicided is preferably composed of a laminate made of titanium and cobalt or an alloy thereof. In this way, the heat resistance of the metal silicide film 27B is improved, so that a stable metal silicide film 27B can be formed.
[0073]
Although the MOS transistor is an N-channel MOS transistor, it may be a P-channel MOS transistor instead. In the case of a P-channel MOS transistor, it is preferable to use antimony (Sb) ions as N-type heavy ions implanted into the channel region and the pocket region.
[0074]
(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described below with reference to the drawings.
[0075]
6 (a) to 6 (d) and FIGS. 7 (a) to 7 (c) show cross-sectional structures in the order of steps of the MOS transistor manufacturing method according to the third embodiment.
[0076]
First, as shown in FIG. 6A, for example, indium (In) ions, which are P type impurity ions having a relatively large mass number, are implanted into a semiconductor substrate 31 made of P type silicon. About 200 KeV and implantation dose is about 1 × 10 ¹² / Cm ² Injection is performed under the following injection conditions. Subsequent to the ion implantation, the temperature is raised to a high temperature of about 1025 ° C. at a rate of about 100 ° C./second, and a rapid heat treatment is performed to maintain this temperature for a maximum of about 10 seconds. A P-type diffusion layer 31a to be a channel region is formed.
[0077]
Next, as shown in FIG. 6B, a gate insulating film 32 having a thickness of about 3 nm is formed on the semiconductor substrate 31, and a polycrystalline film having a thickness of about 250 nm is formed on the gate insulating film 32. A gate electrode 33 made of silicon is formed. Subsequently, an implantation protective film 34 made of a silicon oxide film having a thickness of about 5 nm is formed on the semiconductor substrate 31 over the entire surface including the gate electrode 33.
[0078]
Next, as shown in FIG. 6C, a silicon nitride film having a film pressure of about 50 nm is deposited on the entire surface of the implantation protection film 34 so as to cover the gate electrode 33, and the deposited silicon nitride film is applied to the deposited silicon nitride film. By performing anisotropic etching, a sidewall 35 made of a silicon nitride film is formed on the side surface of the gate electrode 33 on the gate length direction side.
[0079]
Next, as shown in FIG. 6D, the gate electrode 33 and the sidewall 35 are used as a mask, and for example, As ions, which are N-type impurity ions, are injected into the semiconductor substrate 31 through the implantation protective film 34 and the implantation energy is increased. About 30 KeV and implantation dose is about 3 × 10 ¹⁵ / Cm ² Injection is performed under the following injection conditions. After the implantation, the temperature is raised to a high temperature of about 1025 ° C. at a rate of about 100 ° C./second, and rapid heat treatment is performed to maintain this temperature for about 10 seconds. A first high concentration diffusion layer 36 is formed.
[0080]
Next, as shown in FIG. 7A, the upper surface portion of the gate electrode 33 and the upper surface portion of the first high-concentration diffusion layer 36 in the implantation protective film 34 are removed by etching, and subsequently, sputtering is used. A metal film 37A made of Ti having a thickness of, for example, about 30 nm is deposited on the semiconductor substrate 31 over the entire surface including the gate electrode 33 and the sidewalls 35.
[0081]
Next, as shown in FIG. 7B, a rapid heat treatment is performed at a heating temperature of about 680 ° C. for about 10 seconds, so that the deposited metal film 37A, the gate electrode 33, and the first of the semiconductor substrate 31 are formed. The joint surfaces with the high concentration diffusion layer 36 are caused to react with each other. Subsequently, the gate electrode 33, the first high-concentration diffusion layer 36, and the unreacted metal film are selectively etched and removed by a mixed solution of sulfuric acid, hydrogen peroxide, and water. Thereafter, by performing rapid thermal processing at a heating temperature of about 900 ° C. for about 10 seconds, a metal silicide film 37B having a thickness of about 50 nm is formed on the gate electrode 33 and the first high-concentration diffusion layer 36 in a self-aligning manner. Form.
[0082]
Next, as shown in FIG. 7C, the sidewall 35 is removed using a mixed solution of hydrofluoric acid and hot phosphoric acid, and then the side surface of the gate electrode 33 in the semiconductor substrate 31 using the gate electrode 33 as a mask. In the pocket region located on the lower side, P-type impurity ions having a relatively large mass number, for example, In ions are passed through the implantation protective film 34, the implantation energy is about 200 keV, and the implantation dose is about 5 × 10. ¹³ / Cm ² By implanting under the following implantation conditions, a P-type pocket diffusion layer 38 is formed. By performing pocket implantation with heavy ions, the pocket diffusion layer 38 including the extension region on the upper portion is selectively preamorphized.
[0083]
Next, as shown in FIG. 7D, for example, As ions, which are N-type impurity ions, are implanted through the implantation protective film 34 into the semiconductor substrate 31 using the gate electrode 33 and the metal silicide film 37B as a mask. The energy is about 10 keV and the implantation dose is about 5 × 10 ¹⁴ / Cm ² The injection is selectively performed under the following injection conditions. After the As ions are implanted, the temperature is raised to a high temperature of about 1025 ° C. at a rate of about 100 ° C./second, and a rapid heat treatment is performed to maintain this temperature for about 10 seconds to activate the implanted As ions. Thus, an N-type second high concentration diffusion layer 39 having a junction depth shallower than that of the first high concentration diffusion layer 36 is formed in the extension region of the semiconductor substrate 31.
[0084]
Thereafter, for example, B ions are implanted into the pocket diffusion layer 38 through the implantation protective film 34, the implantation energy is about 30 keV, and the implantation dose is about 1 × 10 × 10. ¹³ / Cm ² If the selective implantation is performed under these implantation conditions, the short channel effect can be further suppressed.
[0085]
As described above, according to the third embodiment, the N-type first high-concentration diffusion layer 36 is formed in the step shown in FIG. 6D, and the gate electrode 33 is formed in the step shown in FIG. A metal silicide film 37B is formed on the first high-concentration diffusion layer 36. Thereafter, in the step shown in FIG. 7C, when forming the P-type pocket diffusion layer 38 by implanting In ions having a relatively large mass number using the gate electrode 33 and the metal silicide film 37B as a mask, The pocket diffusion layer 38 including the extension region thereon is selectively and positively amorphized by implantation damage due to In ions. As described above, since the pocket diffusion layer 38 is preamorphized before the second high concentration diffusion layer 39 which is the extension diffusion layer is formed, it is excessive when the second high concentration diffusion layer 39 is formed. Excess point defects that cause accelerated diffusion can be reduced. Furthermore, pre-amorphization can also suppress channeling that occurs during the implantation of As ions in the second high-concentration diffusion layer 39, so that the junction surface of the second high-concentration diffusion layer 39 can be shallowed and the short channel effect can be suppressed. it can.
[0086]
In addition, since the implantation protective film 34 made of a silicon oxide film is provided on the entire surface of the semiconductor substrate 31 after the gate electrode 33 is formed, the junction between the first high concentration diffusion layer 36 and the second high concentration diffusion layer 39 is formed. Each of the depths can be made shallower, and As ions in the second high-concentration diffusion layer 39 can be prevented from entering the region below the gate electrode 33.
[0087]
In addition, the second high-concentration diffusion layer 39 is excessively formed in order to form the second high-concentration diffusion layer 39 that is the extension region after forming the sidewall 35 and the metal silicide film 37B that perform the heat treatment at a relatively low temperature. There is no exposure to low-temperature heat treatment, which also causes increased diffusion.
[0088]
In addition, as a feature of the third embodiment, In ions having a relatively large mass number are used as impurity ions forming the P-type diffusion layer 31a that is a channel region. Since the impurity concentration is small and a steep impurity concentration distribution can be formed in a region away from the region in the vicinity of the surface, miniaturization can be achieved without reducing the driving force of the transistor. In addition, since the rapid heat treatment is performed after the heavy ions are implanted into the channel region, crystal damage due to In ions of the semiconductor substrate 31 can be reliably and quickly recovered.
[0089]
Further, the first high-concentration diffusion layer 36 and the second high-concentration diffusion layer are formed by rapid thermal processing performed after ion implantation into the source / drain region shown in FIG. 6D and ion implantation into the extension region shown in FIG. Since the activation efficiency of each impurity ion of 39 is improved, the impurity concentration gradient of each junction surface between the substrate surface direction and the depth direction in each of the high concentration diffusion layers 36, 39 is 1 × 10. ⁶ (atom / cm ^Three ) / μm or more profile can be realized.
[0090]
As described above, the activation efficiency which is an index from the impurity implantation concentration to the impurity concentration after diffusion increases, so that the driving capability of the transistor is improved and the second high-concentration diffusion layer 39 has a shallow junction depth. By having it, the short channel effect can be suppressed.
[0091]
In the third embodiment, the rapid thermal treatment is performed every time the first high-concentration diffusion layer 36 and the second high-concentration diffusion layer 39 are implanted. You may perform only.
[0092]
Further, in the third embodiment, as shown in FIG. 7C, when performing pocket implantation with In ions, the first high-concentration diffusion layer 36 is masked with the metal silicide film 37B. The vicinity of the surface of the first high concentration diffusion layer 36 is not amorphized. As a result, a dislocation loop does not occur at the interface between the amorphous layer and the crystal layer during the heat treatment for forming the second high-concentration diffusion layer 39, so that there is no possibility of junction leakage due to the dislocation loop.
[0093]
Further, the exposed portion of the implantation protective film 34 may be removed when forming the sidewall 35 in FIG. However, in this case, as the As ion implantation conditions, for example, the implantation energy is about 30 keV and the implantation dose amount so that the impurity profile of the first high-concentration diffusion layer 36 does not change significantly before the removal. About 3.6 × 10 ¹⁵ / Cm ² It is preferable that
[0094]
Further, although polycrystalline silicon is used for the gate electrode 33, polymetal may be used.
[0095]
Further, although the silicon nitride film is used for the sidewall 35, a TEOS film may be used. In the case where the sidewall 35 is formed of a TEOS film, it is preferable that the injection protective film 34 is formed of a silicon nitride film.
[0096]
Further, although titanium silicide is used for the metal silicide film 37B, cobalt silicide may be used. More preferably, the metal film 37A to be silicided is preferably composed of a laminate made of titanium and cobalt or an alloy thereof. In this way, the heat resistance of the metal silicide film 37B is improved, so that a stable metal silicide film 37B can be formed.
[0097]
Although the MOS transistor is an N-channel MOS transistor, it may be a P-channel MOS transistor instead. In the case of a P-channel MOS transistor, it is preferable to use antimony (Sb) ions as N-type heavy ions implanted into the channel region and the pocket region.
[0098]
【The invention's effect】
According to the semiconductor device manufacturing method of the present invention, since the extension region is preamorphized, excess point defects that cause excessively accelerated diffusion are reduced in the extension region. In addition, after forming and removing the sidewall, the second high concentration diffusion layer is formed to form the second high concentration diffusion layer that is the extension region in the first high concentration diffusion layer that is the source / drain region. Therefore, the second high-concentration diffusion layer can be formed into a shallow junction. Furthermore, since the impurity implantation of the first high concentration diffusion layer is performed through the implantation protective film, the first high concentration diffusion layer can be formed into a shallow junction. Thereby, the parasitic resistance of the first and second source / drain regions is reduced, and miniaturization can be realized without reducing the driving force of the semiconductor device.
[Brief description of the drawings]
FIGS. 1A to 1D are cross-sectional structural views showing a manufacturing method of a MOS semiconductor device according to a first embodiment of the present invention.
FIGS. 2A to 2D are structural cross-sectional views in order of steps showing a method for manufacturing a MOS type semiconductor device according to the first embodiment of the present invention. FIGS.
FIGS. 3A and 3B show impurity concentration distributions of the MOS type semiconductor device according to the first embodiment of the present invention, and FIG. 3A is a graph showing impurity concentrations in the depth direction of the substrate. (B) is a graph showing the impurity concentration in the substrate surface direction.
FIGS. 4A to 4D are cross-sectional views in order of steps showing a method for manufacturing a MOS type semiconductor device according to a second embodiment of the present invention.
FIGS. 5A to 5D are process cross-sectional views illustrating a method for manufacturing a MOS type semiconductor device according to a second embodiment of the present invention in order of processes.
FIGS. 6A to 6D are cross-sectional views in order of steps showing a method for manufacturing a MOS type semiconductor device according to a third embodiment of the present invention.
FIGS. 7A to 7D are structural cross-sectional views in order of steps showing a method for manufacturing a MOS type semiconductor device according to a third embodiment of the present invention. FIGS.
FIGS. 8A to 8E are cross-sectional views illustrating a conventional MOS transistor manufacturing method in the order of steps.
[Explanation of symbols]
11 Semiconductor substrate
11a P-type diffusion layer
12 Gate insulation film
13 Gate electrode
14 Injection protective layer
15 First sidewall
16 First high-concentration diffusion layer
17 Pocket diffusion layer
18 Second high-concentration diffusion layer
19 Second sidewall
20 Metal silicide film
21 Semiconductor substrate
21a P-type diffusion layer
22 Gate insulation film
23 Gate electrode
24 Injection protective layer
25 sidewall
26 First high-concentration diffusion layer
27A metal film
27B Metal silicide film
28 Pocket diffusion layer
29 Second high concentration diffusion layer
31 Semiconductor substrate
31a P-type diffusion layer
32 Gate insulation film
33 Gate electrode
34 Injection protective layer
35 sidewall
36 First high-concentration diffusion layer
37A metal film
37B Metal silicide film
38 Pocket diffusion layer
39 Second high-concentration diffusion layer

Claims (8)

Forming a first conductivity type diffusion layer to be a channel region by implanting a first conductivity type first impurity into the upper portion of the semiconductor substrate;
Forming a gate electrode on the semiconductor substrate via a gate insulating film;
Forming an implantation protective film made of an insulating film over the entire surface including the gate electrode on the semiconductor substrate;
Forming a sidewall on the side surface of the gate electrode via the injection protective film;
A second conductivity type second impurity is implanted into the semiconductor substrate through the implantation protective film using the gate electrode and the sidewall as a mask, thereby forming a second conductivity type first high concentration diffusion layer. Process,
After removing the sidewall, a third impurity of the first conductivity type is implanted through the implantation protective film into an extension region located below the side surface of the gate electrode in the semiconductor substrate using the gate electrode as a mask. A process of making the extension region amorphous;
After the step of amorphizing the extension region, a fourth impurity of the second conductivity type is implanted into the semiconductor substrate through the implantation protective film using the gate electrode as a mask, and a heat treatment is performed. Forming a second conductivity type second high-concentration diffusion layer having a junction depth shallower than that of the first high-concentration diffusion layer.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the first high-concentration diffusion layer includes a step of performing a heat treatment on the semiconductor substrate into which the second impurity has been implanted. Method. The semiconductor substrate is made of silicon at least at the top,
After the step of forming the second high concentration diffusion layer,
Forming a sidewall made of an insulating film on a side surface of the gate electrode;
After removing the exposed portion of the implantation protective film on the semiconductor substrate, a metal film is deposited on the entire surface of the semiconductor substrate including the gate electrode, and the deposited metal film, the gate electrode and the semiconductor substrate, The method further comprises the step of forming a silicide film in a self-aligned manner on the gate electrode and the second high-concentration diffusion layer by causing the bonding surfaces of the first and second layers to react with each other. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. The method for manufacturing a semiconductor device according to claim 1, wherein the third impurity is indium ion or antimony ion . Forming a first conductivity type diffusion layer serving as a channel region by injecting a first impurity of the first conductivity type into the upper portion of the semiconductor substrate made of silicon at least at the top;
Forming a gate electrode on the semiconductor substrate via a gate insulating film;
Forming an implantation protective film made of an insulating film over the entire surface including the gate electrode on the semiconductor substrate;
Forming a sidewall made of an insulating film on the side surface of the gate electrode through the injection protective film;
A second conductivity type second impurity is implanted into the semiconductor substrate through the implantation protective film using the gate electrode and the sidewall as a mask, thereby forming a second conductivity type first high concentration diffusion layer. Process,
After removing the exposed portion of the implantation protective film on the semiconductor substrate, a metal film is deposited on the entire surface of the semiconductor substrate including the gate electrode, and the deposited metal film, the gate electrode and the semiconductor substrate, Forming a silicide film in a self-aligned manner on the gate electrode and the first high-concentration diffusion layer by reacting the bonding surfaces of
After removing the sidewalls, a third impurity of the first conductivity type is implanted into the extension protective film in the extension region located below the side surface of the gate electrode in the semiconductor substrate using the gate electrode and the silicide film as a mask. Selectively amorphizing the extension region by implanting through;
After the step of selectively amorphizing the extension region, a fourth impurity of the second conductivity type is implanted into the semiconductor substrate through the implantation protective film using the gate electrode as a mask, and a heat treatment is performed. Forming a second high-concentration diffusion layer of the second conductivity type having a junction depth shallower than that of the first high-concentration diffusion layer in the extension region. Method.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the first high-concentration diffusion layer includes a step of performing a heat treatment on the semiconductor substrate into which the second impurity has been implanted. Method.   The method of manufacturing a semiconductor device according to claim 5, wherein the metal film is made of a laminate made of titanium and cobalt or an alloy of titanium and cobalt. The method for manufacturing a semiconductor device according to claim 5, wherein the third impurity is indium ion or antimony ion .

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